On 18.05.2023 05:41, Zhang, Jun wrote:
> This patch aims to add Intel FRED and LKGS instructions.
>
> The information is based on newly released
> Intel Flexible Return and Event Delivery(FRED).
>
> The document comes following:
> https://cdrdv2.intel.com/v1/dl/getContent/678938
You say "newly released", but this link points to a document from May
2022.
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -494,6 +494,7 @@ if [gas_32_check] then {
> run_dump_test "raoint"
> run_dump_test "raoint-intel"
> run_list_test "amx-complex-inval"
> + run_dump_test "fred"
According to my reading of the spec the new insns aren't legal outside
of 64-bit mode. That's not even "long mode", seeing the spec saying
"FRED transitions also prevents entry to compatibility mode in ring 0."
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-lkgs.s
> @@ -0,0 +1,21 @@
> +# Check 64bit LKGS instructions
> +
> + .allow_index_reg
> + .text
> +_start:
> + lkgs %r12 #LKGS
> + lkgs %r12w #LKGS
> + lkgsw %r12w #LKGS
> + lkgs 0x10000000(%rbp, %r14, 8) #LKGS
> + lkgs (%r9) #LKGS
> + lkgs 254(%rcx) #LKGS Disp32(fe000000)
> + lkgs -256(%rdx) #LKGS Disp32(00ffffff)
> +
> +.intel_syntax noprefix
> + lkgs r12 #LKGS
> + lkgs r12w #LKGS
> + lkgsw r12w #LKGS
Nit: Indentation (want to use tab here just like everywhere else).
> @@ -2755,7 +2758,7 @@ static const struct dis386 reg_table[][8] = {
> { "ltr", { Ew }, 0 },
> { "verr", { Ew }, 0 },
> { "verw", { Ew }, 0 },
> - { Bad_Opcode },
> + { X86_64_TABLE (X86_64_0F00_REG_6) },
> { Bad_Opcode },
> },
> /* REG_0F01 */
> @@ -2996,6 +2999,14 @@ static const struct dis386 prefix_table[][4] = {
> { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
> },
>
> + /* PREFIX_0F00_REG_6_X86_64 */
> + {
> + { Bad_Opcode },
> + { Bad_Opcode },
> + { Bad_Opcode },
> + { "lkgs", { Ew }, 0 },
> + },
While consistent with LTR et al (visible above), I question the use
of Ew here (and there). See below for the assembler side of things,
which this would better be consistent with.
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3351,3 +3351,16 @@ aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64
> axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>
> // RAO-INT instructions end.
> +
> +// FRED instructions.
> +
> +erets, 0xf20f01ca, FRED, NoSuf, {}
> +eretu, 0xf30f01ca, FRED, NoSuf, {}
As per above, I think this lacks |x64 (and the disassembler parts would
then need adjusting accordingly).
> +//FRED instructions end.
Nit: Missing blank.
> +// LKGS instructions.
> +
> +lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|NoRex64, { Reg16|Reg32|Reg64|Word|Unspecified|BaseIndex }
Word is redundant with Reg16, and once omitted you'll notice how what you
have doesn't achieve the intended effect. Please take other similar insns
as reference. Some were split not all that long ago, to properly express
both their register forms (allowing all three widths) and their memory
ones (allowing only 16-bit operands). The set of permitted suffixes also
varies between both.
Jan
@@ -1,5 +1,9 @@
-*- text -*-
+* Add support for Intel FRED instructions.
+
+* Add support for Intel LKGS instructions.
+
* Add support for Intel AMX-COMPLEX instructions.
* Add SME2 support to the AArch64 port.
@@ -1141,6 +1141,8 @@ static const arch_entry cpu_arch[] =
SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
SUBARCH (rao_int, RAO_INT, RAO_INT, false),
SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
+ SUBARCH (fred, FRED, ANY_FRED, false),
+ SUBARCH (lkgs, LKGS, ANY_LKGS, false),
};
#undef SUBARCH
@@ -205,6 +205,8 @@ accept various extension mnemonics. For example,
@code{msrlist},
@code{avx_ne_convert},
@code{rao_int},
+@code{fred},
+@code{lkgs},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1634,6 +1636,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.avx_ne_convert} @tab @samp{.rao_int}
+@item @samp{.fred} @tab @samp{.lkgs}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
new file mode 100644
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw -Mintel
+#name: i386 FRED insns (Intel disassembly)
+#source: fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
new file mode 100644
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: i386 FRED insns
+#source: fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
new file mode 100644
@@ -0,0 +1,11 @@
+# Check 32bit FRED instructions
+
+ .allow_index_reg
+ .text
+_start:
+ erets #FRED
+ eretu #FRED
+
+.intel_syntax noprefix
+ erets #FRED
+ eretu #FRED
@@ -494,6 +494,7 @@ if [gas_32_check] then {
run_dump_test "raoint"
run_dump_test "raoint-intel"
run_list_test "amx-complex-inval"
+ run_dump_test "fred"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
@@ -1189,6 +1190,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-amx-complex-intel"
run_dump_test "x86-64-amx-complex-bad"
run_list_test "x86-64-amx-complex-inval"
+ run_dump_test "x86-64-fred"
+ run_dump_test "x86-64-lkgs"
+ run_list_test "x86-64-lkgs-inval"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
new file mode 100644
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 FRED insns (Intel disassembly)
+#source: x86-64-fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
new file mode 100644
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86_64 FRED insns
+#source: x86-64-fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
new file mode 100644
@@ -0,0 +1,11 @@
+# Check 64bit FRED instructions
+
+ .allow_index_reg
+ .text
+_start:
+ erets #FRED
+ eretu #FRED
+
+.intel_syntax noprefix
+ erets #FRED
+ eretu #FRED
new file mode 100644
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 LKGS insns (Intel disassembly)
+#source: x86-64-lkgs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs WORD PTR \[rdx-0x100\]
+#pass
new file mode 100644
@@ -0,0 +1,8 @@
+.* Assembler messages:
+.*:5: Error: invalid instruction suffix for `lkgs'
+.*:6: Error: invalid instruction suffix for `lkgs'
+.*:7: Error: invalid instruction suffix for `lkgs'
+.*:8: Error: invalid instruction suffix for `lkgs'
+.*:11: Error: invalid instruction suffix for `lkgs'
+.*:12: Error: invalid instruction suffix for `lkgs'
+.*:13: Error: invalid instruction suffix for `lkgs'
new file mode 100644
@@ -0,0 +1,13 @@
+# Check illegal suffer usage in LKGS instructions
+
+ .text
+_start:
+ lkgsb %r12 #LKGS
+ lkgsl %r12 #LKGS
+ lkgss %r12 #LKGS
+ lkgsq %r12 #LKGS
+
+ .intel_syntax noprefix
+ lkgsb %r12 #LKGS
+ lkgsd %r12 #LKGS
+ lkgsq %r12 #LKGS
new file mode 100644
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dw
+#name: x86_64 LKGS insns
+#source: x86-64-lkgs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\)
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\)
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs %r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs 0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs \(%r9\)
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs 0xfe\(%rcx\)
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs -0x100\(%rdx\)
+#pass
new file mode 100644
@@ -0,0 +1,21 @@
+# Check 64bit LKGS instructions
+
+ .allow_index_reg
+ .text
+_start:
+ lkgs %r12 #LKGS
+ lkgs %r12w #LKGS
+ lkgsw %r12w #LKGS
+ lkgs 0x10000000(%rbp, %r14, 8) #LKGS
+ lkgs (%r9) #LKGS
+ lkgs 254(%rcx) #LKGS Disp32(fe000000)
+ lkgs -256(%rdx) #LKGS Disp32(00ffffff)
+
+.intel_syntax noprefix
+ lkgs r12 #LKGS
+ lkgs r12w #LKGS
+ lkgsw r12w #LKGS
+ lkgs WORD PTR [rbp+r14*8+0x10000000] #LKGS
+ lkgs WORD PTR [r9] #LKGS
+ lkgs WORD PTR [rcx+254] #LKGS Disp32(fe000000)
+ lkgs WORD PTR [rdx-256] #LKGS Disp32(00ffffff)
@@ -1025,7 +1025,9 @@ enum
enum
{
PREFIX_90 = 0,
+ PREFIX_0F00_REG_6_X86_64,
PREFIX_0F01_REG_0_MOD_3_RM_6,
+ PREFIX_0F01_REG_1_RM_2,
PREFIX_0F01_REG_1_RM_4,
PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6,
@@ -1310,6 +1312,7 @@ enum
X86_64_E8,
X86_64_E9,
X86_64_EA,
+ X86_64_0F00_REG_6,
X86_64_0F01_REG_0,
X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
@@ -2755,7 +2758,7 @@ static const struct dis386 reg_table[][8] = {
{ "ltr", { Ew }, 0 },
{ "verr", { Ew }, 0 },
{ "verw", { Ew }, 0 },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F00_REG_6) },
{ Bad_Opcode },
},
/* REG_0F01 */
@@ -2996,6 +2999,14 @@ static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
+ /* PREFIX_0F00_REG_6_X86_64 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "lkgs", { Ew }, 0 },
+ },
+
/* PREFIX_0F01_REG_0_MOD_3_RM_6 */
{
{ "wrmsrns", { Skip_MODRM }, 0 },
@@ -3004,6 +3015,14 @@ static const struct dis386 prefix_table[][4] = {
{ X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
},
+ /* PREFIX_0F01_REG_1_RM_2 */
+ {
+ { "clac", { Skip_MODRM }, 0 },
+ { "eretu", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "erets", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F01_REG_1_RM_4 */
{
{ Bad_Opcode },
@@ -4371,6 +4390,12 @@ static const struct dis386 x86_64_table[][2] = {
{ "{l|}jmp{P|}", { Ap }, 0 },
},
+ /* X86_64_0F00_REG_6 */
+ {
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
+ },
+
/* X86_64_0F01_REG_0 */
{
{ "sgdt{Q|Q}", { M }, 0 },
@@ -8702,7 +8727,7 @@ static const struct dis386 rm_table[][8] = {
/* RM_0F01_REG_1 */
{ "monitor", { { OP_Monitor, 0 } }, 0 },
{ "mwait", { { OP_Mwait, 0 } }, 0 },
- { "clac", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
{ "stac", { Skip_MODRM }, 0 },
{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
{ PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
@@ -164,6 +164,8 @@ static const dependency isa_dependencies[] =
"AVX2" },
{ "AVX_NE_CONVERT",
"AVX2" },
+ { "FRED",
+ "LKGS" },
{ "AVX512F",
"AVX2" },
{ "AVX512CD",
@@ -362,6 +364,8 @@ static bitfield cpu_flags[] =
BITFIELD (MSRLIST),
BITFIELD (AVX_NE_CONVERT),
BITFIELD (RAO_INT),
+ BITFIELD (FRED),
+ BITFIELD (LKGS),
BITFIELD (MWAITX),
BITFIELD (CLZERO),
BITFIELD (OSPKE),
@@ -229,6 +229,10 @@ enum
CpuAVX_NE_CONVERT,
/* Intel RAO INT Instructions support required. */
CpuRAO_INT,
+ /* fred instruction required */
+ CpuFRED,
+ /* lkgs instruction required */
+ CpuLKGS,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -424,6 +428,8 @@ typedef union i386_cpu_flags
unsigned int cpumsrlist:1;
unsigned int cpuavx_ne_convert:1;
unsigned int cpurao_int:1;
+ unsigned int cpufred:1;
+ unsigned int cpulkgs:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -3351,3 +3351,16 @@ aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64
axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
// RAO-INT instructions end.
+
+// FRED instructions.
+
+erets, 0xf20f01ca, FRED, NoSuf, {}
+eretu, 0xf30f01ca, FRED, NoSuf, {}
+
+//FRED instructions end.
+
+// LKGS instructions.
+
+lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|NoRex64, { Reg16|Reg32|Reg64|Word|Unspecified|BaseIndex }
+
+// LKGS instructions end.