From patchwork Thu Mar 30 10:26:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 77071 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp1031958vqo; Thu, 30 Mar 2023 03:49:38 -0700 (PDT) X-Google-Smtp-Source: AKy350YCpJ8CmpxL/KN3D0HUjRNaZk+XXA1S4yd79kB0+fc88Jr1LJLUSyjyttRc/C8BRWtBOeyQ X-Received: by 2002:a17:906:aad3:b0:933:be1:8f4f with SMTP id kt19-20020a170906aad300b009330be18f4fmr23403225ejb.9.1680173378317; Thu, 30 Mar 2023 03:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1680173378; cv=none; d=google.com; s=arc-20160816; b=zENYgLcMmXLiHt66iyi5T8neU+SjUmnvZ6fmd204r82A5kfPx4Zq3puQ/44p1gSnwM 0F+hL4AQ+/GaMFESP5tE0R1db+huLrZMQO/CcSM2ad21kaUFwIYN7gVo9ylv1gFXDp64 nco0gfL8ZFCstWcTMG13V9nyHE133LdEmmT9v/Mw4pO2CwLiKMz3egEbZeLzkyuQGYdI hfHj1Qny+n9Ro0XPuMah0abl5XefcDgaqsBtlLwwRD0UPT7m1Zs2/QxT1Xz6t0OZFqIe y1TWiO0ahnqyvnL7BcKDIz34HelNsAuNf6ZGrYXrRfMJu2PfPGTkiouXnvZPfI0xF/d/ yUwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=hK4L+wds7SS352TYVYWU2g8A/hZglkxlDGgHEdBpiW0=; b=KDg7LEe96gYLHJigxXrl5ccriq35dHCEDTKO4dNZcO8MG7YQKxa1F7AJhaLKk7Lvrb PGveHxGftIYs8p/nbHF+2g3EknN6/RdvKmGSeoBYQQ08HOuObyDO5nP4D2vIrOsqsejl 5koVkdHCXsqXq2RsLW4DVPLPS90QQES4dLnB0bY/d9ZB/3Wfd1giJ6DKsEgvBGEcGijM YIU8I6ghyaC+6cNlkVS6miQzXqVxAGlzU+6a3rFa/DdrNmd81FK3L3uwu4DWnBqi9dOF EeBFEfVQ6wb64JNQfFZ/GCyB55abPltnA7McwGEfHarlX4X5uA66NPG9We1y1ald/meg hFDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=X7ssiqnH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id um7-20020a170906cf8700b0092bc3318c92si32586338ejb.682.2023.03.30.03.49.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=X7ssiqnH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 95F8F395200B for ; Thu, 30 Mar 2023 10:35:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 95F8F395200B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172551; bh=hK4L+wds7SS352TYVYWU2g8A/hZglkxlDGgHEdBpiW0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=X7ssiqnHEhoIIEPdf0gWtrDw6Nexs0UjhDi9PVoBocDcYq1jmYynLs/048d3T8pq5 Mw0ZU0uooCbgRWywjtRJg90w3REg2SVUMMXve2Z/P28dIsXshR9vt29xduB3UdjMP1 MiZaHdN/bfFnjlPRkSvatGi7zymHWrlUUUNOymTM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 82CC93896C10 for ; Thu, 30 Mar 2023 10:27:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 82CC93896C10 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B30701650; Thu, 30 Mar 2023 03:27:45 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E9A833F663; Thu, 30 Mar 2023 03:27:00 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 10/31] aarch64: Add the SME2 ZT0 instructions Date: Thu, 30 Mar 2023 11:26:25 +0100 Message-Id: <20230330102646.3327818-11-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102646.3327818-1-richard.sandiford@arm.com> References: <20230330102646.3327818-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-31.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789480445613477?= X-GMAIL-MSGID: =?utf-8?q?1761789480445613477?= SME2 adds lookup table instructions for quantisation. They use a new lookup table register called ZT0. LUTI2 takes an unsuffixed SVE vector index of the form Zn[], which is the first time that this syntax has been used. --- gas/config/tc-aarch64.c | 73 +- gas/testsuite/gas/aarch64/sme-4-illegal.l | 6 +- gas/testsuite/gas/aarch64/sme2-8-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-8-invalid.l | 208 +++++ gas/testsuite/gas/aarch64/sme2-8-invalid.s | 116 +++ gas/testsuite/gas/aarch64/sme2-8-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-8-noarch.l | 104 +++ gas/testsuite/gas/aarch64/sme2-8.d | 112 +++ gas/testsuite/gas/aarch64/sme2-8.s | 124 +++ gas/testsuite/gas/aarch64/sve-invalid.l | 8 + gas/testsuite/gas/aarch64/sve-invalid.s | 1 + include/opcode/aarch64.h | 11 + opcodes/aarch64-asm-2.c | 25 +- opcodes/aarch64-asm.c | 12 + opcodes/aarch64-dis-2.c | 902 ++++++++++++--------- opcodes/aarch64-dis.c | 15 + opcodes/aarch64-opc-2.c | 9 + opcodes/aarch64-opc.c | 59 +- opcodes/aarch64-opc.h | 19 +- opcodes/aarch64-tbl.h | 42 + 20 files changed, 1443 insertions(+), 409 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.l create mode 100644 gas/testsuite/gas/aarch64/sme2-8-invalid.s create mode 100644 gas/testsuite/gas/aarch64/sme2-8-noarch.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8-noarch.l create mode 100644 gas/testsuite/gas/aarch64/sme2-8.d create mode 100644 gas/testsuite/gas/aarch64/sme2-8.s diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index a433925e320..652fd4e6ff3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -312,6 +312,7 @@ struct reloc_entry BASIC_REG_TYPE(ZAT) /* za[0-15] (ZA tile) */ \ BASIC_REG_TYPE(ZATH) /* za[0-15]h (ZA tile horizontal slice) */ \ BASIC_REG_TYPE(ZATV) /* za[0-15]v (ZA tile vertical slice) */ \ + BASIC_REG_TYPE(ZT0) /* zt0 */ \ /* Typecheck: any 64-bit int reg (inc SP exc XZR). */ \ MULTI_REG_TYPE(R64_SP, REG_TYPE(R_64) | REG_TYPE(SP_64)) \ /* Typecheck: same, plus SVE registers. */ \ @@ -483,11 +484,11 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen) if (mask == reg_type_masks[REG_TYPE_VZP]) return N_("expected a vector or predicate register at operand %d"); - /* ZA-related registers. */ + /* SME-related registers. */ if (mask == reg_type_masks[REG_TYPE_ZA]) return N_("expected a ZA array vector at operand %d"); - if (mask == reg_type_masks[REG_TYPE_ZA_ZAT]) - return N_("expected 'za' or a ZA tile at operand %d"); + if (mask == (reg_type_masks[REG_TYPE_ZA_ZAT] | reg_type_masks[REG_TYPE_ZT0])) + return N_("expected ZT0 or a ZA mask at operand %d"); if (mask == reg_type_masks[REG_TYPE_ZAT]) return N_("expected a ZA tile at operand %d"); if (mask == reg_type_masks[REG_TYPE_ZATHV]) @@ -1279,7 +1280,10 @@ parse_typed_reg (char **ccp, aarch64_reg_type type, if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '[')) { /* Reject Sn[index] syntax. */ - if (reg->type != REG_TYPE_PN && !is_typed_vecreg) + if (reg->type != REG_TYPE_Z + && reg->type != REG_TYPE_PN + && reg->type != REG_TYPE_ZT0 + && !is_typed_vecreg) { first_error (_("this type of register can't be indexed")); return NULL; @@ -6722,6 +6726,12 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: reg_type = REG_TYPE_Z; goto vector_reg_index; @@ -6735,14 +6745,23 @@ parse_operands (char *str, const aarch64_opcode *opcode) reg = aarch64_reg_parse (&str, reg_type, &vectype); if (!reg) goto failure; - if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX)) + if (!(vectype.defined & NTA_HASINDEX)) goto failure; + if (reg->type == REG_TYPE_Z && vectype.type == NT_invtype) + /* Unqualified Zn[index] is allowed in LUTI2 instructions. */ + info->qualifier = AARCH64_OPND_QLF_NIL; + else + { + if (vectype.type == NT_invtype) + goto failure; + info->qualifier = vectype_to_qualifier (&vectype); + if (info->qualifier == AARCH64_OPND_QLF_NIL) + goto failure; + } + info->reglane.regno = reg->number; info->reglane.index = vectype.index; - info->qualifier = vectype_to_qualifier (&vectype); - if (info->qualifier == AARCH64_OPND_QLF_NIL) - goto failure; break; case AARCH64_OPND_SVE_ZnxN: @@ -7740,6 +7759,39 @@ parse_operands (char *str, const aarch64_opcode *opcode) goto failure; break; + case AARCH64_OPND_SME_ZT0: + po_reg_or_fail (REG_TYPE_ZT0); + break; + + case AARCH64_OPND_SME_ZT0_INDEX: + reg = aarch64_reg_parse (&str, REG_TYPE_ZT0, &vectype); + if (!reg || vectype.type != NT_invtype) + goto failure; + if (!(vectype.defined & NTA_HASINDEX)) + { + set_syntax_error (_("missing register index")); + goto failure; + } + info->imm.value = vectype.index; + break; + + case AARCH64_OPND_SME_ZT0_LIST: + if (*str != '{') + { + set_expected_reglist_error (REG_TYPE_ZT0, parse_reg (&str)); + goto failure; + } + str++; + if (!parse_typed_reg (&str, REG_TYPE_ZT0, &vectype, PTR_IN_REGLIST)) + goto failure; + if (*str != '}') + { + set_syntax_error (_("expected '}' after ZT0")); + goto failure; + } + str++; + break; + case AARCH64_OPND_SME_PNn3_INDEX1: case AARCH64_OPND_SME_PNn3_INDEX2: reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype); @@ -8462,7 +8514,10 @@ static const reg_entry reg_names[] = { REGSET16S (za, h, ZATH), REGSET16S (ZA, H, ZATH), /* SME ZA tile registers (vertical slice). */ - REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV) + REGSET16S (za, v, ZATV), REGSET16S (ZA, V, ZATV), + + /* SME2 ZT0. */ + REGDEF (zt0, 0, ZT0), REGDEF (ZT0, 0, ZT0) }; #undef REGDEF diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l index 86e315476dd..a9e98524067 100644 --- a/gas/testsuite/gas/aarch64/sme-4-illegal.l +++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l @@ -22,11 +22,11 @@ [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}' [^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {za_}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zaX}' [^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}' -[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}' +[^:]*:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zax}' [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}' [^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}' [^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}' diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.d b/gas/testsuite/gas/aarch64/sme2-8-invalid.d new file mode 100644 index 00000000000..d9f587d6019 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: sme2-8-invalid.s +#error_output: sme2-8-invalid.l diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.l b/gas/testsuite/gas/aarch64/sme2-8-invalid.l new file mode 100644 index 00000000000..afea8bb6735 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.l @@ -0,0 +1,208 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero 0' +[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `zero zt0' +[^ :]+:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {foo}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {zt}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {x0}' +[^ :]+:[0-9]+: Error: expected ZT0 or a ZA mask at operand 1 -- `zero {z0}' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0\.b}' +[^ :]+:[0-9]+: Error: expected '}' after ZT0 at operand 1 -- `zero {zt0,zt0}' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `movt 0,zt0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `movt x0,0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0,x0' +[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za\[0\],x0' +[^ :]+:[0-9]+: Error: unexpected register type at operand 1 -- `movt za0\[0\],x0' +[^ :]+:[0-9]+: Error: bad expression at operand 1 -- `movt zt0\[#0\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[-1\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[1\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[2\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[4\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[7\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[49\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[50\],x0' +[^ :]+:[0-9]+: Error: byte index must be a multiple of 8 at operand 1 -- `movt zt0\[52\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[57\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[64\],x0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 56 at operand 1 -- `movt zt0\[1<<32\],x0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0\.b\[0\],x0' +[^ :]+:[0-9]+: Error: missing register index at operand 1 -- `movt zt0/z\[0\],x0' +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],sp' +[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],w0' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: movt zt0\[0\], x0 +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],wsp' +[^ :]+:[0-9]+: Error: operand mismatch -- `movt zt0\[0\],wzr' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: movt zt0\[0\], xzr +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `movt zt0\[0\],0' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr 0,\[x0\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,0' +[^ :]+:[0-9]+: Error: operand 2 must be an address with base register \(no offset\) -- `ldr zt0,\[x0,#0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr Zt0,\[x0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ldr zT0,\[x0\]' +[^ :]+:[0-9]+: Error: '\]' expected at operand 2 -- `ldr zt0,\[x0,#0,mul vl\]' +[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[w0\]' +[^ :]+:[0-9]+: Error: missing offset in the pre-indexed address at operand 2 -- `ldr zt0,\[x0\]!' +[^ :]+:[0-9]+: Error: invalid base register at operand 2 -- `ldr zt0,\[xzr\]' +[^ :]+:[0-9]+: Error: expected a 64-bit base register at operand 2 -- `ldr zt0,\[wsp\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x0,xzr\]' +[^ :]+:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldr zt0,\[x1,x2\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 15 at operand 3 -- `luti2 z0\.b,zt0,z0\[16\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.b,zt0,z0\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.d,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 z0\.q,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,zt0' +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti2 0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti2 z0\.b,0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti2 z0\.b,zt0,0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.b-z2\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z1\.b},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.h-z1\.h},zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti2 {z0\.h-z1\.h},zt0,z0\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z1\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z1\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z1\.s-z4\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z2\.s-z5\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti2 {z3\.s-z6\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.s-z3\.s},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti2 {z0\.b-z3\.b},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.b-z3\.b},zt0,z0\.b\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti2 {z0\.b-z3\.b},zt0,z0\[4\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.d-z3\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti2 {z0\.q-z3\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `luti4 0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected a register at operand 2 -- `luti4 z0\.b,0,z0\[0\]' +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.b,zt0,0' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `luti4 z0\.h,zt0,z0\[8\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.h,zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.d,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 z0\.q,zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 z0\.b, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 z0\.h, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 z0\.s, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `luti4 z0\.h,zt0,zt0' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.h-z2\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.h-z1\.h},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.h-z1\.h},zt0,z0\.h\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `luti4 {z0\.h-z1\.h},zt0,z0\[4\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z1\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z1\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z1\.s-z4\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z2\.s-z5\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `luti4 {z3\.s-z6\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},z0,z0\[0\]' +[^ :]+:[0-9]+: Error: unexpected register type at operand 2 -- `luti4 {z0\.s-z3\.s},za,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.s-z3\.s},zt0,z0\.s\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[-1\]' +[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `luti4 {z0\.s-z3\.s},zt0,z0\[2\]' +[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `luti4 {z0\.b-z3\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.d-z3\.d},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^ :]+:[0-9]+: Error: operand mismatch -- `luti4 {z0\.q-z3\.q},zt0,z0\[0\]' +[^ :]+:[0-9]+: Info: did you mean this\? +[^ :]+:[0-9]+: Info: luti4 {z0\.b-z3\.b}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: other valid variant\(s\): +[^ :]+:[0-9]+: Info: luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^ :]+:[0-9]+: Info: luti4 {z0\.s-z3\.s}, zt0, z0\[0\] diff --git a/gas/testsuite/gas/aarch64/sme2-8-invalid.s b/gas/testsuite/gas/aarch64/sme2-8-invalid.s new file mode 100644 index 00000000000..a9712c7aa13 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-invalid.s @@ -0,0 +1,116 @@ + zero 0 + + zero zt0 + zero { + zero { foo } + zero { zt } + zero { x0 } + zero { z0 } + zero { zt0 + zero { zt0.b } + zero { zt0, zt0 } + + movt 0, zt0[0] + movt x0, 0 + + movt zt0, x0 + movt za[0], x0 + movt za0[0], x0 + movt zt0[#0], x0 + movt zt0[-1], x0 + movt zt0[1],x0 + movt zt0[2],x0 + movt zt0[4],x0 + movt zt0[7],x0 + movt zt0[49],x0 + movt zt0[50],x0 + movt zt0[52],x0 + movt zt0[57],x0 + movt zt0[64], x0 + movt zt0[1<<32], x0 + movt zt0.b[0], x0 + movt zt0/z[0], x0 + movt zt0[0], sp + movt zt0[0], w0 + movt zt0[0], wsp + movt zt0[0], wzr + movt zt0[0], 0 + + ldr 0, [x0] + ldr zt0, 0 + + ldr zt0, [x0, #0] + ldr Zt0, [x0] + ldr zT0, [x0] + ldr zt0, [x0, #0, mul vl] + ldr zt0, [w0] + ldr zt0, [x0]! + ldr zt0, [xzr] + ldr zt0, [wsp] + ldr zt0, [x0, xzr] + ldr zt0, [x1, x2] + + luti2 z0.b, zt0, z0[-1] + luti2 z0.b, zt0, z0[16] + luti2 z0.b, zt0, z0.b[0] + luti2 z0, zt0, z0[0] + luti2 z0.d, zt0, z0[0] + luti2 z0.q, zt0, z0[0] + luti2 z0.b, zt0, zt0 + + luti2 0, zt0, z0[0] + luti2 z0.b, 0, z0[0] + luti2 z0.b, zt0, 0 + + luti2 { z1.b - z2.b }, zt0, z0[0] + luti2 { z0.b - z1.b }, z0, z0[0] + luti2 { z0.b - z1.b }, za, z0[0] + luti2 { z0.h - z1.h }, zt0, z0.h[0] + luti2 { z0.h - z1.h }, zt0, z0[-1] + luti2 { z0.h - z1.h }, zt0, z0[8] + luti2 { z0.d - z1.d }, zt0, z0[0] + luti2 { z0.q - z1.q }, zt0, z0[0] + + luti2 { z1.s - z4.s }, zt0, z0[0] + luti2 { z2.s - z5.s }, zt0, z0[0] + luti2 { z3.s - z6.s }, zt0, z0[0] + luti2 { z0.s - z3.s }, z0, z0[0] + luti2 { z0.b - z3.b }, za, z0[0] + luti2 { z0.b - z3.b }, zt0, z0.b[0] + luti2 { z0.b - z3.b }, zt0, z0[-1] + luti2 { z0.b - z3.b }, zt0, z0[4] + luti2 { z0.d - z3.d }, zt0, z0[0] + luti2 { z0.q - z3.q }, zt0, z0[0] + + luti4 0, zt0, z0[0] + luti4 z0.b, 0, z0[0] + luti4 z0.b, zt0, 0 + + luti4 z0.h, zt0, z0[-1] + luti4 z0.h, zt0, z0[8] + luti4 z0.h, zt0, z0.h[0] + luti4 z0, zt0, z0[0] + luti4 z0.d, zt0, z0[0] + luti4 z0.q, zt0, z0[0] + luti4 z0.h, zt0, zt0 + + luti4 { z1.h - z2.h }, zt0, z0[0] + luti4 { z0.h - z1.h }, z0, z0[0] + luti4 { z0.h - z1.h }, za, z0[0] + luti4 { z0.h - z1.h }, zt0, z0.h[0] + luti4 { z0.h - z1.h }, zt0, z0[-1] + luti4 { z0.h - z1.h }, zt0, z0[4] + luti4 { z0.d - z1.d }, zt0, z0[0] + luti4 { z0.q - z1.q }, zt0, z0[0] + + luti4 { z1.s - z4.s }, zt0, z0[0] + luti4 { z2.s - z5.s }, zt0, z0[0] + luti4 { z3.s - z6.s }, zt0, z0[0] + luti4 { z0.s - z3.s }, z0, z0[0] + luti4 { z0.s - z3.s }, za, z0[0] + luti4 { z0.s - z3.s }, zt0, z0.s[0] + luti4 { z0.s - z3.s }, zt0, z0[-1] + luti4 { z0.s - z3.s }, zt0, z0[2] + luti4 { z0.b - z3.b }, zt0, z0[0] + luti4 { z0.d - z3.d }, zt0, z0[0] + luti4 { z0.q - z3.q }, zt0, z0[0] diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.d b/gas/testsuite/gas/aarch64/sme2-8-noarch.d new file mode 100644 index 00000000000..116e9d67b66 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a+sme +#source: sme2-8.s +#error_output: sme2-8-noarch.l diff --git a/gas/testsuite/gas/aarch64/sme2-8-noarch.l b/gas/testsuite/gas/aarch64/sme2-8-noarch.l new file mode 100644 index 00000000000..994b359532d --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8-noarch.l @@ -0,0 +1,104 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `zero {zt0}' +[^ :]+:[0-9]+: Error: selected processor does not support `zero {ZT0}' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt X0,ZT0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x30,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt xzr,zt0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x0,zt0\[56\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x9,zt0\[24\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x15,zt0\[40\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt x22,zt0\[48\]' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt ZT0\[0\],X0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[56\],x0' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],x30' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[0\],xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[8\],x20' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[16\],x25' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[32\],x27' +[^ :]+:[0-9]+: Error: selected processor does not support `movt zt0\[24\],x29' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr ZT0,\[X0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[x30\]' +[^ :]+:[0-9]+: Error: selected processor does not support `ldr zt0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str ZT0,\[X0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[x30\]' +[^ :]+:[0-9]+: Error: selected processor does not support `str zt0,\[sp\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 Z0\.B,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.b,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.h,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z31\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 z0\.s,zt0,z0\[15\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z1\.B},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z1\.b},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z1\.h},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z30\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z1\.s},zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {Z0\.B-Z3\.B},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.b-z3\.b},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.h-z3\.h},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z28\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti2 {z0\.s-z3\.s},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.b,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.b,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.b,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 Z0\.H,ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.h,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.h,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z31\.s,zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 z0\.s,zt0,z0\[7\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.b-Z1\.b},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.b-z31\.b},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.b-z1\.b},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z1\.H},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z1\.h},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z30\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z1\.s},zt0,z0\[3\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {Z0\.H-Z3\.H},ZT0,Z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.h-z31\.h},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.h-z3\.h},zt0,z0\[1\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z28\.s-z31\.s},zt0,z0\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z31\[0\]' +[^ :]+:[0-9]+: Error: selected processor does not support `luti4 {z0\.s-z3\.s},zt0,z0\[1\]' diff --git a/gas/testsuite/gas/aarch64/sme2-8.d b/gas/testsuite/gas/aarch64/sme2-8.d new file mode 100644 index 00000000000..a129dff4d70 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8.d @@ -0,0 +1,112 @@ +#as: -march=armv8-a+sme2 +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +[^:]+: c0480001 zero {zt0} +[^:]+: c0480001 zero {zt0} +[^:]+: c04c03e0 movt x0, zt0\[0\] +[^:]+: c04c03e0 movt x0, zt0\[0\] +[^:]+: c04c03fe movt x30, zt0\[0\] +[^:]+: c04c03ff movt xzr, zt0\[0\] +[^:]+: c04c73e0 movt x0, zt0\[56\] +[^:]+: c04c33e9 movt x9, zt0\[24\] +[^:]+: c04c53ef movt x15, zt0\[40\] +[^:]+: c04c63f6 movt x22, zt0\[48\] +[^:]+: c04e03e0 movt zt0\[0\], x0 +[^:]+: c04e03e0 movt zt0\[0\], x0 +[^:]+: c04e73e0 movt zt0\[56\], x0 +[^:]+: c04e03fe movt zt0\[0\], x30 +[^:]+: c04e03ff movt zt0\[0\], xzr +[^:]+: c04e13f4 movt zt0\[8\], x20 +[^:]+: c04e23f9 movt zt0\[16\], x25 +[^:]+: c04e43fb movt zt0\[32\], x27 +[^:]+: c04e33fd movt zt0\[24\], x29 +[^:]+: e11f8000 ldr zt0, \[x0\] +[^:]+: e11f8000 ldr zt0, \[x0\] +[^:]+: e11f83c0 ldr zt0, \[x30\] +[^:]+: e11f83e0 ldr zt0, \[sp\] +[^:]+: e13f8000 str zt0, \[x0\] +[^:]+: e13f8000 str zt0, \[x0\] +[^:]+: e13f83c0 str zt0, \[x30\] +[^:]+: e13f83e0 str zt0, \[sp\] +[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\] +[^:]+: c0cc0000 luti2 z0\.b, zt0, z0\[0\] +[^:]+: c0cc001f luti2 z31\.b, zt0, z0\[0\] +[^:]+: c0cc03e0 luti2 z0\.b, zt0, z31\[0\] +[^:]+: c0cfc000 luti2 z0\.b, zt0, z0\[15\] +[^:]+: c0cc1000 luti2 z0\.h, zt0, z0\[0\] +[^:]+: c0cc101f luti2 z31\.h, zt0, z0\[0\] +[^:]+: c0cc13e0 luti2 z0\.h, zt0, z31\[0\] +[^:]+: c0cfd000 luti2 z0\.h, zt0, z0\[15\] +[^:]+: c0cc2000 luti2 z0\.s, zt0, z0\[0\] +[^:]+: c0cc201f luti2 z31\.s, zt0, z0\[0\] +[^:]+: c0cc23e0 luti2 z0\.s, zt0, z31\[0\] +[^:]+: c0cfe000 luti2 z0\.s, zt0, z0\[15\] +[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08c4000 luti2 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08c401e luti2 {z30\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08c43e0 luti2 {z0\.b-z1\.b}, zt0, z31\[0\] +[^:]+: c08fc000 luti2 {z0\.b-z1\.b}, zt0, z0\[7\] +[^:]+: c08c5000 luti2 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08c501e luti2 {z30\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08c53e0 luti2 {z0\.h-z1\.h}, zt0, z31\[0\] +[^:]+: c08fd000 luti2 {z0\.h-z1\.h}, zt0, z0\[7\] +[^:]+: c08c6000 luti2 {z0\.s-z1\.s}, zt0, z0\[0\] +[^:]+: c08c601e luti2 {z30\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08c63e0 luti2 {z0\.s-z1\.s}, zt0, z31\[0\] +[^:]+: c08fe000 luti2 {z0\.s-z1\.s}, zt0, z0\[7\] +[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^:]+: c08c8000 luti2 {z0\.b-z3\.b}, zt0, z0\[0\] +[^:]+: c08c801c luti2 {z28\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08c83e0 luti2 {z0\.b-z3\.b}, zt0, z31\[0\] +[^:]+: c08f8000 luti2 {z0\.b-z3\.b}, zt0, z0\[3\] +[^:]+: c08c9000 luti2 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08c901c luti2 {z28\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08c93e0 luti2 {z0\.h-z3\.h}, zt0, z31\[0\] +[^:]+: c08f9000 luti2 {z0\.h-z3\.h}, zt0, z0\[3\] +[^:]+: c08ca000 luti2 {z0\.s-z3\.s}, zt0, z0\[0\] +[^:]+: c08ca01c luti2 {z28\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08ca3e0 luti2 {z0\.s-z3\.s}, zt0, z31\[0\] +[^:]+: c08fa000 luti2 {z0\.s-z3\.s}, zt0, z0\[3\] +[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\] +[^:]+: c0ca0000 luti4 z0\.b, zt0, z0\[0\] +[^:]+: c0ca001f luti4 z31\.b, zt0, z0\[0\] +[^:]+: c0ca03e0 luti4 z0\.b, zt0, z31\[0\] +[^:]+: c0cbc000 luti4 z0\.b, zt0, z0\[7\] +[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\] +[^:]+: c0ca1000 luti4 z0\.h, zt0, z0\[0\] +[^:]+: c0ca101f luti4 z31\.h, zt0, z0\[0\] +[^:]+: c0ca13e0 luti4 z0\.h, zt0, z31\[0\] +[^:]+: c0cbd000 luti4 z0\.h, zt0, z0\[7\] +[^:]+: c0ca2000 luti4 z0\.s, zt0, z0\[0\] +[^:]+: c0ca201f luti4 z31\.s, zt0, z0\[0\] +[^:]+: c0ca23e0 luti4 z0\.s, zt0, z31\[0\] +[^:]+: c0cbe000 luti4 z0\.s, zt0, z0\[7\] +[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08a4000 luti4 {z0\.b-z1\.b}, zt0, z0\[0\] +[^:]+: c08a401e luti4 {z30\.b-z31\.b}, zt0, z0\[0\] +[^:]+: c08a43e0 luti4 {z0\.b-z1\.b}, zt0, z31\[0\] +[^:]+: c08bc000 luti4 {z0\.b-z1\.b}, zt0, z0\[3\] +[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08a5000 luti4 {z0\.h-z1\.h}, zt0, z0\[0\] +[^:]+: c08a501e luti4 {z30\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08a53e0 luti4 {z0\.h-z1\.h}, zt0, z31\[0\] +[^:]+: c08bd000 luti4 {z0\.h-z1\.h}, zt0, z0\[3\] +[^:]+: c08a6000 luti4 {z0\.s-z1\.s}, zt0, z0\[0\] +[^:]+: c08a601e luti4 {z30\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08a63e0 luti4 {z0\.s-z1\.s}, zt0, z31\[0\] +[^:]+: c08be000 luti4 {z0\.s-z1\.s}, zt0, z0\[3\] +[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08a9000 luti4 {z0\.h-z3\.h}, zt0, z0\[0\] +[^:]+: c08a901c luti4 {z28\.h-z31\.h}, zt0, z0\[0\] +[^:]+: c08a93e0 luti4 {z0\.h-z3\.h}, zt0, z31\[0\] +[^:]+: c08b9000 luti4 {z0\.h-z3\.h}, zt0, z0\[1\] +[^:]+: c08aa000 luti4 {z0\.s-z3\.s}, zt0, z0\[0\] +[^:]+: c08aa01c luti4 {z28\.s-z31\.s}, zt0, z0\[0\] +[^:]+: c08aa3e0 luti4 {z0\.s-z3\.s}, zt0, z31\[0\] +[^:]+: c08ba000 luti4 {z0\.s-z3\.s}, zt0, z0\[1\] diff --git a/gas/testsuite/gas/aarch64/sme2-8.s b/gas/testsuite/gas/aarch64/sme2-8.s new file mode 100644 index 00000000000..2bd5449c214 --- /dev/null +++ b/gas/testsuite/gas/aarch64/sme2-8.s @@ -0,0 +1,124 @@ + zero { zt0 } + ZERO { ZT0 } + + movt x0, zt0[0] + MOVT X0, ZT0[0] + movt x30, zt0[0] + movt xzr, zt0[0] + movt x0, zt0[56] + movt x9, zt0[24] + movt x15, zt0[40] + movt x22, zt0[48] + + movt zt0[0], x0 + MOVT ZT0[0], X0 + movt zt0[56], x0 + movt zt0[0], x30 + movt zt0[0], xzr + movt zt0[8], x20 + movt zt0[16], x25 + movt zt0[32], x27 + movt zt0[24], x29 + + ldr zt0, [x0] + LDR ZT0, [X0] + ldr zt0, [x30] + ldr zt0, [sp] + + str zt0, [x0] + STR ZT0, [X0] + str zt0, [x30] + str zt0, [sp] + + luti2 z0.b, zt0, z0[0] + LUTI2 Z0.B, ZT0, Z0[0] + luti2 z31.b, zt0, z0[0] + luti2 z0.b, zt0, z31[0] + luti2 z0.b, zt0, z0[15] + + luti2 z0.h, zt0, z0[0] + luti2 z31.h, zt0, z0[0] + luti2 z0.h, zt0, z31[0] + luti2 z0.h, zt0, z0[15] + + luti2 z0.s, zt0, z0[0] + luti2 z31.s, zt0, z0[0] + luti2 z0.s, zt0, z31[0] + luti2 z0.s, zt0, z0[15] + + luti2 { z0.b - z1.b }, zt0, z0[0] + LUTI2 { Z0.B - Z1.B }, ZT0, Z0[0] + luti2 { z30.b - z31.b }, zt0, z0[0] + luti2 { z0.b - z1.b }, zt0, z31[0] + luti2 { z0.b - z1.b }, zt0, z0[7] + + luti2 { z0.h - z1.h }, zt0, z0[0] + luti2 { z30.h - z31.h }, zt0, z0[0] + luti2 { z0.h - z1.h }, zt0, z31[0] + luti2 { z0.h - z1.h }, zt0, z0[7] + + luti2 { z0.s - z1.s }, zt0, z0[0] + luti2 { z30.s - z31.s }, zt0, z0[0] + luti2 { z0.s - z1.s }, zt0, z31[0] + luti2 { z0.s - z1.s }, zt0, z0[7] + + luti2 { z0.b - z3.b }, zt0, z0[0] + LUTI2 { Z0.B - Z3.B }, ZT0, Z0[0] + luti2 { z28.b - z31.b }, zt0, z0[0] + luti2 { z0.b - z3.b }, zt0, z31[0] + luti2 { z0.b - z3.b }, zt0, z0[3] + + luti2 { z0.h - z3.h }, zt0, z0[0] + luti2 { z28.h - z31.h }, zt0, z0[0] + luti2 { z0.h - z3.h }, zt0, z31[0] + luti2 { z0.h - z3.h }, zt0, z0[3] + + luti2 { z0.s - z3.s }, zt0, z0[0] + luti2 { z28.s - z31.s }, zt0, z0[0] + luti2 { z0.s - z3.s }, zt0, z31[0] + luti2 { z0.s - z3.s }, zt0, z0[3] + + luti4 z0.b, zt0, z0[0] + LUTI4 Z0.b, ZT0, Z0[0] + luti4 z31.b, zt0, z0[0] + luti4 z0.b, zt0, z31[0] + luti4 z0.b, zt0, z0[7] + + luti4 z0.h, zt0, z0[0] + LUTI4 Z0.H, ZT0, Z0[0] + luti4 z31.h, zt0, z0[0] + luti4 z0.h, zt0, z31[0] + luti4 z0.h, zt0, z0[7] + + luti4 z0.s, zt0, z0[0] + luti4 z31.s, zt0, z0[0] + luti4 z0.s, zt0, z31[0] + luti4 z0.s, zt0, z0[7] + + luti4 { z0.b - z1.b }, zt0, z0[0] + LUTI4 { Z0.b - Z1.b }, ZT0, Z0[0] + luti4 { z30.b - z31.b }, zt0, z0[0] + luti4 { z0.b - z1.b }, zt0, z31[0] + luti4 { z0.b - z1.b }, zt0, z0[3] + + luti4 { z0.h - z1.h }, zt0, z0[0] + LUTI4 { Z0.H - Z1.H }, ZT0, Z0[0] + luti4 { z30.h - z31.h }, zt0, z0[0] + luti4 { z0.h - z1.h }, zt0, z31[0] + luti4 { z0.h - z1.h }, zt0, z0[3] + + luti4 { z0.s - z1.s }, zt0, z0[0] + luti4 { z30.s - z31.s }, zt0, z0[0] + luti4 { z0.s - z1.s }, zt0, z31[0] + luti4 { z0.s - z1.s }, zt0, z0[3] + + luti4 { z0.h - z3.h }, zt0, z0[0] + LUTI4 { Z0.H - Z3.H }, ZT0, Z0[0] + luti4 { z28.h - z31.h }, zt0, z0[0] + luti4 { z0.h - z3.h }, zt0, z31[0] + luti4 { z0.h - z3.h }, zt0, z0[1] + + luti4 { z0.s - z3.s }, zt0, z0[0] + luti4 { z28.s - z31.s }, zt0, z0[0] + luti4 { z0.s - z3.s }, zt0, z31[0] + luti4 { z0.s - z3.s }, zt0, z0[1] diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l index 00352f88f52..a02fbfe28ef 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.l +++ b/gas/testsuite/gas/aarch64/sve-invalid.l @@ -932,6 +932,14 @@ .*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]' .*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]' .*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]' +.*: Error: operand mismatch -- `dup z0\.b,z1\[0\]' +.*: Info: did you mean this\? +.*: Info: dup z0\.b, z1\.b\[0\] +.*: Info: other valid variant\(s\): +.*: Info: dup z0\.h, z1\.h\[0\] +.*: Info: dup z0\.s, z1\.s\[0\] +.*: Info: dup z0\.d, z1\.d\[0\] +.*: Info: dup z0\.q, z1\.q\[0\] .*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]' .*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]' .*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]' diff --git a/gas/testsuite/gas/aarch64/sve-invalid.s b/gas/testsuite/gas/aarch64/sve-invalid.s index b56a08dc15c..c374396ebb3 100644 --- a/gas/testsuite/gas/aarch64/sve-invalid.s +++ b/gas/testsuite/gas/aarch64/sve-invalid.s @@ -1143,6 +1143,7 @@ dup z0.b, z1.b[63] // OK dup z0.b, z1.b[64] dup z0.b, z1.b[x0] + dup z0.b, z1[0] dup z0.h, z1.h[-1] dup z0.h, z1.h[0] // OK diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index ee0a3b65ab0..69e0f833170 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -515,8 +515,17 @@ enum aarch64_opnd AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [{, #, MUL VL}]. */ AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */ AARCH64_OPND_SME_PnT_Wm_imm, /* SME .[, #]. */ + AARCH64_OPND_SME_Zn_INDEX1_16, /* Zn[index], bits [9:5] and [16:16]. */ + AARCH64_OPND_SME_Zn_INDEX2_15, /* Zn[index], bits [9:5] and [16:15]. */ + AARCH64_OPND_SME_Zn_INDEX2_16, /* Zn[index], bits [9:5] and [17:16]. */ + AARCH64_OPND_SME_Zn_INDEX3_14, /* Zn[index], bits [9:5] and [16:14]. */ + AARCH64_OPND_SME_Zn_INDEX3_15, /* Zn[index], bits [9:5] and [17:15]. */ + AARCH64_OPND_SME_Zn_INDEX4_14, /* Zn[index], bits [9:5] and [17:14]. */ AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */ AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */ + AARCH64_OPND_SME_ZT0, /* The fixed token zt0/ZT0 (not encoded). */ + AARCH64_OPND_SME_ZT0_INDEX, /* ZT0[], bits [14:12]. */ + AARCH64_OPND_SME_ZT0_LIST, /* { zt0/ZT0 } (not encoded). */ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */ AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */ AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */ @@ -690,6 +699,8 @@ enum aarch64_insn_class sme_mov, sme_ldr, sme_psel, + sme_size_12_bhs, + sme_size_12_hs, sme_size_22, sme_str, sme_start, diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index 9302253db59..cdc9e465d13 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -684,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 247: + case 256: return aarch64_ins_reglane (self, info, code, inst, errors); case 36: return aarch64_ins_reglist (self, info, code, inst, errors); @@ -730,11 +730,12 @@ aarch64_insert_operand (const aarch64_operand *self, case 193: case 194: case 236: - case 244: - case 245: - case 246: + case 250: case 251: - case 252: + case 253: + case 255: + case 260: + case 261: return aarch64_ins_imm (self, info, code, inst, errors); case 44: case 45: @@ -803,6 +804,8 @@ aarch64_insert_operand (const aarch64_operand *self, case 107: return aarch64_ins_prfop (self, info, code, inst, errors); case 108: + case 252: + case 254: return aarch64_ins_none (self, info, code, inst, errors); case 109: return aarch64_ins_hint (self, info, code, inst, errors); @@ -915,6 +918,12 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors); case 234: case 235: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: return aarch64_ins_simple_index (self, info, code, inst, errors); case 238: case 239: @@ -926,9 +935,9 @@ aarch64_insert_operand (const aarch64_operand *self, return aarch64_ins_sme_sm_za (self, info, code, inst, errors); case 243: return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors); - case 248: - case 249: - case 250: + case 257: + case 258: + case 259: return aarch64_ins_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index acfec3773dc..bd03f4116cc 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -404,6 +404,8 @@ aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info, imm = info->imm.value; if (operand_need_shift_by_two (self)) imm >>= 2; + if (operand_need_shift_by_three (self)) + imm >>= 3; if (operand_need_shift_by_four (self)) imm >>= 4; insert_all_fields (self, code, imm); @@ -1946,11 +1948,21 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst) /* The variant is encoded as part of the immediate. */ break; + case sme_size_12_bhs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst), 0); + break; + case sme_size_22: insert_field (FLD_SME_size_22, &inst->value, aarch64_get_variant (inst), 0); break; + case sme_size_12_hs: + insert_field (FLD_SME_size_12, &inst->value, + aarch64_get_variant (inst) + 1, 0); + break; + case sve_cpy: insert_fields (&inst->value, aarch64_get_variant (inst), 0, 2, FLD_SVE_M_14, FLD_size); diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index 5210db3b008..f69f30f8884 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -94,9 +94,9 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - if (((word >> 17) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - if (((word >> 18) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { if (((word >> 19) & 0x1) == 0) { @@ -152,95 +152,194 @@ aarch64_opcode_lookup_1 (uint32_t word) } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0x100xxxxxxxxxxxxxxxxx - zero. */ - return 2392; + if (((word >> 22) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x100xxxxxxxxxxxxxxxxx + zero. */ + return 2392; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x10x100xxxxxxxxxxxxxxxxx + zero. */ + return 2596; + } } } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 19) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x001xxxxxxxxxxxxxxxxx + mov. */ + return 2388; + } + else + { + if (((word >> 22) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx10xxxxx00xxxxxxxxxx - mov. */ - return 2499; + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x101xx0xxxxxxxxxxxxxx + luti4. */ + return 2499; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x101xx1xxxxxxxxxxxxxx + luti4. */ + return 2498; + } } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx10xxxxxxxxxx - mov. */ + x1000000x10x101xxxxxxxxxxxxxxxxx + luti4. */ return 2497; } } + } + } + else + { + if (((word >> 10) & 0x1) == 0) + { + if (((word >> 11) & 0x1) == 0) + { + if (((word >> 19) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x010xxxxx00xxxxxxxxxx + mov. */ + return 2506; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000xx0x011xxxxx00xxxxxxxxxx + mov. */ + return 2502; + } + } + else + { + if (((word >> 22) & 0x1) == 0) + { + if (((word >> 14) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x11xxx0xx00xxxxxxxxxx + luti2. */ + return 2496; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000x00x11xxx1xx00xxxxxxxxxx + luti2. */ + return 2495; + } + } + else + { + if (((word >> 23) & 0x1) == 0) + { + if (((word >> 17) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000010x110xxxxx00xxxxxxxxxx + movt. */ + return 2517; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000010x111xxxxx00xxxxxxxxxx + movt. */ + return 2516; + } + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1000000110x11xxxxxx00xxxxxxxxxx + luti2. */ + return 2494; + } + } + } + } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx01xxxxxxxxxx + x1000000xx0xx10xxxxx10xxxxxxxxxx mov. */ - return 2500; + return 2504; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx10xxxxx11xxxxxxxxxx + x1000000xx0xx11xxxxx10xxxxxxxxxx mov. */ - return 2498; + return 2500; } } } - } - else - { - if (((word >> 18) & 0x1) == 0) - { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1000000xx0xx01xxxxxxxxxxxxxxxxx - mov. */ - return 2388; - } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 11) & 0x1) == 0) { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx00xxxxxxxxxx + x1000000xx0xx10xxxxx01xxxxxxxxxx mov. */ - return 2495; + return 2507; } else { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx10xxxxxxxxxx + x1000000xx0xx11xxxxx01xxxxxxxxxx mov. */ - return 2493; + return 2503; } } else { - if (((word >> 11) & 0x1) == 0) + if (((word >> 17) & 0x1) == 0) { /* 33222222222211111111110000000000 10987654321098765432109876543210 - x1000000xx0xx11xxxxx01xxxxxxxxxx + x1000000xx0xx10xxxxx11xxxxxxxxxx mov. */ - return 2496; + return 2505; } else { @@ -248,7 +347,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000000xx0xx11xxxxx11xxxxxxxxxx mov. */ - return 2494; + return 2501; } } } @@ -713,7 +812,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2518; + return 2527; } else { @@ -721,7 +820,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2519; + return 2528; } } else @@ -732,7 +831,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2542; + return 2551; } else { @@ -740,7 +839,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2543; + return 2552; } } } @@ -754,7 +853,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2534; + return 2543; } else { @@ -762,7 +861,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2535; + return 2544; } } else @@ -773,7 +872,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2526; + return 2535; } else { @@ -781,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2527; + return 2536; } } } @@ -798,7 +897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2550; + return 2559; } else { @@ -806,7 +905,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2551; + return 2560; } } else @@ -817,7 +916,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2574; + return 2583; } else { @@ -825,7 +924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2575; + return 2584; } } } @@ -839,7 +938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2566; + return 2575; } else { @@ -847,7 +946,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2567; + return 2576; } } else @@ -858,7 +957,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2558; + return 2567; } else { @@ -866,7 +965,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000001xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2559; + return 2568; } } } @@ -930,7 +1029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx0 st1b. */ - return 2514; + return 2523; } else { @@ -938,7 +1037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx0 st1b. */ - return 2515; + return 2524; } } else @@ -949,7 +1048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx0 st1w. */ - return 2538; + return 2547; } else { @@ -957,7 +1056,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx0 st1w. */ - return 2539; + return 2548; } } } @@ -971,7 +1070,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx0 st1h. */ - return 2530; + return 2539; } else { @@ -979,7 +1078,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx0 st1h. */ - return 2531; + return 2540; } } else @@ -990,7 +1089,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx0 st1d. */ - return 2522; + return 2531; } else { @@ -998,7 +1097,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx0 st1d. */ - return 2523; + return 2532; } } } @@ -1015,7 +1114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx000xxxxxxxxxxxx1 stnt1b. */ - return 2546; + return 2555; } else { @@ -1023,7 +1122,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx100xxxxxxxxxxxx1 stnt1b. */ - return 2547; + return 2556; } } else @@ -1034,7 +1133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx010xxxxxxxxxxxx1 stnt1w. */ - return 2570; + return 2579; } else { @@ -1042,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx110xxxxxxxxxxxx1 stnt1w. */ - return 2571; + return 2580; } } } @@ -1056,7 +1155,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx001xxxxxxxxxxxx1 stnt1h. */ - return 2562; + return 2571; } else { @@ -1064,7 +1163,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx101xxxxxxxxxxxx1 stnt1h. */ - return 2563; + return 2572; } } else @@ -1075,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx011xxxxxxxxxxxx1 stnt1d. */ - return 2554; + return 2563; } else { @@ -1083,7 +1182,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0x00000011xxxxx111xxxxxxxxxxxx1 stnt1d. */ - return 2555; + return 2564; } } } @@ -1265,11 +1364,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xxx00001000xxxxx100xxxxxxxxx0xxx - ld1b. */ - return 2436; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0x00001000xxxxx100xxxxxxxxx0xxx + ld1b. */ + return 2436; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1x00001000xxxxx100xxxxxxxxx0xxx + ldr. */ + return 2493; + } } else { @@ -1623,7 +1733,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx0xxxxxxxxxxxxxxxx sel. */ - return 2512; + return 2521; } else { @@ -1631,7 +1741,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1000001xx1xxxx1xxxxxxxxxxxxxxxx sel. */ - return 2513; + return 2522; } } } @@ -1655,7 +1765,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx0xxx st1b. */ - return 2520; + return 2529; } else { @@ -1663,7 +1773,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx0xxx st1w. */ - return 2544; + return 2553; } } else @@ -1674,7 +1784,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx0xxx st1h. */ - return 2536; + return 2545; } else { @@ -1682,7 +1792,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx0xxx st1d. */ - return 2528; + return 2537; } } } @@ -1696,7 +1806,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2552; + return 2561; } else { @@ -1704,7 +1814,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2576; + return 2585; } } else @@ -1715,7 +1825,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2568; + return 2577; } else { @@ -1723,7 +1833,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0100001001xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2560; + return 2569; } } } @@ -1745,11 +1855,22 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 14) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - xx100001001xxxxx100xxxxxxxxx0xxx - st1b. */ - return 2521; + if (((word >> 30) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x0100001001xxxxx100xxxxxxxxx0xxx + st1b. */ + return 2530; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1100001001xxxxx100xxxxxxxxx0xxx + str. */ + return 2587; + } } else { @@ -1757,7 +1878,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx0xxx st1w. */ - return 2545; + return 2554; } } else @@ -1768,7 +1889,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx0xxx st1h. */ - return 2537; + return 2546; } else { @@ -1776,7 +1897,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx0xxx st1d. */ - return 2529; + return 2538; } } } @@ -1790,7 +1911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2553; + return 2562; } else { @@ -1798,7 +1919,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2577; + return 2586; } } else @@ -1809,7 +1930,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2569; + return 2578; } else { @@ -1817,7 +1938,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001001xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2561; + return 2570; } } } @@ -1859,7 +1980,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx0xxx st1b. */ - return 2516; + return 2525; } else { @@ -1867,7 +1988,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx0xxx st1b. */ - return 2517; + return 2526; } } else @@ -1878,7 +1999,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx0xxx st1w. */ - return 2540; + return 2549; } else { @@ -1886,7 +2007,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx0xxx st1w. */ - return 2541; + return 2550; } } } @@ -1900,7 +2021,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx0xxx st1h. */ - return 2532; + return 2541; } else { @@ -1908,7 +2029,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx0xxx st1h. */ - return 2533; + return 2542; } } else @@ -1919,7 +2040,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx0xxx st1d. */ - return 2524; + return 2533; } else { @@ -1927,7 +2048,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx0xxx st1d. */ - return 2525; + return 2534; } } } @@ -1944,7 +2065,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx000xxxxxxxxx1xxx stnt1b. */ - return 2548; + return 2557; } else { @@ -1952,7 +2073,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx100xxxxxxxxx1xxx stnt1b. */ - return 2549; + return 2558; } } else @@ -1963,7 +2084,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx010xxxxxxxxx1xxx stnt1w. */ - return 2572; + return 2581; } else { @@ -1971,7 +2092,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx110xxxxxxxxx1xxx stnt1w. */ - return 2573; + return 2582; } } } @@ -1985,7 +2106,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx001xxxxxxxxx1xxx stnt1h. */ - return 2564; + return 2573; } else { @@ -1993,7 +2114,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx101xxxxxxxxx1xxx stnt1h. */ - return 2565; + return 2574; } } else @@ -2004,7 +2125,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx011xxxxxxxxx1xxx stnt1d. */ - return 2556; + return 2565; } else { @@ -2012,7 +2133,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx100001011xxxxx111xxxxxxxxx1xxx stnt1d. */ - return 2557; + return 2566; } } } @@ -4414,7 +4535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001000xxxxxxxxx00xxxxxxxxxx stlurb. */ - return 2626; + return 2637; } else { @@ -4422,7 +4543,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2634; + return 2645; } } else @@ -4433,7 +4554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001000xxxxxxxxx00xxxxxxxxxx stlurh. */ - return 2630; + return 2641; } else { @@ -4441,7 +4562,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001000xxxxxxxxx00xxxxxxxxxx stlur. */ - return 2637; + return 2648; } } } @@ -4479,7 +4600,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0000x1xxxxxxxxxx cpyfp. */ - return 2686; + return 2697; } else { @@ -4487,7 +4608,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1000x1xxxxxxxxxx cpyfprn. */ - return 2692; + return 2703; } } else @@ -4498,7 +4619,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0100x1xxxxxxxxxx cpyfpwn. */ - return 2689; + return 2700; } else { @@ -4506,7 +4627,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1100x1xxxxxxxxxx cpyfpn. */ - return 2695; + return 2706; } } } @@ -4520,7 +4641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0010x1xxxxxxxxxx cpyfprt. */ - return 2710; + return 2721; } else { @@ -4528,7 +4649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1010x1xxxxxxxxxx cpyfprtrn. */ - return 2716; + return 2727; } } else @@ -4539,7 +4660,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0110x1xxxxxxxxxx cpyfprtwn. */ - return 2713; + return 2724; } else { @@ -4547,7 +4668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1110x1xxxxxxxxxx cpyfprtn. */ - return 2719; + return 2730; } } } @@ -4564,7 +4685,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0001x1xxxxxxxxxx cpyfpwt. */ - return 2698; + return 2709; } else { @@ -4572,7 +4693,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1001x1xxxxxxxxxx cpyfpwtrn. */ - return 2704; + return 2715; } } else @@ -4583,7 +4704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0101x1xxxxxxxxxx cpyfpwtwn. */ - return 2701; + return 2712; } else { @@ -4591,7 +4712,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1101x1xxxxxxxxxx cpyfpwtn. */ - return 2707; + return 2718; } } } @@ -4605,7 +4726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0011x1xxxxxxxxxx cpyfpt. */ - return 2722; + return 2733; } else { @@ -4613,7 +4734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1011x1xxxxxxxxxx cpyfptrn. */ - return 2728; + return 2739; } } else @@ -4624,7 +4745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx0111x1xxxxxxxxxx cpyfptwn. */ - return 2725; + return 2736; } else { @@ -4632,7 +4753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001000xxxxx1111x1xxxxxxxxxx cpyfptn. */ - return 2731; + return 2742; } } } @@ -4697,7 +4818,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001010xxxxxxxxx00xxxxxxxxxx ldapurb. */ - return 2627; + return 2638; } else { @@ -4705,7 +4826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2635; + return 2646; } } else @@ -4716,7 +4837,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 01011001010xxxxxxxxx00xxxxxxxxxx ldapurh. */ - return 2631; + return 2642; } else { @@ -4724,7 +4845,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11011001010xxxxxxxxx00xxxxxxxxxx ldapur. */ - return 2638; + return 2649; } } } @@ -4762,7 +4883,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0000x1xxxxxxxxxx cpyfm. */ - return 2687; + return 2698; } else { @@ -4770,7 +4891,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1000x1xxxxxxxxxx cpyfmrn. */ - return 2693; + return 2704; } } else @@ -4781,7 +4902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0100x1xxxxxxxxxx cpyfmwn. */ - return 2690; + return 2701; } else { @@ -4789,7 +4910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1100x1xxxxxxxxxx cpyfmn. */ - return 2696; + return 2707; } } } @@ -4803,7 +4924,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0010x1xxxxxxxxxx cpyfmrt. */ - return 2711; + return 2722; } else { @@ -4811,7 +4932,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1010x1xxxxxxxxxx cpyfmrtrn. */ - return 2717; + return 2728; } } else @@ -4822,7 +4943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0110x1xxxxxxxxxx cpyfmrtwn. */ - return 2714; + return 2725; } else { @@ -4830,7 +4951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1110x1xxxxxxxxxx cpyfmrtn. */ - return 2720; + return 2731; } } } @@ -4847,7 +4968,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0001x1xxxxxxxxxx cpyfmwt. */ - return 2699; + return 2710; } else { @@ -4855,7 +4976,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1001x1xxxxxxxxxx cpyfmwtrn. */ - return 2705; + return 2716; } } else @@ -4866,7 +4987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0101x1xxxxxxxxxx cpyfmwtwn. */ - return 2702; + return 2713; } else { @@ -4874,7 +4995,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1101x1xxxxxxxxxx cpyfmwtn. */ - return 2708; + return 2719; } } } @@ -4888,7 +5009,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0011x1xxxxxxxxxx cpyfmt. */ - return 2723; + return 2734; } else { @@ -4896,7 +5017,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1011x1xxxxxxxxxx cpyfmtrn. */ - return 2729; + return 2740; } } else @@ -4907,7 +5028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx0111x1xxxxxxxxxx cpyfmtwn. */ - return 2726; + return 2737; } else { @@ -4915,7 +5036,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001010xxxxx1111x1xxxxxxxxxx cpyfmtn. */ - return 2732; + return 2743; } } } @@ -4983,7 +5104,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 00011001100xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2629; + return 2640; } else { @@ -4991,7 +5112,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 10011001100xxxxxxxxx00xxxxxxxxxx ldapursw. */ - return 2636; + return 2647; } } else @@ -5000,7 +5121,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001100xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2633; + return 2644; } } else @@ -5011,7 +5132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0011001110xxxxxxxxx00xxxxxxxxxx ldapursb. */ - return 2628; + return 2639; } else { @@ -5019,7 +5140,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1011001110xxxxxxxxx00xxxxxxxxxx ldapursh. */ - return 2632; + return 2643; } } } @@ -5081,7 +5202,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0000x1xxxxxxxxxx cpyfe. */ - return 2688; + return 2699; } else { @@ -5089,7 +5210,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0000x1xxxxxxxxxx setp. */ - return 2782; + return 2793; } } else @@ -5100,7 +5221,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1000x1xxxxxxxxxx cpyfern. */ - return 2694; + return 2705; } else { @@ -5108,7 +5229,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1000x1xxxxxxxxxx sete. */ - return 2784; + return 2795; } } } @@ -5122,7 +5243,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0100x1xxxxxxxxxx cpyfewn. */ - return 2691; + return 2702; } else { @@ -5130,7 +5251,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0100x1xxxxxxxxxx setm. */ - return 2783; + return 2794; } } else @@ -5139,7 +5260,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1100x1xxxxxxxxxx cpyfen. */ - return 2697; + return 2708; } } } @@ -5155,7 +5276,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0010x1xxxxxxxxxx cpyfert. */ - return 2712; + return 2723; } else { @@ -5163,7 +5284,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0010x1xxxxxxxxxx setpn. */ - return 2788; + return 2799; } } else @@ -5174,7 +5295,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1010x1xxxxxxxxxx cpyfertrn. */ - return 2718; + return 2729; } else { @@ -5182,7 +5303,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1010x1xxxxxxxxxx seten. */ - return 2790; + return 2801; } } } @@ -5196,7 +5317,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0110x1xxxxxxxxxx cpyfertwn. */ - return 2715; + return 2726; } else { @@ -5204,7 +5325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0110x1xxxxxxxxxx setmn. */ - return 2789; + return 2800; } } else @@ -5213,7 +5334,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1110x1xxxxxxxxxx cpyfertn. */ - return 2721; + return 2732; } } } @@ -5232,7 +5353,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0001x1xxxxxxxxxx cpyfewt. */ - return 2700; + return 2711; } else { @@ -5240,7 +5361,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0001x1xxxxxxxxxx setpt. */ - return 2785; + return 2796; } } else @@ -5251,7 +5372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1001x1xxxxxxxxxx cpyfewtrn. */ - return 2706; + return 2717; } else { @@ -5259,7 +5380,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1001x1xxxxxxxxxx setet. */ - return 2787; + return 2798; } } } @@ -5273,7 +5394,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0101x1xxxxxxxxxx cpyfewtwn. */ - return 2703; + return 2714; } else { @@ -5281,7 +5402,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0101x1xxxxxxxxxx setmt. */ - return 2786; + return 2797; } } else @@ -5290,7 +5411,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1101x1xxxxxxxxxx cpyfewtn. */ - return 2709; + return 2720; } } } @@ -5306,7 +5427,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0011x1xxxxxxxxxx cpyfet. */ - return 2724; + return 2735; } else { @@ -5314,7 +5435,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0011x1xxxxxxxxxx setptn. */ - return 2791; + return 2802; } } else @@ -5325,7 +5446,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx1011x1xxxxxxxxxx cpyfetrn. */ - return 2730; + return 2741; } else { @@ -5333,7 +5454,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx1011x1xxxxxxxxxx setetn. */ - return 2793; + return 2804; } } } @@ -5347,7 +5468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001100xxxxx0111x1xxxxxxxxxx cpyfetwn. */ - return 2727; + return 2738; } else { @@ -5355,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011001110xxxxx0111x1xxxxxxxxxx setmtn. */ - return 2792; + return 2803; } } else @@ -5364,7 +5485,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx0110011x0xxxxx1111x1xxxxxxxxxx cpyfetn. */ - return 2733; + return 2744; } } } @@ -5737,7 +5858,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1x11010110xxxx0x01000xxxxxxxxxx abs. */ - return 2811; + return 2822; } else { @@ -5755,7 +5876,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11000xxxxxxxxxx smax. */ - return 2814; + return 2825; } } } @@ -5835,7 +5956,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx0xx10xxxxxxxxxx setf8. */ - return 2624; + return 2635; } else { @@ -5843,7 +5964,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x00xxxxxx1xx10xxxxxxxxxx setf16. */ - return 2625; + return 2636; } } else @@ -5950,7 +6071,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxxxx11010xxxxxxxxxx smin. */ - return 2816; + return 2827; } } } @@ -5966,7 +6087,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010110xxxx0x00110xxxxxxxxxx ctz. */ - return 2813; + return 2824; } else { @@ -6011,7 +6132,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010000xxxxxxxxx01xxxxxxxxxx rmif. */ - return 2623; + return 2634; } else { @@ -6105,7 +6226,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010x10xxxxxx11001xxxxxxxxxx umax. */ - return 2815; + return 2826; } } } @@ -6235,7 +6356,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxxxx11011xxxxxxxxxx umin. */ - return 2817; + return 2828; } } } @@ -6251,7 +6372,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xxx11010xx0xxxx0x00111xxxxxxxxxx cnt. */ - return 2812; + return 2823; } else { @@ -7093,7 +7214,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000110xxxxxxxxxx usdot. */ - return 2643; + return 2654; } } } @@ -7167,7 +7288,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x01x1xxxxx000111xxxxxxxxxx sudot. */ - return 2644; + return 2655; } } } @@ -9841,7 +9962,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x0xx0xxxxx011110xxxxxxxxxx usdot. */ - return 2642; + return 2653; } } } @@ -11545,7 +11666,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0100xxx10101xxxxxxxxxxxxx bfcvtnt. */ - return 2671; + return 2682; } } else @@ -11788,7 +11909,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxxx00xxxxxxxxxxxxx ld1rob. */ - return 2647; + return 2658; } else { @@ -11796,7 +11917,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxxx00xxxxxxxxxxxxx ld1roh. */ - return 2648; + return 2659; } } else @@ -12028,7 +12149,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx010xxxxxxxxxxxxx bfdot. */ - return 2668; + return 2679; } else { @@ -12049,7 +12170,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx0xxxxxxxxxx bfmlalb. */ - return 2675; + return 2686; } else { @@ -12057,7 +12178,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx010xx1xxxxxxxxxx bfmlalt. */ - return 2674; + return 2685; } } else @@ -12112,7 +12233,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11001x0011xxxxx1x0xxxxxxxxxxxxx bfdot. */ - return 2667; + return 2678; } else { @@ -12124,7 +12245,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx0xxxxxxxxxx bfmlalb. */ - return 2673; + return 2684; } else { @@ -12132,7 +12253,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx1x0xx1xxxxxxxxxx bfmlalt. */ - return 2672; + return 2683; } } else @@ -12183,7 +12304,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x00x1xxxxx001xxxxxxxxxxxxx ld1rob. */ - return 2651; + return 2662; } else { @@ -12191,7 +12312,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x01x1xxxxx001xxxxxxxxxxxxx ld1roh. */ - return 2652; + return 2663; } } else @@ -12550,7 +12671,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0101xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2645; + return 2656; } else { @@ -12583,7 +12704,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0011xxxxx111xxxxxxxxxxxxx bfmmla. */ - return 2669; + return 2680; } else { @@ -12613,7 +12734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x0111xxxxx111xxxxxxxxxxxxx fmmla. */ - return 2646; + return 2657; } else { @@ -12742,7 +12863,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x00xxxxxxxxxx zip1. */ - return 2655; + return 2666; } else { @@ -12752,7 +12873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000010xxxxxxxxxx uzp1. */ - return 2657; + return 2668; } else { @@ -12760,7 +12881,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000110xxxxxxxxxx trn1. */ - return 2659; + return 2670; } } } @@ -12772,7 +12893,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000x01xxxxxxxxxx zip2. */ - return 2656; + return 2667; } else { @@ -12782,7 +12903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000011xxxxxxxxxx uzp2. */ - return 2658; + return 2669; } else { @@ -12790,7 +12911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000001x1101xxxxx000111xxxxxxxxxx trn2. */ - return 2660; + return 2671; } } } @@ -13849,7 +13970,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1000xxxxx100110xxxxxxxxxx smmla. */ - return 2639; + return 2650; } else { @@ -13857,7 +13978,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1100xxxxx100110xxxxxxxxxx usmmla. */ - return 2641; + return 2652; } } else @@ -13866,7 +13987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010001x1x10xxxxx100110xxxxxxxxxx ummla. */ - return 2640; + return 2651; } } } @@ -15362,7 +15483,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx000xxxxxxxxxxxxx ld1row. */ - return 2649; + return 2660; } else { @@ -15370,7 +15491,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx000xxxxxxxxxxxxx ld1rod. */ - return 2650; + return 2661; } } } @@ -15744,7 +15865,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x10x1xxxxx001xxxxxxxxxxxxx ld1row. */ - return 2653; + return 2664; } else { @@ -15752,7 +15873,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 101001x11x1xxxxx001xxxxxxxxxxxxx ld1rod. */ - return 2654; + return 2665; } } } @@ -16113,7 +16234,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx10xxx whilege. */ - return 2578; + return 2588; } else { @@ -16121,7 +16242,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x000xxxxx11xxx whilegt. */ - return 2579; + return 2589; } } else @@ -16151,7 +16272,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011100xxxxx1xxxx pext. */ - return 2509; + return 2518; } } } @@ -16165,7 +16286,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx10xxx whilehs. */ - return 2581; + return 2591; } else { @@ -16173,7 +16294,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x010xxxxx11xxx whilehi. */ - return 2580; + return 2590; } } else @@ -16203,7 +16324,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011110xxxxx1xxxx ptrue. */ - return 2511; + return 2520; } } } @@ -16220,7 +16341,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx10xxx whilelt. */ - return 2585; + return 2595; } else { @@ -16228,7 +16349,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x001xxxxx11xxx whilele. */ - return 2582; + return 2592; } } else @@ -16258,7 +16379,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx011101xxxxx1xxxx pext. */ - return 2510; + return 2519; } } } @@ -16272,7 +16393,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx10xxx whilelo. */ - return 2583; + return 2593; } else { @@ -16280,7 +16401,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 001001x1xx1xxxxx01x011xxxxx11xxx whilels. */ - return 2584; + return 2594; } } else @@ -17406,7 +17527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 011001x110001x10101xxxxxxxxxxxxx bfcvt. */ - return 2670; + return 2681; } } else @@ -18767,7 +18888,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1010100xxxxxxxxxxxxxxxxxxx1xxxx bc.c. */ - return 2806; + return 2817; } else { @@ -19347,7 +19468,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0000xxxxxxxxxxxx cpyp. */ - return 2734; + return 2745; } else { @@ -19355,7 +19476,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0000xxxxxxxxxxxx cpye. */ - return 2736; + return 2747; } } else @@ -19366,7 +19487,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1000xxxxxxxxxxxx cpyprn. */ - return 2740; + return 2751; } else { @@ -19374,7 +19495,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1000xxxxxxxxxxxx cpyern. */ - return 2742; + return 2753; } } } @@ -19388,7 +19509,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0100xxxxxxxxxxxx cpypwn. */ - return 2737; + return 2748; } else { @@ -19396,7 +19517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0100xxxxxxxxxxxx cpyewn. */ - return 2739; + return 2750; } } else @@ -19407,7 +19528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1100xxxxxxxxxxxx cpypn. */ - return 2743; + return 2754; } else { @@ -19415,7 +19536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1100xxxxxxxxxxxx cpyen. */ - return 2745; + return 2756; } } } @@ -19432,7 +19553,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0010xxxxxxxxxxxx cpyprt. */ - return 2758; + return 2769; } else { @@ -19440,7 +19561,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0010xxxxxxxxxxxx cpyert. */ - return 2760; + return 2771; } } else @@ -19451,7 +19572,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1010xxxxxxxxxxxx cpyprtrn. */ - return 2764; + return 2775; } else { @@ -19459,7 +19580,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1010xxxxxxxxxxxx cpyertrn. */ - return 2766; + return 2777; } } } @@ -19473,7 +19594,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0110xxxxxxxxxxxx cpyprtwn. */ - return 2761; + return 2772; } else { @@ -19481,7 +19602,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0110xxxxxxxxxxxx cpyertwn. */ - return 2763; + return 2774; } } else @@ -19492,7 +19613,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1110xxxxxxxxxxxx cpyprtn. */ - return 2767; + return 2778; } else { @@ -19500,7 +19621,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1110xxxxxxxxxxxx cpyertn. */ - return 2769; + return 2780; } } } @@ -19520,7 +19641,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0001xxxxxxxxxxxx cpypwt. */ - return 2746; + return 2757; } else { @@ -19528,7 +19649,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0001xxxxxxxxxxxx cpyewt. */ - return 2748; + return 2759; } } else @@ -19539,7 +19660,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1001xxxxxxxxxxxx cpypwtrn. */ - return 2752; + return 2763; } else { @@ -19547,7 +19668,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1001xxxxxxxxxxxx cpyewtrn. */ - return 2754; + return 2765; } } } @@ -19561,7 +19682,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0101xxxxxxxxxxxx cpypwtwn. */ - return 2749; + return 2760; } else { @@ -19569,7 +19690,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0101xxxxxxxxxxxx cpyewtwn. */ - return 2751; + return 2762; } } else @@ -19580,7 +19701,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1101xxxxxxxxxxxx cpypwtn. */ - return 2755; + return 2766; } else { @@ -19588,7 +19709,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1101xxxxxxxxxxxx cpyewtn. */ - return 2757; + return 2768; } } } @@ -19605,7 +19726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0011xxxxxxxxxxxx cpypt. */ - return 2770; + return 2781; } else { @@ -19613,7 +19734,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0011xxxxxxxxxxxx cpyet. */ - return 2772; + return 2783; } } else @@ -19624,7 +19745,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1011xxxxxxxxxxxx cpyptrn. */ - return 2776; + return 2787; } else { @@ -19632,7 +19753,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1011xxxxxxxxxxxx cpyetrn. */ - return 2778; + return 2789; } } } @@ -19646,7 +19767,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx0111xxxxxxxxxxxx cpyptwn. */ - return 2773; + return 2784; } else { @@ -19654,7 +19775,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx0111xxxxxxxxxxxx cpyetwn. */ - return 2775; + return 2786; } } else @@ -19665,7 +19786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110100xxxxxx1111xxxxxxxxxxxx cpyptn. */ - return 2779; + return 2790; } else { @@ -19673,7 +19794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110110xxxxxx1111xxxxxxxxxxxx cpyetn. */ - return 2781; + return 2792; } } } @@ -19707,7 +19828,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0000xxxxxxxxxxxx cpym. */ - return 2735; + return 2746; } else { @@ -19715,7 +19836,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0000xxxxxxxxxxxx setgp. */ - return 2794; + return 2805; } } else @@ -19726,7 +19847,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1000xxxxxxxxxxxx cpymrn. */ - return 2741; + return 2752; } else { @@ -19734,7 +19855,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1000xxxxxxxxxxxx setge. */ - return 2796; + return 2807; } } } @@ -19748,7 +19869,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0100xxxxxxxxxxxx cpymwn. */ - return 2738; + return 2749; } else { @@ -19756,7 +19877,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0100xxxxxxxxxxxx setgm. */ - return 2795; + return 2806; } } else @@ -19765,7 +19886,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1100xxxxxxxxxxxx cpymn. */ - return 2744; + return 2755; } } } @@ -19781,7 +19902,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0010xxxxxxxxxxxx cpymrt. */ - return 2759; + return 2770; } else { @@ -19789,7 +19910,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0010xxxxxxxxxxxx setgpn. */ - return 2800; + return 2811; } } else @@ -19800,7 +19921,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1010xxxxxxxxxxxx cpymrtrn. */ - return 2765; + return 2776; } else { @@ -19808,7 +19929,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1010xxxxxxxxxxxx setgen. */ - return 2802; + return 2813; } } } @@ -19822,7 +19943,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0110xxxxxxxxxxxx cpymrtwn. */ - return 2762; + return 2773; } else { @@ -19830,7 +19951,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0110xxxxxxxxxxxx setgmn. */ - return 2801; + return 2812; } } else @@ -19839,7 +19960,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1110xxxxxxxxxxxx cpymrtn. */ - return 2768; + return 2779; } } } @@ -19858,7 +19979,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0001xxxxxxxxxxxx cpymwt. */ - return 2747; + return 2758; } else { @@ -19866,7 +19987,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0001xxxxxxxxxxxx setgpt. */ - return 2797; + return 2808; } } else @@ -19877,7 +19998,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1001xxxxxxxxxxxx cpymwtrn. */ - return 2753; + return 2764; } else { @@ -19885,7 +20006,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1001xxxxxxxxxxxx setget. */ - return 2799; + return 2810; } } } @@ -19899,7 +20020,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0101xxxxxxxxxxxx cpymwtwn. */ - return 2750; + return 2761; } else { @@ -19907,7 +20028,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0101xxxxxxxxxxxx setgmt. */ - return 2798; + return 2809; } } else @@ -19916,7 +20037,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1101xxxxxxxxxxxx cpymwtn. */ - return 2756; + return 2767; } } } @@ -19932,7 +20053,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0011xxxxxxxxxxxx cpymt. */ - return 2771; + return 2782; } else { @@ -19940,7 +20061,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0011xxxxxxxxxxxx setgptn. */ - return 2803; + return 2814; } } else @@ -19951,7 +20072,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx1011xxxxxxxxxxxx cpymtrn. */ - return 2777; + return 2788; } else { @@ -19959,7 +20080,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx1011xxxxxxxxxxxx setgetn. */ - return 2805; + return 2816; } } } @@ -19973,7 +20094,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110101xxxxxx0111xxxxxxxxxxxx cpymtwn. */ - return 2774; + return 2785; } else { @@ -19981,7 +20102,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx01110111xxxxxx0111xxxxxxxxxxxx setgmtn. */ - return 2804; + return 2815; } } else @@ -19990,7 +20111,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx011101x1xxxxxx1111xxxxxxxxxxxx cpymtn. */ - return 2780; + return 2791; } } } @@ -20157,7 +20278,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1001xxxxxxxxxx smmla. */ - return 2661; + return 2672; } } } @@ -20190,7 +20311,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0101xxxxxxxxxx sdot. */ - return 2587; + return 2598; } } else @@ -20264,7 +20385,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x1011xxxxxxxxxx usmmla. */ - return 2663; + return 2674; } } } @@ -20297,7 +20418,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 0x001110xx0xxxxx1x0111xxxxxxxxxx usdot. */ - return 2664; + return 2675; } } else @@ -20344,7 +20465,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110000xxxxxxxxxxxxxxxxxxxxx eor3. */ - return 2594; + return 2605; } else { @@ -20352,7 +20473,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110100xxxxxxxxxxxxxxxxxxxxx xar. */ - return 2596; + return 2607; } } else @@ -20363,7 +20484,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx0xxxxxxxxxxxxxxx sm3ss1. */ - return 2598; + return 2609; } else { @@ -20377,7 +20498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx00xxxxxxxxxx sm3tt1a. */ - return 2599; + return 2610; } else { @@ -20385,7 +20506,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx00xxxxxxxxxx sha512su0. */ - return 2592; + return 2603; } } else @@ -20394,7 +20515,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx10xxxxxxxxxx sm3tt2a. */ - return 2601; + return 2612; } } else @@ -20407,7 +20528,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110010xxxxx1xxx01xxxxxxxxxx sm3tt1b. */ - return 2600; + return 2611; } else { @@ -20415,7 +20536,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110110xxxxx1xxx01xxxxxxxxxx sm4e. */ - return 2605; + return 2616; } } else @@ -20424,7 +20545,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110x10xxxxx1xxx11xxxxxxxxxx sm3tt2b. */ - return 2602; + return 2613; } } } @@ -20605,7 +20726,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx100101xxxxxxxxxx udot. */ - return 2586; + return 2597; } } else @@ -20636,7 +20757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx101x01xxxxxxxxxx ummla. */ - return 2662; + return 2673; } else { @@ -20655,7 +20776,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101110xx0xxxxx1x1011xxxxxxxxxx bfmmla. */ - return 2678; + return 2689; } else { @@ -20665,7 +20786,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx1011100x0xxxxx1x1111xxxxxxxxxx bfdot. */ - return 2676; + return 2687; } else { @@ -20675,7 +20796,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x0xxxxx1x1111xxxxxxxxxx bfmlalb. */ - return 2683; + return 2694; } else { @@ -20683,7 +20804,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x0xxxxx1x1111xxxxxxxxxx bfmlalt. */ - return 2682; + return 2693; } } } @@ -21267,7 +21388,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 000011101x1xxxx1011010xxxxxxxxxx bfcvtn. */ - return 2679; + return 2690; } else { @@ -21275,7 +21396,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 010011101x1xxxx1011010xxxxxxxxxx bfcvtn2. */ - return 2680; + return 2691; } } } @@ -21593,7 +21714,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx0xxxxxxxxxxxxxxx bcax. */ - return 2597; + return 2608; } } else @@ -22204,7 +22325,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx100000xxxxxxxxxx sha512h. */ - return 2590; + return 2601; } } } @@ -22256,7 +22377,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 11001110xx1xxxxx110000xxxxxxxxxx sm3partw1. */ - return 2603; + return 2614; } } } @@ -22499,7 +22620,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100010xxxxxxxxxx sha512su1. */ - return 2593; + return 2604; } } else @@ -22575,7 +22696,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110010xxxxxxxxxx sm4ekey. */ - return 2606; + return 2617; } } else @@ -23401,7 +23522,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100001xxxxxxxxxx sha512h2. */ - return 2591; + return 2602; } } else @@ -23433,7 +23554,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x0011100x1xxxxx110001xxxxxxxxxx sm3partw2. */ - return 2604; + return 2615; } } else @@ -23673,7 +23794,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 1x001110xx1xxxxx100011xxxxxxxxxx rax1. */ - return 2595; + return 2606; } } else @@ -23705,7 +23826,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2609; + return 2620; } else { @@ -23713,7 +23834,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011100x1xxxxx110011xxxxxxxxxx fmlal2. */ - return 2613; + return 2624; } } } @@ -23735,7 +23856,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x01011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2610; + return 2621; } else { @@ -23743,7 +23864,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x11011101x1xxxxx110011xxxxxxxxxx fmlsl2. */ - return 2614; + return 2625; } } } @@ -23782,7 +23903,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2607; + return 2618; } else { @@ -23790,7 +23911,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011100x1xxxxx111011xxxxxxxxxx fmlal. */ - return 2611; + return 2622; } } else @@ -23812,7 +23933,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x00011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2608; + return 2619; } else { @@ -23820,7 +23941,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x10011101x1xxxxx111011xxxxxxxxxx fmlsl. */ - return 2612; + return 2623; } } else @@ -25628,7 +25749,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2615; + return 2626; } else { @@ -25636,7 +25757,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0000x0xxxxxxxxxx fmlal. */ - return 2619; + return 2630; } } else @@ -25658,7 +25779,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2616; + return 2627; } else { @@ -25666,7 +25787,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1001111xxxxxxxx0100x0xxxxxxxxxx fmlsl. */ - return 2620; + return 2631; } } else @@ -26172,7 +26293,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2617; + return 2628; } else { @@ -26180,7 +26301,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1000x0xxxxxxxxxx fmlal2. */ - return 2621; + return 2632; } } } @@ -26202,7 +26323,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x0101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2618; + return 2629; } else { @@ -26210,7 +26331,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x1101111xxxxxxxx1100x0xxxxxxxxxx fmlsl2. */ - return 2622; + return 2633; } } } @@ -26266,7 +26387,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx001111xxxxxxxx1110x0xxxxxxxxxx sdot. */ - return 2589; + return 2600; } else { @@ -26274,7 +26395,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx101111xxxxxxxx1110x0xxxxxxxxxx udot. */ - return 2588; + return 2599; } } } @@ -26377,7 +26498,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111100xxxxxx1111x0xxxxxxxxxx sudot. */ - return 2666; + return 2677; } else { @@ -26385,7 +26506,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111110xxxxxx1111x0xxxxxxxxxx usdot. */ - return 2665; + return 2676; } } else @@ -26396,7 +26517,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 xx00111101xxxxxx1111x0xxxxxxxxxx bfdot. */ - return 2677; + return 2688; } else { @@ -26406,7 +26527,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x000111111xxxxxx1111x0xxxxxxxxxx bfmlalb. */ - return 2685; + return 2696; } else { @@ -26414,7 +26535,7 @@ aarch64_opcode_lookup_1 (uint32_t word) 10987654321098765432109876543210 x100111111xxxxxx1111x0xxxxxxxxxx bfmlalt. */ - return 2684; + return 2695; } } } @@ -26903,24 +27024,24 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) { case 2389: value = 2391; break; /* mov --> mova. */ case 2391: return NULL; /* mova --> NULL. */ - case 2499: value = 2507; break; /* mov --> mova. */ - case 2507: return NULL; /* mova --> NULL. */ - case 2497: value = 2505; break; /* mov --> mova. */ - case 2505: return NULL; /* mova --> NULL. */ - case 2500: value = 2508; break; /* mov --> mova. */ - case 2508: return NULL; /* mova --> NULL. */ - case 2498: value = 2506; break; /* mov --> mova. */ - case 2506: return NULL; /* mova --> NULL. */ case 2388: value = 2390; break; /* mov --> mova. */ case 2390: return NULL; /* mova --> NULL. */ - case 2495: value = 2503; break; /* mov --> mova. */ - case 2503: return NULL; /* mova --> NULL. */ - case 2493: value = 2501; break; /* mov --> mova. */ - case 2501: return NULL; /* mova --> NULL. */ - case 2496: value = 2504; break; /* mov --> mova. */ - case 2504: return NULL; /* mova --> NULL. */ - case 2494: value = 2502; break; /* mov --> mova. */ - case 2502: return NULL; /* mova --> NULL. */ + case 2506: value = 2514; break; /* mov --> mova. */ + case 2514: return NULL; /* mova --> NULL. */ + case 2502: value = 2510; break; /* mov --> mova. */ + case 2510: return NULL; /* mova --> NULL. */ + case 2504: value = 2512; break; /* mov --> mova. */ + case 2512: return NULL; /* mova --> NULL. */ + case 2500: value = 2508; break; /* mov --> mova. */ + case 2508: return NULL; /* mova --> NULL. */ + case 2507: value = 2515; break; /* mov --> mova. */ + case 2515: return NULL; /* mova --> NULL. */ + case 2503: value = 2511; break; /* mov --> mova. */ + case 2511: return NULL; /* mova --> NULL. */ + case 2505: value = 2513; break; /* mov --> mova. */ + case 2513: return NULL; /* mova --> NULL. */ + case 2501: value = 2509; break; /* mov --> mova. */ + case 2509: return NULL; /* mova --> NULL. */ case 2393: value = 2398; break; /* ld1b --> ld1b. */ case 2398: return NULL; /* ld1b --> NULL. */ case 2395: value = 2400; break; /* ld1w --> ld1w. */ @@ -26942,11 +27063,11 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 2407: value = 2412; break; /* st1q --> st1q. */ case 2412: return NULL; /* st1q --> NULL. */ case 12: value = 19; break; /* add --> addg. */ - case 19: value = 2807; break; /* addg --> smax. */ - case 2807: value = 2808; break; /* smax --> umax. */ - case 2808: value = 2809; break; /* umax --> smin. */ - case 2809: value = 2810; break; /* smin --> umin. */ - case 2810: return NULL; /* umin --> NULL. */ + case 19: value = 2818; break; /* addg --> smax. */ + case 2818: value = 2819; break; /* smax --> umax. */ + case 2819: value = 2820; break; /* umax --> smin. */ + case 2820: value = 2821; break; /* smin --> umin. */ + case 2821: return NULL; /* umin --> NULL. */ case 16: value = 20; break; /* sub --> subg. */ case 20: return NULL; /* subg --> NULL. */ case 971: value = 975; break; /* stnp --> stp. */ @@ -27104,8 +27225,8 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode) case 824: return NULL; /* fsqrt --> NULL. */ case 832: value = 833; break; /* frintz --> frintz. */ case 833: return NULL; /* frintz --> NULL. */ - case 825: value = 2681; break; /* fcvt --> bfcvt. */ - case 2681: return NULL; /* bfcvt --> NULL. */ + case 825: value = 2692; break; /* fcvt --> bfcvt. */ + case 2692: return NULL; /* bfcvt --> NULL. */ case 834: value = 835; break; /* frinta --> frinta. */ case 835: return NULL; /* frinta --> NULL. */ case 836: value = 837; break; /* frintx --> frintx. */ @@ -27633,7 +27754,7 @@ aarch64_extract_operand (const aarch64_operand *self, case 33: case 34: case 35: - case 247: + case 256: return aarch64_ext_reglane (self, info, code, inst, errors); case 36: return aarch64_ext_reglist (self, info, code, inst, errors); @@ -27680,11 +27801,12 @@ aarch64_extract_operand (const aarch64_operand *self, case 193: case 194: case 236: - case 244: - case 245: - case 246: + case 250: case 251: - case 252: + case 253: + case 255: + case 260: + case 261: return aarch64_ext_imm (self, info, code, inst, errors); case 44: case 45: @@ -27755,6 +27877,8 @@ aarch64_extract_operand (const aarch64_operand *self, case 107: return aarch64_ext_prfop (self, info, code, inst, errors); case 108: + case 252: + case 254: return aarch64_ext_none (self, info, code, inst, errors); case 109: return aarch64_ext_hint (self, info, code, inst, errors); @@ -27867,6 +27991,12 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors); case 234: case 235: + case 244: + case 245: + case 246: + case 247: + case 248: + case 249: return aarch64_ext_simple_index (self, info, code, inst, errors); case 238: case 239: @@ -27878,9 +28008,9 @@ aarch64_extract_operand (const aarch64_operand *self, return aarch64_ext_sme_sm_za (self, info, code, inst, errors); case 243: return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors); - case 248: - case 249: - case 250: + case 257: + case 258: + case 259: return aarch64_ext_x0_to_x30 (self, info, code, inst, errors); default: assert (0); abort (); } diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index a2f69186355..0475adbc31d 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -702,6 +702,8 @@ aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, if (operand_need_shift_by_two (self)) imm <<= 2; + else if (operand_need_shift_by_three (self)) + imm <<= 3; else if (operand_need_shift_by_four (self)) imm <<= 4; @@ -3072,6 +3074,19 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst) } break; + case sme_size_12_bhs: + variant = extract_field (FLD_SME_size_12, inst->value, 0); + if (variant >= 3) + return false; + break; + + case sme_size_12_hs: + variant = extract_field (FLD_SME_size_12, inst->value, 0); + if (variant != 1 && variant != 2) + return false; + variant -= 1; + break; + case sme_size_22: variant = extract_field (FLD_SME_size_22, inst->value, 0); break; diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 9f2b670c49a..21e06e6114f 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -268,8 +268,17 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"}, {AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"}, {AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX1_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm1_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_15}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX2_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm2_16}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_14}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX3_15", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm3_15}, "an indexed SVE vector register"}, + {AARCH64_OPND_CLASS_SVE_REG, "SME_Zn_INDEX4_14", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn, FLD_imm4_14}, "an indexed SVE vector register"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"}, + {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "ZT0"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"}, + {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"}, {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"}, {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 3b4397d0f06..cd185b8af29 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -249,6 +249,7 @@ const aarch64_field fields[] = { 0, 3 }, /* SME_Zt3: lower 3 bits of Zt, bits [2:0]. */ { 0, 2 }, /* SME_Zt2: lower 2 bits of Zt, bits [1:0]. */ { 23, 1 }, /* SME_i1: immediate field, bit 23. */ + { 12, 2 }, /* SME_size_12: bits [13:12]. */ { 22, 2 }, /* SME_size_22: size<1>, size<0> class field, [23:22]. */ { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */ { 18, 3 }, /* SME_tszl: immediate and qualifier field, bits [20:18]. */ @@ -318,14 +319,21 @@ const aarch64_field fields[] = { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */ { 21, 2 }, /* hw: in move wide constant instructions. */ { 8, 1 }, /* imm1_8: general immediate in bits [8]. */ + { 16, 1 }, /* imm1_16: general immediate in bits [16]. */ { 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */ + { 15, 2 }, /* imm2_15: 2-bit immediate, bits [16:15] */ + { 16, 2 }, /* imm2_16: 2-bit immediate, bits [17:16] */ { 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */ { 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */ { 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */ + { 12, 3 }, /* imm3_12: general immediate in bits [14:12]. */ + { 14, 3 }, /* imm3_14: general immediate in bits [16:14]. */ + { 15, 3 }, /* imm3_15: general immediate in bits [17:15]. */ { 0, 4 }, /* imm4_0: in rmif instructions. */ { 5, 4 }, /* imm4_5: in SME instructions. */ { 10, 4 }, /* imm4_10: in adddg/subg instructions. */ { 11, 4 }, /* imm4_11: in advsimd ext and advsimd ins instructions. */ + { 14, 4 }, /* imm4_14: general immediate in bits [17:14]. */ { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */ { 10, 6 }, /* imm6_10: in add/sub reg shifted instructions. */ { 15, 6 }, /* imm6_15: in rmif instructions. */ @@ -1744,6 +1752,18 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, return 0; break; + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: + size = get_operand_fields_width (get_operand_from_code (type)) - 5; + if (!check_reglane (opnd, mismatch_detail, idx, "z", 0, 31, + 0, (1 << size) - 1)) + return 0; + break; + case AARCH64_OPND_SME_PnT_Wm_imm: size = aarch64_get_qualifier_esize (opnd->qualifier); max_value = 16 / size - 1; @@ -2862,6 +2882,20 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, } break; + case AARCH64_OPND_SME_ZT0_INDEX: + if (!value_in_range_p (opnd->imm.value, 0, 56)) + { + set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, 56); + return 0; + } + if (opnd->imm.value % 8 != 0) + { + set_other_error (mismatch_detail, idx, + _("byte index must be a multiple of 8")); + return 0; + } + break; + default: break; } @@ -3867,9 +3901,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: + case AARCH64_OPND_SME_Zn_INDEX1_16: + case AARCH64_OPND_SME_Zn_INDEX2_15: + case AARCH64_OPND_SME_Zn_INDEX2_16: + case AARCH64_OPND_SME_Zn_INDEX3_14: + case AARCH64_OPND_SME_Zn_INDEX3_15: + case AARCH64_OPND_SME_Zn_INDEX4_14: snprintf (buf, size, "%s[%s]", - style_reg (styler, "z%d.%s", opnd->reglane.regno, - aarch64_get_qualifier_name (opnd->qualifier)), + (opnd->qualifier == AARCH64_OPND_QLF_NIL + ? style_reg (styler, "z%d", opnd->reglane.regno) + : style_reg (styler, "z%d.%s", opnd->reglane.regno, + aarch64_get_qualifier_name (opnd->qualifier))), style_imm (styler, "%" PRIi64, opnd->reglane.index)); break; @@ -4450,6 +4492,19 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", style_sub_mnem (styler, "csync")); break; + case AARCH64_OPND_SME_ZT0: + snprintf (buf, size, "%s", style_reg (styler, "zt0")); + break; + + case AARCH64_OPND_SME_ZT0_INDEX: + snprintf (buf, size, "%s[%s]", style_reg (styler, "zt0"), + style_imm (styler, "%d", (int) opnd->imm.value)); + break; + + case AARCH64_OPND_SME_ZT0_LIST: + snprintf (buf, size, "{%s}", style_reg (styler, "zt0")); + break; + case AARCH64_OPND_BTI_TARGET: if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0) snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h index e505786e60e..8422be4c9db 100644 --- a/opcodes/aarch64-opc.h +++ b/opcodes/aarch64-opc.h @@ -70,6 +70,7 @@ enum aarch64_field_kind FLD_SME_Zt3, FLD_SME_Zt2, FLD_SME_i1, + FLD_SME_size_12, FLD_SME_size_22, FLD_SME_tszh, FLD_SME_tszl, @@ -139,14 +140,21 @@ enum aarch64_field_kind FLD_defgh, FLD_hw, FLD_imm1_8, + FLD_imm1_16, FLD_imm2_8, + FLD_imm2_15, + FLD_imm2_16, FLD_imm3_0, FLD_imm3_5, FLD_imm3_10, + FLD_imm3_12, + FLD_imm3_14, + FLD_imm3_15, FLD_imm4_0, FLD_imm4_5, FLD_imm4_10, FLD_imm4_11, + FLD_imm4_14, FLD_imm5, FLD_imm6_10, FLD_imm6_15, @@ -242,7 +250,10 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma, #define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */ #define OPD_F_OD_LSB 5 #define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */ -#define OPD_F_SHIFT_BY_4 0x00000400 /* Need to left shift the field +#define OPD_F_SHIFT_BY_3 0x00000400 /* Need to left shift the field + value by 3 to get the value + of an immediate operand. */ +#define OPD_F_SHIFT_BY_4 0x00000800 /* Need to left shift the field value by 4 to get the value of an immediate operand. */ @@ -329,6 +340,12 @@ operand_need_shift_by_two (const aarch64_operand *operand) return (operand->flags & OPD_F_SHIFT_BY_2) != 0; } +static inline bool +operand_need_shift_by_three (const aarch64_operand *operand) +{ + return (operand->flags & OPD_F_SHIFT_BY_3) != 0; +} + static inline bool operand_need_shift_by_four (const aarch64_operand *operand) { diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index cff35b127bd..0f881681aab 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1755,6 +1755,10 @@ { \ QLF3(NIL,NIL,S_S), \ } +#define OP_SVE_UX \ +{ \ + QLF2(NIL,X), \ +} #define OP_SVE_VMR_BHSD \ { \ QLF3(S_B,P_M,W), \ @@ -1905,6 +1909,12 @@ QLF3(S_S,NIL,W), \ QLF3(S_D,NIL,X), \ } +#define OP_SVE_VUU_BHS \ +{ \ + QLF3(S_B,NIL,NIL), \ + QLF3(S_H,NIL,NIL), \ + QLF3(S_S,NIL,NIL), \ +} #define OP_SVE_VUU_BHSD \ { \ QLF3(S_B,NIL,NIL), \ @@ -1919,6 +1929,11 @@ QLF4(S_S,NIL,S_S,S_S), \ QLF4(S_D,NIL,S_D,S_D), \ } +#define OP_SVE_VUU_HS \ +{ \ + QLF3(S_H,NIL,NIL), \ + QLF3(S_S,NIL,NIL), \ +} #define OP_SVE_VUVV_HSD \ { \ QLF4(S_H,NIL,S_H,S_H), \ @@ -5375,6 +5390,13 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("ldnt1w", 0xa000c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), SME2_INSN ("ldnt1w", 0xa1004008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), SME2_INSN ("ldnt1w", 0xa100c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, 0, 0), + SME2_INSN ("ldr", 0xe11f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), + SME2_INSN ("luti2", 0xc0cc0000, 0xfffc0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX4_14), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti2", 0xc08c4000, 0xfffc4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX3_15), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti2", 0xc08c8000, 0xfffccc03, sme_size_12_bhs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX2_16), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc0ca0000, 0xfffe0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX3_14), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc08a4000, 0xfffe4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BHS, 0, 0), + SME2_INSN ("luti4", 0xc08a8000, 0xfffecc03, sme_size_12_hs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_VUU_HS, 0, 0), SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0), SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0), SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0), @@ -5391,6 +5413,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0), SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0), SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0), + SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0), + SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0), SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0), SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0), SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0), @@ -5460,6 +5484,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0), + SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0), SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), @@ -5468,6 +5493,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0), + SME2_INSN ("zero", 0xc0480001, 0xffffffff, sme_misc, 0, OP1 (SME_ZT0_LIST), {}, 0, 0), /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -6178,10 +6204,26 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \ F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \ "Source scalable predicate register with index ") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX1_16", 0, \ + F(FLD_SVE_Zn, FLD_imm1_16), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_15", 0, \ + F(FLD_SVE_Zn, FLD_imm2_15), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX2_16", 0, \ + F(FLD_SVE_Zn, FLD_imm2_16), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX3_14", 0, \ + F(FLD_SVE_Zn, FLD_imm3_14), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX3_15", 0, \ + F(FLD_SVE_Zn, FLD_imm3_15), "an indexed SVE vector register") \ + Y(SVE_REG, simple_index, "SME_Zn_INDEX4_14", 0, \ + F(FLD_SVE_Zn, FLD_imm4_14), "an indexed SVE vector register") \ Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \ "VLx2 or VLx4") \ Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \ "VLx2 or VLx4") \ + Y(SYSTEM, none, "SME_ZT0", 0, F (), "ZT0") \ + Y(IMMEDIATE, imm, "SME_ZT0_INDEX", OPD_F_SHIFT_BY_3, \ + F (FLD_imm3_12), "a ZT0 index") \ + Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \