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[8.43.85.97]) by mx.google.com with ESMTPS id mf27-20020a170906cb9b00b0093c96e490a8si17946090ejb.202.2023.03.30.03.27.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:27:13 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=u1lgqiTU; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D9AC3882125 for ; Thu, 30 Mar 2023 10:25:45 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7D9AC3882125 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680171945; bh=DVLxyJKhmn39rDvDReQMnDGKDtterTEN/wZ6xhcmCEU=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=u1lgqiTU3rLFxPPMIBk2T6MuR5v4PudZYPh3Sex2na9mVcgzPxT9WvsNNX2xKw+Dv C2OXiLA0bKHcdPK9o3bzpABJpw/M1P7OLPv5rxSN300NDAnEK+XaY1Z+j9HWOR2S89 yKhaugwC8gmNwa67PGl8o3ocTVD0RAPOG9TXlDEM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id 6082A385842B for ; Thu, 30 Mar 2023 10:24:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6082A385842B Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 98B6E12FC; Thu, 30 Mar 2023 03:25:04 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CFD0A3F663; Thu, 30 Mar 2023 03:24:19 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 08/43] aarch64: Move vectype_to_qualifier further up Date: Thu, 30 Mar 2023 11:23:24 +0100 Message-Id: <20230330102359.3327695-9-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-33.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761788069882351132?= X-GMAIL-MSGID: =?utf-8?q?1761788069882351132?= This patch just moves vectype_to_qualifier further up, so that a later patch can call it at an earlier point in the file. No behavioural change intended. --- gas/config/tc-aarch64.c | 150 ++++++++++++++++++++-------------------- 1 file changed, 75 insertions(+), 75 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 98091f564d9..7de0f5c83f6 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -694,6 +694,81 @@ first_error_fmt (const char *format, ...) } } +/* Internal helper routine converting a vector_type_el structure *VECTYPE + to a corresponding operand qualifier. */ + +static inline aarch64_opnd_qualifier_t +vectype_to_qualifier (const struct vector_type_el *vectype) +{ + /* Element size in bytes indexed by vector_el_type. */ + const unsigned char ele_size[5] + = {1, 2, 4, 8, 16}; + const unsigned int ele_base [5] = + { + AARCH64_OPND_QLF_V_4B, + AARCH64_OPND_QLF_V_2H, + AARCH64_OPND_QLF_V_2S, + AARCH64_OPND_QLF_V_1D, + AARCH64_OPND_QLF_V_1Q + }; + + if (!vectype->defined || vectype->type == NT_invtype) + goto vectype_conversion_fail; + + if (vectype->type == NT_zero) + return AARCH64_OPND_QLF_P_Z; + if (vectype->type == NT_merge) + return AARCH64_OPND_QLF_P_M; + + gas_assert (vectype->type >= NT_b && vectype->type <= NT_q); + + if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH)) + { + /* Special case S_4B. */ + if (vectype->type == NT_b && vectype->width == 4) + return AARCH64_OPND_QLF_S_4B; + + /* Special case S_2H. */ + if (vectype->type == NT_h && vectype->width == 2) + return AARCH64_OPND_QLF_S_2H; + + /* Vector element register. */ + return AARCH64_OPND_QLF_S_B + vectype->type; + } + else + { + /* Vector register. */ + int reg_size = ele_size[vectype->type] * vectype->width; + unsigned offset; + unsigned shift; + if (reg_size != 16 && reg_size != 8 && reg_size != 4) + goto vectype_conversion_fail; + + /* The conversion is by calculating the offset from the base operand + qualifier for the vector type. The operand qualifiers are regular + enough that the offset can established by shifting the vector width by + a vector-type dependent amount. */ + shift = 0; + if (vectype->type == NT_b) + shift = 3; + else if (vectype->type == NT_h || vectype->type == NT_s) + shift = 2; + else if (vectype->type >= NT_d) + shift = 1; + else + gas_assert (0); + + offset = ele_base [vectype->type] + (vectype->width >> shift); + gas_assert (AARCH64_OPND_QLF_V_4B <= offset + && offset <= AARCH64_OPND_QLF_V_1Q); + return offset; + } + + vectype_conversion_fail: + first_error (_("bad vector arrangement type")); + return AARCH64_OPND_QLF_NIL; +} + /* Register parsing. */ /* Generic register parser which is called by other specialized @@ -5905,81 +5980,6 @@ opcode_lookup (char *base, char *dot, char *end) return NULL; } -/* Internal helper routine converting a vector_type_el structure *VECTYPE - to a corresponding operand qualifier. */ - -static inline aarch64_opnd_qualifier_t -vectype_to_qualifier (const struct vector_type_el *vectype) -{ - /* Element size in bytes indexed by vector_el_type. */ - const unsigned char ele_size[5] - = {1, 2, 4, 8, 16}; - const unsigned int ele_base [5] = - { - AARCH64_OPND_QLF_V_4B, - AARCH64_OPND_QLF_V_2H, - AARCH64_OPND_QLF_V_2S, - AARCH64_OPND_QLF_V_1D, - AARCH64_OPND_QLF_V_1Q - }; - - if (!vectype->defined || vectype->type == NT_invtype) - goto vectype_conversion_fail; - - if (vectype->type == NT_zero) - return AARCH64_OPND_QLF_P_Z; - if (vectype->type == NT_merge) - return AARCH64_OPND_QLF_P_M; - - gas_assert (vectype->type >= NT_b && vectype->type <= NT_q); - - if (vectype->defined & (NTA_HASINDEX | NTA_HASVARWIDTH)) - { - /* Special case S_4B. */ - if (vectype->type == NT_b && vectype->width == 4) - return AARCH64_OPND_QLF_S_4B; - - /* Special case S_2H. */ - if (vectype->type == NT_h && vectype->width == 2) - return AARCH64_OPND_QLF_S_2H; - - /* Vector element register. */ - return AARCH64_OPND_QLF_S_B + vectype->type; - } - else - { - /* Vector register. */ - int reg_size = ele_size[vectype->type] * vectype->width; - unsigned offset; - unsigned shift; - if (reg_size != 16 && reg_size != 8 && reg_size != 4) - goto vectype_conversion_fail; - - /* The conversion is by calculating the offset from the base operand - qualifier for the vector type. The operand qualifiers are regular - enough that the offset can established by shifting the vector width by - a vector-type dependent amount. */ - shift = 0; - if (vectype->type == NT_b) - shift = 3; - else if (vectype->type == NT_h || vectype->type == NT_s) - shift = 2; - else if (vectype->type >= NT_d) - shift = 1; - else - gas_assert (0); - - offset = ele_base [vectype->type] + (vectype->width >> shift); - gas_assert (AARCH64_OPND_QLF_V_4B <= offset - && offset <= AARCH64_OPND_QLF_V_1Q); - return offset; - } - - vectype_conversion_fail: - first_error (_("bad vector arrangement type")); - return AARCH64_OPND_QLF_NIL; -} - /* Process an optional operand that is found omitted from the assembly line. Fill *OPERAND for such an operand of type TYPE. OPCODE points to the instruction's opcode entry while IDX is the index of this omitted operand.