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[8.43.85.97]) by mx.google.com with ESMTPS id dn17-20020a17090794d100b00946bd148b48si8821138ejc.391.2023.03.30.03.57.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:57:04 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Li5y0Ktv; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 60C3338A90BB for ; Thu, 30 Mar 2023 10:39:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 60C3338A90BB DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172796; bh=EgItuzMDn26TGF2abCIXJaCqG4x97eHodoDKYKGoZZE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=Li5y0Ktvr5b7ppfWfsPQaOKoaIEsJd61JMWdnHA+sQVALMtjWQBna7Wdp7QFciseE Q6+D0qq7xxI1JNj5fpr1ORNewvPtY926tznna/wEyifNvlQTu51AeA6MVnEsTb4pnK Y0rwY8z5k0c4YGIbsGAp4xLPjt4spXC+5b0cwcII= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id D562B3851ABF for ; Thu, 30 Mar 2023 10:24:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D562B3851ABF Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 13BC12F4; Thu, 30 Mar 2023 03:25:25 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4AD6E3F663; Thu, 30 Mar 2023 03:24:40 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper Date: Thu, 30 Mar 2023 11:23:53 +0100 Message-Id: <20230330102359.3327695-38-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761789948394386911?= X-GMAIL-MSGID: =?utf-8?q?1761789948394386911?= Quite a lot of SME2 instructions have an opcode bit that selects between 32-bit and 64-bit forms of an instruction, with the 32-bit forms being part of base SME2 and with the 64-bit forms being part of an optional extension. It's nevertheless useful to have a single opcode entry for both forms since (a) that matches the ISA definition and (b) it tends to improve error reporting. This patch therefore adds a libopcodes function called aarch64_cpu_supports_inst_p that tests whether the target supports a particular instruction. In future it will depend on internal libopcodes routines. --- gas/config/tc-aarch64.c | 3 +-- include/opcode/aarch64.h | 3 +++ opcodes/aarch64-opc.c | 13 +++++++++++++ 3 files changed, 17 insertions(+), 2 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index c8e37623d9e..71b63d3f7b3 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -8116,8 +8116,7 @@ md_assemble (char *str) && do_encode (inst_base->opcode, &inst.base, &inst_base->value)) { /* Check that this instruction is supported for this CPU. */ - if (!opcode->avariant - || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant)) + if (!aarch64_cpu_supports_inst_p (cpu_variant, inst_base)) { as_bad (_("selected processor does not support `%s'"), str); return; diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index d09897f48d4..61afe561a12 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1471,6 +1471,9 @@ aarch64_get_operand_desc (enum aarch64_opnd); extern bool aarch64_sve_dupm_mov_immediate_p (uint64_t, int); +extern bool +aarch64_cpu_supports_inst_p (uint64_t, aarch64_inst *); + #ifdef DEBUG_AARCH64 extern int debug_dump; diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index b9029010c47..7a88c19633d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -6158,6 +6158,19 @@ aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize) return svalue < -128 || svalue >= 128; } +/* Return true if a CPU with the AARCH64_FEATURE_* bits in CPU_VARIANT + supports the instruction described by INST. */ + +bool +aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst) +{ + if (!inst->opcode->avariant + || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant)) + return false; + + return true; +} + /* Include the opcode description table as well as the operand description table. */ #define VERIFIER(x) verify_##x