diff mbox series

[37/43] aarch64: Add a aarch64_cpu_supports_inst_p helper

Message ID 20230330102359.3327695-38-richard.sandiford@arm.com
State Unresolved
Headers
Series aarch64: Groundwork for SME2 support |

Checks

Context Check Description
snail/binutils-gdb-check warning Git am fail log

Commit Message

Richard Sandiford March 30, 2023, 10:23 a.m. UTC 
  Quite a lot of SME2 instructions have an opcode bit that selects
between 32-bit and 64-bit forms of an instruction, with the 32-bit
forms being part of base SME2 and with the 64-bit forms being part
of an optional extension.  It's nevertheless useful to have a single
opcode entry for both forms since (a) that matches the ISA definition
and (b) it tends to improve error reporting.

This patch therefore adds a libopcodes function called
aarch64_cpu_supports_inst_p that tests whether the target
supports a particular instruction.  In future it will depend
on internal libopcodes routines.
---
 gas/config/tc-aarch64.c  |  3 +--
 include/opcode/aarch64.h |  3 +++
 opcodes/aarch64-opc.c    | 13 +++++++++++++
 3 files changed, 17 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index c8e37623d9e..71b63d3f7b3 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8116,8 +8116,7 @@  md_assemble (char *str)
 	  && do_encode (inst_base->opcode, &inst.base, &inst_base->value))
 	{
 	  /* Check that this instruction is supported for this CPU.  */
-	  if (!opcode->avariant
-	      || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *opcode->avariant))
+	  if (!aarch64_cpu_supports_inst_p (cpu_variant, inst_base))
 	    {
 	      as_bad (_("selected processor does not support `%s'"), str);
 	      return;
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index d09897f48d4..61afe561a12 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1471,6 +1471,9 @@  aarch64_get_operand_desc (enum aarch64_opnd);
 extern bool
 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
 
+extern bool
+aarch64_cpu_supports_inst_p (uint64_t, aarch64_inst *);
+
 #ifdef DEBUG_AARCH64
 extern int debug_dump;
 
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b9029010c47..7a88c19633d 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -6158,6 +6158,19 @@  aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
   return svalue < -128 || svalue >= 128;
 }
 
+/* Return true if a CPU with the AARCH64_FEATURE_* bits in CPU_VARIANT
+   supports the instruction described by INST.  */
+
+bool
+aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst)
+{
+  if (!inst->opcode->avariant
+      || !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant))
+    return false;
+
+  return true;
+}
+
 /* Include the opcode description table as well as the operand description
    table.  */
 #define VERIFIER(x) verify_##x