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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id xa4-20020a170907b9c400b009311eb6863dsi34403379ejc.634.2023.03.30.03.35.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:35:06 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=JIHjSzuX; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9A6313894C12 for ; Thu, 30 Mar 2023 10:29:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9A6313894C12 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172183; bh=qSMZ2nBdfv+dV1YKguLKWKVPEIYs23qFZv7wTvl5xMI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=JIHjSzuXJaBHP/feS8JBNvi3PwrSLFJaWhknEb69hKlRxV/zemYoAGbeLINk2vqiT Kjua4bQ4tHR2MWr7dE5JPFEsNdhwHKsXlcxmEZ5nVmtaht++JWABqwJw6a/L97P/fH AQe1xPBITe3/6ZImWda2MCiu88PKs+j6pOqR86Lk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id B354D3858288 for ; Thu, 30 Mar 2023 10:24:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B354D3858288 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1AAB2F4; Thu, 30 Mar 2023 03:25:18 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 24A2F3F663; Thu, 30 Mar 2023 03:24:34 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 28/43] aarch64: Add an error code for out-of-range registers Date: Thu, 30 Mar 2023 11:23:44 +0100 Message-Id: <20230330102359.3327695-29-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-32.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761788565870196433?= X-GMAIL-MSGID: =?utf-8?q?1761788565870196433?= libopcodes currently reports out-of-range registers as a general AARCH64_OPDE_OTHER_ERROR. However, this means that each register range needs its own hard-coded string, which is a bit cumbersome if the range is determined programmatically. This patch therefore adds a dedicated error type for out-of-range errors. --- gas/config/tc-aarch64.c | 8 ++++++++ include/opcode/aarch64.h | 10 +++++++++- opcodes/aarch64-opc.c | 20 ++++++++++++++------ 3 files changed, 31 insertions(+), 7 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 86d5ba992ff..145e241b13b 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -5057,6 +5057,7 @@ const char* operand_mismatch_kind_names[] = "AARCH64_OPDE_OUT_OF_RANGE", "AARCH64_OPDE_UNALIGNED", "AARCH64_OPDE_OTHER_ERROR", + "AARCH64_OPDE_INVALID_REGNO", }; #endif /* DEBUG_AARCH64 */ @@ -5081,6 +5082,7 @@ operand_error_higher_severity_p (enum aarch64_operand_error_kind lhs, gas_assert (AARCH64_OPDE_OUT_OF_RANGE > AARCH64_OPDE_REG_LIST); gas_assert (AARCH64_OPDE_UNALIGNED > AARCH64_OPDE_OUT_OF_RANGE); gas_assert (AARCH64_OPDE_OTHER_ERROR > AARCH64_OPDE_REG_LIST); + gas_assert (AARCH64_OPDE_INVALID_REGNO > AARCH64_OPDE_OTHER_ERROR); return lhs > rhs; } @@ -5712,6 +5714,12 @@ output_operand_error_record (const operand_error_record *record, char *str) detail->index + 1, str); break; + case AARCH64_OPDE_INVALID_REGNO: + handler (_("%s%d-%s%d expected at operand %d -- `%s'"), + detail->data[0].s, detail->data[1].i, + detail->data[0].s, detail->data[2].i, idx + 1, str); + break; + case AARCH64_OPDE_OUT_OF_RANGE: if (detail->data[0].i != detail->data[1].i) handler (_("%s out of range %d to %d at operand %d -- `%s'"), diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 10c7983aa2d..6615dec41a7 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1311,6 +1311,13 @@ struct aarch64_inst Error of the highest severity and used for any severe issue that does not fall into any of the above categories. + AARCH64_OPDE_INVALID_REGNO + A register was syntactically valid and had the right type, but it was + outside the range supported by the associated operand field. This is + a high severity error because there are currently no instructions that + would accept the operands that precede the erroneous one (if any) and + yet still accept a wider range of registers. + AARCH64_OPDE_RECOVERABLE, AARCH64_OPDE_SYNTAX_ERROR and AARCH64_OPDE_FATAL_SYNTAX_ERROR are only deteced by GAS while the AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as @@ -1339,7 +1346,8 @@ enum aarch64_operand_error_kind AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPDE_OUT_OF_RANGE, AARCH64_OPDE_UNALIGNED, - AARCH64_OPDE_OTHER_ERROR + AARCH64_OPDE_OTHER_ERROR, + AARCH64_OPDE_INVALID_REGNO }; /* N.B. GAS assumes that this structure work well with shallow copy. */ diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 24cca9e8193..c36e4cc67f6 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1335,6 +1335,18 @@ set_syntax_error (aarch64_operand_error *mismatch_detail, int idx, set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error); } +static inline void +set_invalid_regno_error (aarch64_operand_error *mismatch_detail, int idx, + const char *prefix, int lower_bound, int upper_bound) +{ + if (mismatch_detail == NULL) + return; + set_error (mismatch_detail, AARCH64_OPDE_INVALID_REGNO, idx, NULL); + mismatch_detail->data[0].s = prefix; + mismatch_detail->data[1].i = lower_bound; + mismatch_detail->data[2].i = upper_bound; +} + static inline void set_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound, @@ -1569,11 +1581,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, mask = (1 << shift) - 1; if (opnd->reg.regno > mask) { - assert (mask == 7 || mask == 15); - set_other_error (mismatch_detail, idx, - mask == 15 - ? _("z0-z15 expected") - : _("z0-z7 expected")); + set_invalid_regno_error (mismatch_detail, idx, "z", 0, mask); return 0; } mask = (1u << (size - shift)) - 1; @@ -1642,7 +1650,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, if (opnd->reg.regno >= 8 && get_operand_fields_width (get_operand_from_code (type)) == 3) { - set_other_error (mismatch_detail, idx, _("p0-p7 expected")); + set_invalid_regno_error (mismatch_detail, idx, "p", 0, 7); return 0; } break;