diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 616454b584e..fac027ab7b8 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -161,6 +161,32 @@ static aarch64_instruction inst;
 static bool parse_operands (char *, const aarch64_opcode *);
 static bool programmer_friendly_fixup (aarch64_instruction *);
 
+/* If an AARCH64_OPDE_SYNTAX_ERROR has no error string, its first three
+   data fields contain the following information:
+
+   data[0].i:
+     A mask of register types that would have been acceptable as bare
+     operands, outside of a register list.  In addition, SEF_DEFAULT_ERROR
+     is set if a general parsing error occured for an operand (that is,
+     an error not related to registers, and having no error string).
+
+   data[1].i:
+     A mask of register types that would have been acceptable inside
+     a register list.  In addition, SEF_IN_REGLIST is set if the
+     operand contained a '{' and if we got to the point of trying
+     to parse a register inside a list.
+
+   data[2].i:
+     The mask associated with the register that was actually seen, or 0
+     if none.  A nonzero value describes a register inside a register
+     list if data[1].i & SEF_IN_REGLIST, otherwise it describes a bare
+     register.
+
+   The idea is that stringless errors from multiple opcode templates can
+   be ORed together to give a summary of the available alternatives.  */
+#define SEF_DEFAULT_ERROR (1U << 31)
+#define SEF_IN_REGLIST (1U << 31)
+
 /* Diagnostics inline function utilities.
 
    These are lightweight utilities which should only be called by parse_operands
@@ -212,6 +238,14 @@ static inline void
 set_default_error (void)
 {
   set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+  inst.parsing_error.data[0].i = SEF_DEFAULT_ERROR;
+}
+
+static inline void
+set_expected_error (unsigned int flags)
+{
+  set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+  inst.parsing_error.data[0].i = flags;
 }
 
 static inline void
@@ -317,17 +351,25 @@ struct reloc_entry
   MULTI_REG_TYPE(R_N, REG_TYPE(R_32) | REG_TYPE(R_64)			\
 		 | REG_TYPE(SP_32) | REG_TYPE(SP_64)			\
 		 | REG_TYPE(Z_32) | REG_TYPE(Z_64))			\
+  /* Any vector register.  */						\
+  MULTI_REG_TYPE(VZ, REG_TYPE(VN) | REG_TYPE(ZN))			\
+  /* An SVE vector or predicate register.  */				\
+  MULTI_REG_TYPE(ZP, REG_TYPE(ZN) | REG_TYPE(PN))			\
+  /* Any vector or predicate register.  */				\
+  MULTI_REG_TYPE(VZP, REG_TYPE(VN) | REG_TYPE(ZN) | REG_TYPE(PN))	\
   /* The whole of ZA or a single tile.  */				\
   MULTI_REG_TYPE(ZA_ZAT, REG_TYPE(ZA) | REG_TYPE(ZAT))			\
   /* A horizontal or vertical slice of a ZA tile.  */			\
   MULTI_REG_TYPE(ZATHV, REG_TYPE(ZATH) | REG_TYPE(ZATV))		\
   /* Pseudo type to mark the end of the enumerator sequence.  */	\
-  BASIC_REG_TYPE(MAX)
+  END_REG_TYPE(MAX)
 
 #undef BASIC_REG_TYPE
 #define BASIC_REG_TYPE(T)	REG_TYPE_##T,
 #undef MULTI_REG_TYPE
 #define MULTI_REG_TYPE(T,V)	BASIC_REG_TYPE(T)
+#undef END_REG_TYPE
+#define END_REG_TYPE(T)		BASIC_REG_TYPE(T)
 
 /* Register type enumerators.  */
 typedef enum aarch64_reg_type_
@@ -342,6 +384,8 @@ typedef enum aarch64_reg_type_
 #define REG_TYPE(T)		(1 << REG_TYPE_##T)
 #undef MULTI_REG_TYPE
 #define MULTI_REG_TYPE(T,V)	V,
+#undef END_REG_TYPE
+#define END_REG_TYPE(T)		0
 
 /* Structure for a hash table entry for a register.  */
 typedef struct
@@ -361,84 +405,129 @@ static const unsigned reg_type_masks[] =
 #undef BASIC_REG_TYPE
 #undef REG_TYPE
 #undef MULTI_REG_TYPE
+#undef END_REG_TYPE
 #undef AARCH64_REG_TYPES
 
-/* Diagnostics used when we don't get a register of the expected type.
-   Note:  this has to synchronized with aarch64_reg_type definitions
-   above.  */
+/* We expected one of the registers in MASK to be specified.  If a register
+   of some kind was specified, SEEN is a mask that contains that register,
+   otherwise it is zero.
+
+   If it is possible to provide a relatively pithy message that describes
+   the error exactly, return a string that does so, reporting the error
+   against "operand %d".  Return null otherwise.
+
+   From a QoI perspective, any REG_TYPE_* that is passed as the first
+   argument to set_expected_reg_error should generally have its own message.
+   Providing messages for combinations of such REG_TYPE_*s can be useful if
+   it is possible to summarize the combination in a relatively natural way.
+   On the other hand, it seems better to avoid long lists of unrelated
+   things.  */
+
 static const char *
-get_reg_expected_msg (aarch64_reg_type reg_type)
+get_reg_expected_msg (unsigned int mask, unsigned int seen)
+{
+  /* First handle messages that use SEEN.  */
+  if ((mask & reg_type_masks[REG_TYPE_ZAT])
+      && (seen & reg_type_masks[REG_TYPE_ZATHV]))
+    return N_("expected an unsuffixed ZA tile at operand %d");
+
+  if ((mask & reg_type_masks[REG_TYPE_ZATHV])
+      && (seen & reg_type_masks[REG_TYPE_ZAT]))
+    return N_("missing horizontal or vertical suffix at operand %d");
+
+  if ((mask & reg_type_masks[REG_TYPE_ZA])
+      && (seen & (reg_type_masks[REG_TYPE_ZAT]
+		  | reg_type_masks[REG_TYPE_ZATHV])))
+    return N_("expected 'za' rather than a ZA tile at operand %d");
+
+  /* Integer, zero and stack registers.  */
+  if (mask == reg_type_masks[REG_TYPE_R_64])
+    return N_("expected a 64-bit integer register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_R_Z])
+    return N_("expected an integer or zero register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_R_SP])
+    return N_("expected an integer or stack pointer register at operand %d");
+
+  /* Floating-point and SIMD registers.  */
+  if (mask == reg_type_masks[REG_TYPE_BHSDQ])
+    return N_("expected a scalar SIMD or floating-point register"
+	      " at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_VN])
+    return N_("expected an Advanced SIMD vector register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_ZN])
+    return N_("expected an SVE vector register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_PN])
+    return N_("expected an SVE predicate register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_VZ])
+    return N_("expected a vector register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_ZP])
+    return N_("expected an SVE vector or predicate register at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_VZP])
+    return N_("expected a vector or predicate register at operand %d");
+
+  /* ZA-related registers.  */
+  if (mask == reg_type_masks[REG_TYPE_ZA])
+    return N_("expected a ZA array vector at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_ZA_ZAT])
+    return N_("expected 'za' or a ZA tile at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_ZAT])
+    return N_("expected a ZA tile at operand %d");
+  if (mask == reg_type_masks[REG_TYPE_ZATHV])
+    return N_("expected a ZA tile slice at operand %d");
+
+  /* Integer and vector combos.  */
+  if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VN]))
+    return N_("expected an integer register or Advanced SIMD vector register"
+	      " at operand %d");
+  if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_ZN]))
+    return N_("expected an integer register or SVE vector register"
+	      " at operand %d");
+  if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZ]))
+    return N_("expected an integer or vector register at operand %d");
+  if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_PN]))
+    return N_("expected an integer or predicate register at operand %d");
+  if (mask == (reg_type_masks[REG_TYPE_R_Z] | reg_type_masks[REG_TYPE_VZP]))
+    return N_("expected an integer, vector or predicate register"
+	      " at operand %d");
+
+  /* SVE and SME combos.  */
+  if (mask == (reg_type_masks[REG_TYPE_ZN] | reg_type_masks[REG_TYPE_ZATHV]))
+    return N_("expected an SVE vector register or ZA tile slice"
+	      " at operand %d");
+
+  return NULL;
+}
+
+/* Record that we expected a register of type TYPE but didn't see one.
+   REG is the register that we actually saw, or null if we didn't see a
+   recognized register.  FLAGS is SEF_IN_REGLIST if we are parsing the
+   contents of a register list, otherwise it is zero.  */
+
+static inline void
+set_expected_reg_error (aarch64_reg_type type, const reg_entry *reg,
+			unsigned int flags)
 {
-  const char *msg;
+  assert (flags == 0 || flags == SEF_IN_REGLIST);
+  set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+  if (flags & SEF_IN_REGLIST)
+    inst.parsing_error.data[1].i = reg_type_masks[type] | flags;
+  else
+    inst.parsing_error.data[0].i = reg_type_masks[type];
+  if (reg)
+    inst.parsing_error.data[2].i = reg_type_masks[reg->type];
+}
 
-  switch (reg_type)
-    {
-    case REG_TYPE_R_32:
-      msg = N_("integer 32-bit register expected");
-      break;
-    case REG_TYPE_R_64:
-      msg = N_("integer 64-bit register expected");
-      break;
-    case REG_TYPE_R_N:
-      msg = N_("integer register expected");
-      break;
-    case REG_TYPE_R64_SP:
-      msg = N_("64-bit integer or SP register expected");
-      break;
-    case REG_TYPE_SVE_BASE:
-      msg = N_("base register expected");
-      break;
-    case REG_TYPE_R_Z:
-      msg = N_("integer or zero register expected");
-      break;
-    case REG_TYPE_SVE_OFFSET:
-      msg = N_("offset register expected");
-      break;
-    case REG_TYPE_R_SP:
-      msg = N_("integer or SP register expected");
-      break;
-    case REG_TYPE_R_Z_SP:
-      msg = N_("integer, zero or SP register expected");
-      break;
-    case REG_TYPE_FP_B:
-      msg = N_("8-bit SIMD scalar register expected");
-      break;
-    case REG_TYPE_FP_H:
-      msg = N_("16-bit SIMD scalar or floating-point half precision "
-	       "register expected");
-      break;
-    case REG_TYPE_FP_S:
-      msg = N_("32-bit SIMD scalar or floating-point single precision "
-	       "register expected");
-      break;
-    case REG_TYPE_FP_D:
-      msg = N_("64-bit SIMD scalar or floating-point double precision "
-	       "register expected");
-      break;
-    case REG_TYPE_FP_Q:
-      msg = N_("128-bit SIMD scalar or floating-point quad precision "
-	       "register expected");
-      break;
-    case REG_TYPE_R_Z_BHSDQ_V:
-    case REG_TYPE_R_Z_SP_BHSDQ_VZP:
-      msg = N_("register expected");
-      break;
-    case REG_TYPE_BHSDQ:	/* any [BHSDQ]P FP  */
-      msg = N_("SIMD scalar or floating-point register expected");
-      break;
-    case REG_TYPE_VN:		/* any V reg  */
-      msg = N_("vector register expected");
-      break;
-    case REG_TYPE_ZN:
-      msg = N_("SVE vector register expected");
-      break;
-    case REG_TYPE_PN:
-      msg = N_("SVE predicate register expected");
-      break;
-    default:
-      as_fatal (_("invalid register type %d"), reg_type);
-    }
-  return msg;
+/* Record that we expected a register list containing registers of type TYPE,
+   but didn't see the opening '{'.  If we saw a register instead, REG is the
+   register that we saw, otherwise it is null.  */
+
+static inline void
+set_expected_reglist_error (aarch64_reg_type type, const reg_entry *reg)
+{
+  set_error (AARCH64_OPDE_SYNTAX_ERROR, NULL);
+  inst.parsing_error.data[1].i = reg_type_masks[type];
+  if (reg)
+    inst.parsing_error.data[2].i = reg_type_masks[reg->type];
 }
 
 /* Some well known registers that we refer to directly elsewhere.  */
@@ -1092,6 +1181,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
   struct vector_type_el atype;
   struct vector_type_el parsetype;
   bool is_typed_vecreg = false;
+  unsigned int err_flags = (flags & PTR_IN_REGLIST) ? SEF_IN_REGLIST : 0;
 
   atype.defined = 0;
   atype.type = NT_invtype;
@@ -1108,7 +1198,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
       else if (flags & PTR_GOOD_MATCH)
 	set_fatal_syntax_error (NULL);
       else
-	set_default_error ();
+	set_expected_reg_error (type, reg, err_flags);
       return NULL;
     }
 
@@ -1118,7 +1208,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
       if (flags & PTR_GOOD_MATCH)
 	set_fatal_syntax_error (NULL);
       else
-	set_default_error ();
+	set_expected_reg_error (type, reg, err_flags);
       return NULL;
     }
   type = reg->type;
@@ -1275,7 +1365,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
 
   if (*str != '{')
     {
-      set_syntax_error (_("expecting {"));
+      set_expected_reglist_error (type, parse_reg (&str));
       return PARSE_FAIL;
     }
   str++;
@@ -3612,7 +3702,7 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand,
 
       if (!aarch64_check_reg_type (reg, REG_TYPE_R_Z))
 	{
-	  set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_Z)));
+	  set_expected_reg_error (REG_TYPE_R_Z, reg, 0);
 	  return false;
 	}
 
@@ -4110,7 +4200,7 @@ parse_x0_to_x30 (char **str, aarch64_opnd_info *operand)
   const reg_entry *reg = parse_reg (str);
   if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R_64))
     {
-      set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
+      set_expected_reg_error (REG_TYPE_R_64, reg, 0);
       return false;
     }
   operand->reg.regno = reg->number;
@@ -4509,7 +4599,7 @@ parse_sme_za_hv_tiles_operand_with_braces (char **str,
 {
   if (!skip_past_char (str, '{'))
     {
-      set_syntax_error (_("expected '{'"));
+      set_expected_reglist_error (REG_TYPE_ZATHV, parse_reg (str));
       return false;
     }
 
@@ -4783,17 +4873,14 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
 #define po_reg_or_fail(regtype) do {				\
     reg = aarch64_reg_parse (&str, regtype, NULL);		\
     if (!reg)							\
-      {								\
-	set_default_error ();					\
-	goto failure;						\
-      }								\
+      goto failure;						\
   } while (0)
 
 #define po_int_fp_reg_or_fail(reg_type) do {			\
     reg = parse_reg (&str);					\
     if (!reg || !aarch64_check_reg_type (reg, reg_type))	\
       {								\
-	set_default_error ();					\
+	set_expected_reg_error (reg_type, reg, 0);		\
 	goto failure;						\
       }								\
     info->reg.regno = reg->number;				\
@@ -5389,6 +5476,64 @@ output_info (const char *format, ...)
   (void) putc ('\n', stderr);
 }
 
+/* See if the AARCH64_OPDE_SYNTAX_ERROR error described by DETAIL
+   relates to registers or register lists.  If so, return a string that
+   reports the error against "operand %d", otherwise return null.  */
+
+static const char *
+get_reg_error_message (const aarch64_operand_error *detail)
+{
+  /* Handle the case where we found a register that was expected
+     to be in a register list outside of a register list.  */
+  if ((detail->data[1].i & detail->data[2].i) != 0
+      && (detail->data[1].i & SEF_IN_REGLIST) == 0)
+    return _("missing braces at operand %d");
+
+  /* If some opcodes expected a register, and we found a register,
+     complain about the difference.  */
+  if (detail->data[2].i)
+    {
+      unsigned int expected = (detail->data[1].i & SEF_IN_REGLIST
+			       ? detail->data[1].i & ~SEF_IN_REGLIST
+			       : detail->data[0].i & ~SEF_DEFAULT_ERROR);
+      const char *msg = get_reg_expected_msg (expected, detail->data[2].i);
+      if (!msg)
+	msg = N_("unexpected register type at operand %d");
+      return msg;
+    }
+
+  /* Handle the case where we got to the point of trying to parse a
+     register within a register list, but didn't find a known register.  */
+  if (detail->data[1].i & SEF_IN_REGLIST)
+    {
+      unsigned int expected = detail->data[1].i & ~SEF_IN_REGLIST;
+      const char *msg = get_reg_expected_msg (expected, 0);
+      if (!msg)
+	msg = _("invalid register list at operand %d");
+      return msg;
+    }
+
+  /* Punt if register-related problems weren't the only errors.  */
+  if (detail->data[0].i & SEF_DEFAULT_ERROR)
+    return NULL;
+
+  /* Handle the case where the only acceptable things are registers.  */
+  if (detail->data[1].i == 0)
+    {
+      const char *msg = get_reg_expected_msg (detail->data[0].i, 0);
+      if (!msg)
+	msg = _("expected a register at operand %d");
+      return msg;
+    }
+
+  /* Handle the case where the only acceptable things are register lists,
+     and there was no opening '{'.  */
+  if (detail->data[0].i == 0)
+    return _("expected '{' at operand %d");
+
+  return _("expected a register or register list at operand %d");
+}
+
 /* Output one operand error record.  */
 
 static void
@@ -5402,6 +5547,7 @@ output_operand_error_record (const operand_error_record *record, char *str)
 
   typedef void (*handler_t)(const char *format, ...);
   handler_t handler = detail->non_fatal ? as_warn : as_bad;
+  const char *msg = detail->error;
 
   switch (detail->kind)
     {
@@ -5422,18 +5568,31 @@ output_operand_error_record (const operand_error_record *record, char *str)
       break;
 
     case AARCH64_OPDE_SYNTAX_ERROR:
+      if (!msg && idx >= 0)
+	{
+	  msg = get_reg_error_message (detail);
+	  if (msg)
+	    {
+	      char *full_msg = xasprintf (msg, idx + 1);
+	      handler (_("%s -- `%s'"), full_msg, str);
+	      free (full_msg);
+	      break;
+	    }
+	}
+      /* Fall through.  */
+
     case AARCH64_OPDE_RECOVERABLE:
     case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
     case AARCH64_OPDE_OTHER_ERROR:
       /* Use the prepared error message if there is, otherwise use the
 	 operand description string to describe the error.  */
-      if (detail->error != NULL)
+      if (msg != NULL)
 	{
 	  if (idx < 0)
-	    handler (_("%s -- `%s'"), detail->error, str);
+	    handler (_("%s -- `%s'"), msg, str);
 	  else
 	    handler (_("%s at operand %d -- `%s'"),
-		     detail->error, idx + 1, str);
+		     msg, idx + 1, str);
 	}
       else
 	{
@@ -5554,11 +5713,11 @@ output_operand_error_record (const operand_error_record *record, char *str)
     case AARCH64_OPDE_OUT_OF_RANGE:
       if (detail->data[0].i != detail->data[1].i)
 	handler (_("%s out of range %d to %d at operand %d -- `%s'"),
-		 detail->error ? detail->error : _("immediate value"),
+		 msg ? msg : _("immediate value"),
 		 detail->data[0].i, detail->data[1].i, idx + 1, str);
       else
 	handler (_("%s must be %d at operand %d -- `%s'"),
-		 detail->error ? detail->error : _("immediate value"),
+		 msg ? msg : _("immediate value"),
 		 detail->data[0].i, idx + 1, str);
       break;
 
@@ -5600,8 +5759,6 @@ output_operand_error_record (const operand_error_record *record, char *str)
 static void
 output_operand_error_report (char *str, bool non_fatal_only)
 {
-  int largest_error_pos;
-  const char *msg = NULL;
   enum aarch64_operand_error_kind kind;
   operand_error_record *curr;
   operand_error_record *head = operand_error_report.head;
@@ -5633,7 +5790,17 @@ output_operand_error_report (char *str, bool non_fatal_only)
   for (curr = head; curr != NULL; curr = curr->next)
     {
       gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
-      DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
+      if (curr->detail.kind == AARCH64_OPDE_SYNTAX_ERROR)
+	{
+	  DEBUG_TRACE ("\t%s [%x, %x, %x]",
+		       operand_mismatch_kind_names[curr->detail.kind],
+		       curr->detail.data[0].i, curr->detail.data[1].i,
+		       curr->detail.data[2].i);
+	}
+      else
+	{
+	  DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
+	}
       if (operand_error_higher_severity_p (curr->detail.kind, kind)
 	  && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
 	kind = curr->detail.kind;
@@ -5642,7 +5809,6 @@ output_operand_error_report (char *str, bool non_fatal_only)
   gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
 
   /* Pick up one of errors of KIND to report.  */
-  largest_error_pos = -2; /* Index can be -1 which means unknown index.  */
   for (curr = head; curr != NULL; curr = curr->next)
     {
       /* If we don't want to print non-fatal errors then don't consider them
@@ -5654,13 +5820,23 @@ output_operand_error_report (char *str, bool non_fatal_only)
 	 mismatching operand index.  In the case of multiple errors with
 	 the equally highest operand index, pick up the first one or the
 	 first one with non-NULL error message.  */
-      if (curr->detail.index > largest_error_pos
-	  || (curr->detail.index == largest_error_pos && msg == NULL
-	      && curr->detail.error != NULL))
+      if (!record || curr->detail.index > record->detail.index)
+	record = curr;
+      else if (curr->detail.index == record->detail.index
+	       && !record->detail.error)
 	{
-	  largest_error_pos = curr->detail.index;
-	  record = curr;
-	  msg = record->detail.error;
+	  if (curr->detail.error)
+	    record = curr;
+	  else if (kind == AARCH64_OPDE_SYNTAX_ERROR)
+	    {
+	      record->detail.data[0].i |= curr->detail.data[0].i;
+	      record->detail.data[1].i |= curr->detail.data[1].i;
+	      record->detail.data[2].i |= curr->detail.data[2].i;
+	      DEBUG_TRACE ("\t--> %s [%x, %x, %x]",
+			   operand_mismatch_kind_names[kind],
+			   curr->detail.data[0].i, curr->detail.data[1].i,
+			   curr->detail.data[2].i);
+	    }
 	}
     }
 
@@ -5675,9 +5851,9 @@ output_operand_error_report (char *str, bool non_fatal_only)
   if (non_fatal_only && !record)
     return;
 
-  gas_assert (largest_error_pos != -2 && record != NULL);
+  gas_assert (record);
   DEBUG_TRACE ("Pick up error kind %s to report",
-	       operand_mismatch_kind_names[record->detail.kind]);
+	       operand_mismatch_kind_names[kind]);
 
   /* Output.  */
   output_operand_error_record (record, str);
@@ -6299,10 +6475,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	vector_reg:
 	  reg = aarch64_reg_parse (&str, reg_type, &vectype);
 	  if (!reg)
-	    {
-	      first_error (_(get_reg_expected_msg (reg_type)));
-	      goto failure;
-	    }
+	    goto failure;
 	  if (vectype.defined & NTA_HASINDEX)
 	    goto failure;
 
@@ -6325,10 +6498,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_VnD1:
 	  reg = aarch64_reg_parse (&str, REG_TYPE_VN, &vectype);
 	  if (!reg)
-	    {
-	      set_first_syntax_error (_(get_reg_expected_msg (REG_TYPE_VN)));
-	      goto failure;
-	    }
+	    goto failure;
 	  if (vectype.type != NT_d || vectype.index != 1)
 	    {
 	      set_fatal_syntax_error
@@ -6361,10 +6531,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	vector_reg_index:
 	  reg = aarch64_reg_parse (&str, reg_type, &vectype);
 	  if (!reg)
-	    {
-	      first_error (_(get_reg_expected_msg (reg_type)));
-	      goto failure;
-	    }
+	    goto failure;
 	  if (vectype.type == NT_invtype || !(vectype.defined & NTA_HASINDEX))
 	    goto failure;
 
@@ -6392,10 +6559,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	    {
 	      reg = aarch64_reg_parse (&str, reg_type, &vectype);
 	      if (!reg)
-		{
-		  first_error (_(get_reg_expected_msg (reg_type)));
-		  goto failure;
-		}
+		goto failure;
 	      info->reglist.first_regno = reg->number;
 	      info->reglist.num_regs = 1;
 	    }
diff --git a/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l b/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
index d31a0b0b27e..066123d4475 100644
--- a/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
+++ b/gas/testsuite/gas/aarch64/armv8_2-a-crypto-fp16-illegal.l
@@ -1,9 +1,9 @@
 [^:]+: Assembler messages:
-[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h X0,Q0,V1.2D'
+[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h X0,Q0,V1.2D'
 [^:]+:[0-9]+: Error: operand mismatch -- `sha512h Q0,Q1,V2.16B'
 [^:]+:[0-9]+: Info:    did you mean this\?
 [^:]+:[0-9]+: Info:    	sha512h q0, q1, v2.2d
-[^:]+:[0-9]+: Error: operand 1 must be a floating-point register -- `sha512h2 X0,Q0,V1.2D'
+[^:]+:[0-9]+: Error: expected a scalar SIMD or floating-point register at operand 1 -- `sha512h2 X0,Q0,V1.2D'
 [^:]+:[0-9]+: Error: operand mismatch -- `sha512h2 Q0,Q1,V2.16B'
 [^:]+:[0-9]+: Info:    did you mean this\?
 [^:]+:[0-9]+: Info:    	sha512h2 q0, q1, v2.2d
@@ -11,7 +11,7 @@
 [^:]+:[0-9]+: Info:    did you mean this\?
 [^:]+:[0-9]+: Info:    	sha512su0 v1.2d, v2.2d
 [^:]+:[0-9]+: Error: invalid use of vector register at operand 1 -- `sha512su0 V0,V2.2D'
-[^:]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sha512su1 X0,X1,X2'
+[^:]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 1 -- `sha512su1 X0,X1,X2'
 [^:]+:[0-9]+: Error: operand mismatch -- `sha512su1 V1.2D,V2.16B,V2.2D'
 [^:]+:[0-9]+: Info:    did you mean this\?
 [^:]+:[0-9]+: Info:    	sha512su1 v1.2d, v2.2d, v2.2d
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 99359891c5f..52365319283 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -51,7 +51,7 @@
 [^:]*:53: Error: invalid floating-point constant at operand 2 -- `fmov s3,1.01'
 [^:]*:54: Error: invalid floating-point constant at operand 2 -- `fmov d3,1.01'
 [^:]*:55: Error: immediate zero expected at operand 2 -- `fcmp d0,#1.0'
-[^:]*:56: Error: operand 2 must be a floating-point register -- `fcmp d0,x0'
+[^:]*:56: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fcmp d0,x0'
 [^:]*:57: Error: immediate zero expected at operand 3 -- `cmgt v0.4s,v2.4s,#1'
 [^:]*:58: Error: unexpected characters following instruction at operand 2 -- `fmov d3,1.00,lsl#3'
 [^:]*:59: Error: invalid offset register at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],sp'
@@ -59,7 +59,7 @@
 [^:]*:61: Error: invalid shift for the register offset addressing mode at operand 2 -- `ldr q0,\[x0,w0,lsr#4\]'
 [^:]*:62: Error: only 'LSL' shift is permitted at operand 3 -- `adds x1,sp,2134,uxtw#12'
 [^:]*:63: Error: shift amount out of range 0 to 63 at operand 2 -- `movz x0,2134,lsl#64'
-[^:]*:64: Error: operand 1 must be an integer register -- `adds sp,sp,2134,lsl#12'
+[^:]*:64: Error: expected an integer or zero register at operand 1 -- `adds sp,sp,2134,lsl#12'
 [^:]*:65: Error: the optional immediate offset can only be 0 at operand 2 -- `ldxrb w2,\[x0,#1\]'
 [^:]*:66: Error: invalid addressing mode at operand 2 -- `ldrb w0,x1,x2,sxtx'
 [^:]*:67: Error: invalid shift amount at operand 2 -- `prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
@@ -98,11 +98,11 @@
 [^:]*:100: Error: operand 3 must be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
 [^:]*:101: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
 [^:]*:102: Error: operand 2 must be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'
-[^:]*:106: Error: operand 1 must be an integer register -- `ret kk'
+[^:]*:106: Error: expected an integer or zero register at operand 1 -- `ret kk'
 [^:]*:107: Error: immediate operand required at operand 1 -- `clrex x0'
 [^:]*:108: Error: immediate operand required at operand 1 -- `clrex w0'
 [^:]*:109: Error: constant expression required at operand 1 -- `clrex kk'
-[^:]*:110: Error: operand 5 must be an integer register -- `sys #0,c0,c0,#0,kk'
+[^:]*:110: Error: expected an integer or zero register at operand 5 -- `sys #0,c0,c0,#0,kk'
 [^:]*:111: Error: unexpected comma before the omitted optional operand at operand 5 -- `sys #0,c0,c0,#0,'
 [^:]*:113: Error: selected processor does not support `casp w0,w1,w2,w3,\[x4\]'
 [^:]*:116: Warning: unpredictable load of register pair -- `ldp x0,x0,\[sp\]'
@@ -186,3 +186,21 @@
 [^:]*:317: Error: expected a base register at operand 2 -- `ldr x0,\[1\]'
 [^:]*:318: Error: expected a base register at operand 2 -- `ldr x0,\[\]'
 [^:]*:319: Error: expected a base register at operand 2 -- `ldr x0,\[,xzr\]'
+[^:]*:321: Error: expected a vector or predicate register at operand 1 -- `zip2 x1'
+[^:]*:322: Error: expected an integer register or SVE vector register at operand 1 -- `uxtw d2'
+[^:]*:323: Error: unexpected register type at operand 1 -- `usra x3'
+[^:]*:324: Error: unexpected register type at operand 1 -- `ushr z4'
+[^:]*:325: Error: expected an integer register or Advanced SIMD vector register at operand 1 -- `umull z5'
+[^:]*:326: Error: expected an integer or vector register at operand 1 -- `umin d6'
+[^:]*:327: Error: unexpected register type at operand 1 -- `stur v7'
+[^:]*:328: Error: expected an SVE vector or predicate register at operand 1 -- `sel v8'
+[^:]*:329: Error: expected an integer, vector or predicate register at operand 1 -- `orn d9'
+[^:]*:330: Error: unexpected register type at operand 1 -- `frecpx v10'
+[^:]*:331: Error: expected an integer or predicate register at operand 1 -- `bics z11'
+[^:]*:332: Error: unexpected register type at operand 1 -- `rev wsp'
+[^:]*:333: Error: unexpected register type at operand 1 -- `orr b12'
+[^:]*:334: Error: unexpected register type at operand 1 -- `neg p13'
+[^:]*:335: Error: unexpected register type at operand 1 -- `fcvtpu za14h'
+[^:]*:336: Error: unexpected register type at operand 1 -- `fcmlt z15'
+[^:]*:337: Error: unexpected register type at operand 1 -- `clastb sp'
+[^:]*:338: Error: unexpected register type at operand 1 -- `ldr sp'
diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index 014e0abe332..5f3c7791180 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -317,3 +317,22 @@
 	ldr	x0, [1]
 	ldr	x0, []
 	ldr	x0, [,xzr]
+
+	zip2	x1
+	uxtw	d2
+	usra	x3
+	ushr	z4
+	umull	z5
+	umin	d6
+	stur	v7
+	sel	v8
+	orn	d9
+	frecpx	v10
+	bics	z11
+	rev	wsp
+	orr	b12
+	neg	p13
+	fcvtpu	za14h
+	fcmlt	z15
+	clastb	sp
+	ldr	sp
diff --git a/gas/testsuite/gas/aarch64/illegal-bfloat16.l b/gas/testsuite/gas/aarch64/illegal-bfloat16.l
index c20f132de38..e513c3cc64c 100644
--- a/gas/testsuite/gas/aarch64/illegal-bfloat16.l
+++ b/gas/testsuite/gas/aarch64/illegal-bfloat16.l
@@ -25,28 +25,28 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalt z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalt z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalb z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bfmlalb z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -61,18 +61,18 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalb v0\.4s, v0\.8h, v0\.8h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalt v0\.4s, v0\.8h, v0\.8h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
-[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
 [^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -87,8 +87,8 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an Advanced SIMD vector register at operand 2 -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
 [^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1'
 [^ :]+:[0-9]+: Info:    did you mean this\?
diff --git a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
index 7a38ddca5a7..8431dc3b3a9 100644
--- a/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
+++ b/gas/testsuite/gas/aarch64/illegal-fjcvtzs.l
@@ -1,8 +1,8 @@
 [^:]+: Assembler messages:
-[^:]+:8: Error: operand 1 must be an integer register -- `fjcvtzs d0,d1'
-[^:]+:9: Error: operand 1 must be an integer register -- `fjcvtzs s0,d1'
+[^:]+:8: Error: expected an integer or zero register at operand 1 -- `fjcvtzs d0,d1'
+[^:]+:9: Error: expected an integer or zero register at operand 1 -- `fjcvtzs s0,d1'
 [^:]+:10: Error: operand mismatch -- `fjcvtzs x0,d1'
 [^:]+:11: Error: operand mismatch -- `fjcvtzs w0,s1'
 [^:]+:12: Error: operand mismatch -- `fjcvtzs w0,h1'
 [^:]+:13: Error: operand mismatch -- `fjcvtzs w0,q1'
-[^:]+:14: Error: operand 2 must be a floating-point register -- `fjcvtzs w0,x1'
+[^:]+:14: Error: expected a scalar SIMD or floating-point register at operand 2 -- `fjcvtzs w0,x1'
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 7e48f0a71e9..476c345d366 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -18,38 +18,38 @@
 [^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `ldgm x4,\[x5,#16\]!'
 [^:]*:[0-9]+: Error: the optional immediate offset can only be 0 at operand 2 -- `stgm x2,\[x3,#16\]'
 [^:]*:[0-9]+: Error: invalid addressing mode at operand 2 -- `stgm x4,\[x5,#16\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `irg xzr,x2,x3'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `irg x1,xzr,x3'
-[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `irg x1,x2,sp'
-[^:]*:[0-9]+: Error: operand 3 must be an integer register -- `gmi x1,x2,sp'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `gmi sp,x2,x3'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `gmi x1,xzr,x3'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `addg xzr,x2,#0,#0'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subg x1,xzr,#0,#0'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subp sp,x1,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subp x1,xzr,x2'
-[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subp x1,x2,xzr'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `subps sp,x1,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `subps x1,xzr,x2'
-[^:]*:[0-9]+: Error: operand 3 must be an integer or stack pointer register -- `subps x1,x2,xzr'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `cmpp xzr,x2'
-[^:]*:[0-9]+: Error: operand 2 must be an integer or stack pointer register -- `cmpp x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `irg xzr,x2,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `irg x1,xzr,x3'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `irg x1,x2,sp'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 3 -- `gmi x1,x2,sp'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gmi sp,x2,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subps x1,xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subps x1,x2,xzr'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `cmpp xzr,x2'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `cmpp x2,xzr'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stg x2,\[xzr,#0\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `st2g x2,\[xzr,#0\]!'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzg x2,\[xzr\],#0'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stz2g x2,\[xzr,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stg xzr,\[x2,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `st2g xzr,\[x2,#0\]!'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stzg xzr,\[x2\],#0'
-[^:]*:[0-9]+: Error: operand 1 must be an integer or stack pointer register -- `stz2g xzr,\[x2,#0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgp sp,x2,\[x3\]'
-[^:]*:[0-9]+: Error: operand 2 must be an integer register -- `stgp x1,sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stg xzr,\[x2,#0\]'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `st2g xzr,\[x2,#0\]!'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stzg xzr,\[x2\],#0'
+[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `stz2g xzr,\[x2,#0\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgp sp,x2,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 2 -- `stgp x1,sp,\[x3\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 3 -- `stgp x0,x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldg sp,\[x0,#16\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldg sp,\[x0,#16\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldg x0,\[xzr,#16\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stzgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stzgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stzgm sp,\[x3\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `ldgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `ldgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `ldgm sp,\[x3\]'
 [^:]*:[0-9]+: Error: invalid base register at operand 2 -- `stgm x0,\[xzr\]'
-[^:]*:[0-9]+: Error: operand 1 must be an integer register -- `stgm sp,\[x3\]'
+[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `stgm sp,\[x3\]'
diff --git a/gas/testsuite/gas/aarch64/illegal-sve2.l b/gas/testsuite/gas/aarch64/illegal-sve2.l
index 13df21b4a4e..d41f6f23ba5 100644
--- a/gas/testsuite/gas/aarch64/illegal-sve2.l
+++ b/gas/testsuite/gas/aarch64/illegal-sve2.l
@@ -8,35 +8,35 @@
 [^ :]+:[0-9]+: Info:    	adclb z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	adclb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclb z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclb z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclb z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `adclb z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `adclb z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `adclb z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `adclt z0\.d,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	adclt z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	adclt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `adclt z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `adclt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `adclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `adclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `adclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `adclt z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `addhnb z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	addhnb z0\.b, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	addhnb z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	addhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `addhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `addhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `addhnb z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `addhnt z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	addhnt z0\.b, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	addhnt z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	addhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `addhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `addhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `addhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `addhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `addhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `addhnt z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `addp z0\.b,p0/m,z0\.b,z1\.b'
 [^ :]+:[0-9]+: Warning: predicate register differs from that in preceding `movprfx' at operand 2 -- `addp z0\.d,p1/m,z0\.d,z1\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `addp z0\.b,p0/z,z0\.b,z0\.b'
@@ -47,35 +47,35 @@
 [^ :]+:[0-9]+: Info:    	addp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	addp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `addp z0\.h,p0/m,z1\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `addp z32\.s,p0/m,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `addp z0\.s,p0/m,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `addp z32\.s,p0/m,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `addp z0\.s,p0/m,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `addp z0\.s,p8/m,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesd z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesd z0\.b,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesd z0\.b,z0\.s,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aesd z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesd z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aesd z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesd z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aesd z0\.b,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aese z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aese z0\.b,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aese z0\.b,z0\.s,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aese z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aese z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `aese z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aese z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `aese z0\.b,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesimc z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesimc z0\.b,z1\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesimc z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aesimc z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesimc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesimc z32\.b,z0\.b'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `aesmc z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `aesmc z0\.b,z1\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `aesmc z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	aesmc z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `aesmc z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `aesmc z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bcax z0\.d,z1\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.d,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -83,9 +83,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bcax z0\.d,z0\.h,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bcax z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bcax z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bcax z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bcax z0\.d,z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl z0\.d,z1\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.d,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -93,9 +93,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl z0\.d,z0\.h,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bsl z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `bsl z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl z0\.d,z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl1n z0\.d,z1\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.d,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -103,9 +103,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl1n z0\.d,z0\.h,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bsl1n z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bsl1n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl1n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl1n z0\.d,z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `bsl2n z0\.d,z1\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.d,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -113,9 +113,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `bsl2n z0\.d,z0\.h,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bsl2n z0\.d, z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bsl2n z32\.d,z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bsl2n z0\.d,z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `bsl2n z0\.d,z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bdep z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bdep z0\.b, z0\.b, z0\.b
@@ -123,9 +123,9 @@
 [^ :]+:[0-9]+: Info:    	bdep z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	bdep z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	bdep z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bdep z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bdep z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bdep z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bdep z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bdep z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bdep z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bext z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bext z0\.b, z0\.b, z0\.b
@@ -133,9 +133,9 @@
 [^ :]+:[0-9]+: Info:    	bext z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	bext z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	bext z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bext z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bext z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bext z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bext z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bext z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bext z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `bgrp z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	bgrp z0\.b, z0\.b, z0\.b
@@ -143,9 +143,9 @@
 [^ :]+:[0-9]+: Info:    	bgrp z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	bgrp z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	bgrp z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bgrp z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bgrp z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `bgrp z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `bgrp z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `bgrp z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `bgrp z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `cadd z18\.b,z17\.b,z21\.b,#90'
 [^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `cadd z0\.b,z0\.b,z0\.b,#91'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cadd z0\.b,z0\.h,z0\.h,#90'
@@ -160,19 +160,19 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.d,z0\.b\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.s,z0\.b,z0\.b\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.s,z32\.b,z0\.b\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cdot z0\.s,z0\.b,z8\.b\[0\],#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cdot z0\.d,z0\.h,z0\.h\[0\],#1'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.d,z0\.d,z0\.h\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.d,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.d,z32\.h,z0\.h\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cdot z0\.d,z0\.h,z16\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cdot z32\.s,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cdot z0\.s,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cdot z0\.s,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cdot z32\.s,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cdot z0\.s,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `cdot z0\.s,z0\.b,z32\.b,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cdot z0\.s,z0\.b,z0\.s,#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cdot z0\.s, z0\.b, z0\.b, #0
@@ -184,25 +184,25 @@
 [^ :]+:[0-9]+: Info:    	cdot z0\.d, z0\.h, z0\.h, #0
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	cdot z0\.s, z0\.b, z0\.b, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.h,z32\.h,z0\.h\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `cmla z0\.h,z0\.h,z8\.h\[0\],#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.h,z0\.h,z0\.d\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cmla z0\.h, z0\.h, z0\.h\[0\], #0
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `cmla z0\.h,z0\.h,z0\.h\[4\],#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.h,z0\.h,z0\.h\[0\],#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.s,z32\.s,z0\.s\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `cmla z0\.s,z0\.s,z16\.s\[0\],#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.s,z0\.s,z0\.d\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cmla z0\.h, z0\.h, z0\.h\[0\], #0
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `cmla z0\.s,z0\.s,z0\.s\[2\],#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `cmla z0\.s,z0\.s,z0\.s\[0\],#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `cmla z32\.b,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `cmla z0\.b,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `cmla z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `cmla z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `cmla z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `cmla z0\.b,z0\.b,z32\.b,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `cmla z0\.b,z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	cmla z0\.b, z0\.b, z0\.b, #0
@@ -225,9 +225,9 @@
 [^ :]+:[0-9]+: Info:    	eorbt z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	eorbt z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	eorbt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eorbt z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eorbt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eorbt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `eorbt z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `eorbt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `eorbt z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `eortb z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	eortb z0\.b, z0\.b, z0\.b
@@ -235,9 +235,9 @@
 [^ :]+:[0-9]+: Info:    	eortb z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	eortb z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	eortb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `eortb z32\.h,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `eortb z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `eortb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `eortb z32\.h,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `eortb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `eortb z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: syntax error in register list at operand 2 -- `ext z0\.b,{,},#0'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z2\.b},#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ext z0\.h,{z0\.b,z1\.b},#0'
@@ -250,16 +250,16 @@
 [^ :]+:[0-9]+: Info:    	ext z0\.b, {z0\.b, z1\.b}, #0
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z1\.b,z2\.b},#0'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b},#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ext z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ext z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z31\.b,z1\.b},#0'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `ext z0\.b,{z0\.b,z31\.b},#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 255 at operand 3 -- `ext z0\.b,{z0\.b,z1\.b},#256'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ext z32\.b,{z0\.b,z1\.b},#0'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `ext z32\.b,{z0\.b,z1\.b},#0'
 [^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `ext z0\.b,{z31\.b,z32\.b},#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ext z0\.b,{z32\.b,z33\.b},#0'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ext z0\.b,{z32\.b,z33\.b},#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `faddp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `faddp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `faddp z0\.h,p0/m,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `faddp z0\.h,p0/m,z1\.h,z0\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `faddp z0\.h,p0/z,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -274,18 +274,18 @@
 [^ :]+:[0-9]+: Info:    	faddp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	faddp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtlt z0\.s,p0/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.s,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.s,p0/m,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.s,p8/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.s,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.s,p0/m,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.s,p0/z,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtlt z32\.d,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtlt z32\.d,p0/m,z0\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtlt z0\.d,p8/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtlt z0\.d,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtlt z0\.d,p0/m,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtlt z0\.d,p0/m,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
@@ -293,27 +293,27 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtlt z0\.d, p0/m, z0\.s
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtnt z0\.h,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.h,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.h,p0/m,z0\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.h,p8/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.h,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.h,p0/m,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/m,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.h,p0/z,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtnt z32\.s,p0/m,z0\.d'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtnt z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtnt z0\.s,p0/m,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtnt z0\.s,p0/z,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtnt z0\.s, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtx z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtx z32\.s,p0/m,z0\.d'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtx z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtx z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtx z0\.s,p0/m,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtx z0\.s,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtx z0\.s, p0/m, z0\.d
@@ -322,9 +322,9 @@
 [^ :]+:[0-9]+: Info:    	fcvtx z0\.s, p0/m, z0\.d
 [^ :]+:[0-9]+: Warning: register size not compatible with previous `movprfx' at operand 1 -- `fcvtx z0\.s,p0/m,z2\.d'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `fcvtxnt z0\.s,p0/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fcvtxnt z32\.s,p0/m,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fcvtxnt z32\.s,p0/m,z0\.d'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fcvtxnt z0\.s,p8/m,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fcvtxnt z0\.s,p0/m,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fcvtxnt z0\.s,p0/m,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fcvtxnt z0\.s,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fcvtxnt z0\.s, p0/m, z0\.d
@@ -349,9 +349,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	flogb z0\.s, p0/m, z0\.s
 [^ :]+:[0-9]+: Info:    	flogb z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `flogb z32\.h,p0/m,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `flogb z32\.h,p0/m,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `flogb z0\.h,p8/m,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `flogb z0\.h,p0/m,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `flogb z0\.h,p0/m,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxnmp z0\.b,p0/m,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmaxnmp z0\.h, p0/m, z0\.h, z0\.h
@@ -365,9 +365,9 @@
 [^ :]+:[0-9]+: Info:    	fmaxnmp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	fmaxnmp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxnmp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmaxnmp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxnmp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fmaxnmp z0\.h,p0/m,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmaxp z0\.b,p0/m,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmaxp z0\.h, p0/m, z0\.h, z0\.h
@@ -381,9 +381,9 @@
 [^ :]+:[0-9]+: Info:    	fmaxp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	fmaxp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fmaxp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fmaxp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fmaxp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fmaxp z0\.h,p0/m,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fminnmp z0\.b,p0/m,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fminnmp z0\.h, p0/m, z0\.h, z0\.h
@@ -397,9 +397,9 @@
 [^ :]+:[0-9]+: Info:    	fminnmp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	fminnmp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminnmp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fminnmp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminnmp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fminnmp z0\.h,p0/m,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fminp z0\.b,p0/m,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fminp z0\.h, p0/m, z0\.h, z0\.h
@@ -413,65 +413,65 @@
 [^ :]+:[0-9]+: Info:    	fminp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	fminp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `fminp z1\.h,p0/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `fminp z32\.h,p0/m,z32\.h,z0\.h'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `fminp z0\.h,p8/m,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `fminp z0\.h,p0/m,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalb z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlalb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalb z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalb z0\.s,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlalt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlalt z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlalt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlalt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlalt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlalt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlalt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlalt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlalt z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlalt z0\.s,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslb z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslb z32\.s,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlslb z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslb z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslb z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslb z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslb z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslb z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlslb z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslb z0\.s,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlslb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `fmlslt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `fmlslt z0\.s,z0\.h,z8\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslt z32\.s,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlslt z0\.s, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `fmlslt z32\.s,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `fmlslt z0\.s,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `fmlslt z0\.s,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `fmlslt z32\.s,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `fmlslt z0\.s,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `fmlslt z0\.s,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `fmlslt z0\.s,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	fmlslt z0\.s, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `histcnt z32\.s,p0/z,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `histcnt z0\.s,p8/z,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `histcnt z0\.s,p0/z,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `histcnt z0\.s,p0/z,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `histcnt z0\.s,p0/m,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	histcnt z0\.s, p0/z, z0\.s, z0\.s
@@ -482,9 +482,9 @@
 [^ :]+:[0-9]+: Info:    	histcnt z0\.s, p0/z, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	histcnt z0\.d, p0/z, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `histseg z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `histseg z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `histseg z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `histseg z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `histseg z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `histseg z0\.b,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `histseg z0\.b,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	histseg z0\.b, z0\.b, z0\.b
@@ -492,7 +492,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -509,7 +509,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1b {z0\.s},p0/m,\[z0\.s\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1b {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1b {z32\.s},p0/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1b {z0\.s},p8/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1b {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -519,7 +519,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1d {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1d {z0\.d}, p0/z, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1d {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1d {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1d {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -539,7 +539,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1h {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -550,7 +550,7 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1h {z0\.s}, p0/z, \[z0\.s, xzr\]
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1h {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1h {z32\.s},p0/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1h {z0\.s},p8/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1h {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -562,7 +562,7 @@
 [^ :]+:[0-9]+: Info:    	ldnt1sb {z0\.d}, p0/z, \[z0\.d, xzr\]
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ldnt1sb {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sb {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sb {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sb {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -575,7 +575,7 @@
 [^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -588,7 +588,7 @@
 [^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.d}, p0/z, \[z0\.d, xzr\]
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ldnt1sh {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1sh {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1sh {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1sh {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -599,7 +599,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `ldnt1w {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.d},p0/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.d},p8/z,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.d},p0/z,\[z0\.d,sp\]'
@@ -610,7 +610,7 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	ldnt1w {z0\.s}, p0/z, \[z0\.s, xzr\]
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `ldnt1w {z0\.s,z1\.d},p0/z,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ldnt1w {z32\.s},p0/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ldnt1w {z0\.s},p8/z,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `ldnt1w {z0\.s},p0/z,\[z0\.s,sp\]'
@@ -621,10 +621,10 @@
 [^ :]+:[0-9]+: Info:    	match p0\.b, p0/z, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	match p0\.h, p0/z, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `match p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `match p16\.b,p0/z,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `match p0\.b,p8/z,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `match p0\.b,p0/z,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `match p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `match p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `match p0\.b,p0/z,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mla z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -632,8 +632,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mla z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.s,z0\.s\[0\]'
@@ -642,8 +642,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mla z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mla z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.h,z0\.d,z0\.d\[0\]'
@@ -652,8 +652,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mla z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mla z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mla z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mla z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mla z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mla z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mla z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mls z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.h,z0\.h\[0\]'
@@ -662,8 +662,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mls z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.s,z0\.s\[0\]'
@@ -672,8 +672,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mls z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mls z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.h,z0\.d,z0\.d\[0\]'
@@ -682,8 +682,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mls z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mls z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mls z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `mls z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `mls z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mls z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mls z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `mul z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.h,z0\.h\[0\]'
@@ -692,8 +692,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `mul z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.s,z0\.s\[0\]'
@@ -702,8 +702,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `mul z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `mul z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.d,z0\.d\[0\]'
@@ -712,8 +712,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `mul z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `mul z0\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -722,8 +722,8 @@
 [^ :]+:[0-9]+: Info:    	mul z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	mul z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	mul z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `mul z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `mul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an integer or vector register at operand 1 -- `mul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `mul z0\.b,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `nmatch p0\.h,p0/z,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	nmatch p0\.b, p0/z, z0\.b, z0\.b
@@ -734,10 +734,10 @@
 [^ :]+:[0-9]+: Info:    	nmatch p0\.b, p0/z, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	nmatch p0\.h, p0/z, z0\.h, z0\.h
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `nmatch p16\.b,p0/z,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `nmatch p0\.b,p8/z,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `nmatch p0\.b,p0/z,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `nmatch p0\.b,p0/z,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `nbsl z0\.d,z1\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `nbsl z0\.d,z0\.d,z0\.h,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -748,30 +748,30 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `pmul z0\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	pmul z0\.b, z0\.b, z0\.b
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmul z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmul z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmul z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.q,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.q,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `pmul z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmul z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmul z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullb z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullb z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullb z0\.q,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	pmullb z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullb z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	pmullb z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.q,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.q,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.q,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullt z32\.q,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullt z0\.q,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.q,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.d,z0\.d,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	pmullt z0\.q, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `pmullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `pmullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `pmullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `pmullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `pmullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `pmullt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `pmullt z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	pmullt z0\.q, z0\.d, z0\.d
@@ -781,26 +781,26 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	raddhnb z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	raddhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `raddhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `raddhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `raddhnb z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `raddhnt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	raddhnt z0\.b, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	raddhnt z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	raddhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `raddhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `raddhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `raddhnt z0\.b,z0\.h,z32\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `rax1 z32\.d,z0\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rax1 z0\.d,z32\.d,z0\.d'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rax1 z0\.d,z0\.d,z32\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `raddhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `raddhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `raddhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `rax1 z32\.d,z0\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rax1 z0\.d,z32\.d,z0\.d'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rax1 z0\.d,z0\.d,z32\.d'
 [^ :]+:[0-9]+: Error: operand mismatch -- `rax1 z0\.d,z0\.d,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	rax1 z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rshrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `rshrnb z0\.h,z0\.h,#8'
@@ -814,8 +814,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `rshrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `rshrnt z0\.b,z1\.h,#8'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rshrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `rshrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `rshrnt z0\.h,z0\.h,#8'
@@ -834,18 +834,18 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	rsubhnb z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	rsubhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rsubhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rsubhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rsubhnb z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `rsubhnt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	rsubhnt z0\.b, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	rsubhnt z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	rsubhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `rsubhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `rsubhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `rsubhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `rsubhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `rsubhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `rsubhnt z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saba z0\.h,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saba z0\.b, z0\.b, z0\.b
@@ -853,45 +853,45 @@
 [^ :]+:[0-9]+: Info:    	saba z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	saba z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	saba z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saba z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saba z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saba z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `saba z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saba z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saba z0\.b,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sabalb z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sabalb z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sabalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sabalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabalb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sabalt z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sabalt z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sabalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sabalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabalt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sabdlb z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sabdlb z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sabdlb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sabdlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabdlb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sabdlt z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sabdlt z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sabdlt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sabdlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sabdlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sabdlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sabdlt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sadalp z0\.b,p0/m,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sadalp z0\.h, p0/m, z0\.b
@@ -905,74 +905,74 @@
 [^ :]+:[0-9]+: Info:    	sadalp z0\.s, p0/m, z0\.h
 [^ :]+:[0-9]+: Info:    	sadalp z0\.d, p0/m, z0\.s
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sadalp z0\.h,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sadalp z32\.h,p0/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sadalp z0\.h,p0/m,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlb z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saddlb z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	saddlb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	saddlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlbt z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saddlbt z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	saddlbt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	saddlbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlbt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saddlt z0\.b,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saddlt z0\.h, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	saddlt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	saddlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddlt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saddwb z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saddwb z0\.h, z0\.h, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	saddwb z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	saddwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddwb z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `saddwt z0\.b,z0\.h,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	saddwt z0\.h, z0\.h, z0\.b
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	saddwt z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	saddwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `saddwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `saddwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `saddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `saddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `saddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `saddwt z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sbclb z0\.d,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sbclb z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sbclb z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclb z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclb z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclb z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sbclb z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sbclb z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sbclb z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sbclt z0\.d,z0\.s,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sbclt z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sbclt z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sbclt z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sbclt z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sbclt z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sbclt z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sbclt z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sbclt z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shadd z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `shadd z32\.b,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shadd z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `shadd z0\.h,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	shadd z0\.b, p0/m, z0\.b, z0\.b
@@ -987,8 +987,8 @@
 [^ :]+:[0-9]+: Info:    	shadd z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	shadd z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	shadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `shrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `shrnb z0\.h,z0\.h,#8'
@@ -1002,8 +1002,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `shrnt z0\.b,z1\.h,#8'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `shrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `shrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `shrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `shrnt z0\.h,z0\.h,#8'
@@ -1017,10 +1017,10 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `shrnt z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsub z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `shsub z32\.b,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsub z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shsub z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `shsub z0\.h,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	shsub z0\.b, p0/m, z0\.b, z0\.b
@@ -1036,10 +1036,10 @@
 [^ :]+:[0-9]+: Info:    	shsub z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	shsub z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `shsubr z0\.b,p0/m,z1\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `shsubr z32\.b,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `shsubr z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `shsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `shsubr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `shsubr z0\.h,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	shsubr z0\.b, p0/m, z0\.b, z0\.b
@@ -1061,23 +1061,23 @@
 [^ :]+:[0-9]+: Info:    	sli z0\.h, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sli z0\.s, z0\.s, #0
 [^ :]+:[0-9]+: Info:    	sli z0\.d, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sli z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sli z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sli z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sli z0\.b,z32\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sli z0\.b,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sli z0\.h,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sli z0\.s,z0\.s,#32'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 3 -- `sli z0\.d,z0\.d,#64'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sm4e z0\.s,z0\.s,z1\.s'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sm4e z1\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4e z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4e z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4e z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sm4e z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sm4e z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sm4e z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4e z0\.s,z0\.s,z0\.d'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sm4e z0\.s, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sm4ekey z32\.s,z0\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sm4ekey z0\.s,z32\.s,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sm4ekey z0\.s,z0\.s,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sm4ekey z32\.s,z0\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sm4ekey z0\.s,z32\.s,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sm4ekey z0\.s,z0\.s,z32\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sm4ekey z0\.s,z0\.s,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sm4ekey z0\.s, z0\.s, z0\.s
@@ -1096,9 +1096,9 @@
 [^ :]+:[0-9]+: Info:    	smaxp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	smaxp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `smaxp z1\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `smaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `smaxp z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `smaxp z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sminp z0\.h,p0/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1115,27 +1115,27 @@
 [^ :]+:[0-9]+: Info:    	sminp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sminp z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sminp z1\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `sminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sminp z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sminp z0\.b,p8/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlalb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1143,23 +1143,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	smlalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	smlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlalt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlalt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlalt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlalt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlalt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlalt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlalt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1167,23 +1167,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	smlalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	smlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlslb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1191,23 +1191,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	smlslb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	smlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smlslt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smlslt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smlslt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smlslt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smlslt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smlslt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smlslt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1222,26 +1222,26 @@
 [^ :]+:[0-9]+: Info:    	smulh z0\.h, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	smulh z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	smulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smulh z32\.b,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `smulh z0\.b,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `smulh z0\.b,z0\.b,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `smulh z32\.b,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `smulh z0\.b,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smulh z0\.b,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smullb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1249,23 +1249,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	smullb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	smullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `smullt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `smullt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `smullt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `smullt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	smullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `smullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `smullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `smullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `smullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `smullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `smullt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `smullt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `smullt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1283,14 +1283,14 @@
 [^ :]+:[0-9]+: Info:    	splice z0\.d, p0, {z0\.d, z1\.d}
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.h,z1\.b}'
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 3 -- `splice z0\.b,p0,{z0\.b,z1\.h}'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `splice z32\.b,p0,{z0\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `splice z32\.b,p0,{z0\.b,z1\.b}'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `splice z0\.b,p8,{z0\.b,z1\.b}'
 [^ :]+:[0-9]+: Error: invalid register list at operand 3 -- `splice z0\.b,p0,{z31\.b,z1\.b}'
 [^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z31\.b,z32\.b}'
-[^ :]+:[0-9]+: Error: operand 3 must be a list of SVE vector registers -- `splice z0\.b,p0,{z32\.b,z1\.b}'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqabs z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `splice z0\.b,p0,{z32\.b,z1\.b}'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqabs z32\.b,p0/m,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqabs z0\.b,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqabs z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqabs z0\.b,p0/m,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqabs z0\.b,p0/m,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqabs z0\.b, p0/m, z0\.b
@@ -1305,9 +1305,9 @@
 [^ :]+:[0-9]+: Info:    	sqabs z0\.h, p0/m, z0\.h
 [^ :]+:[0-9]+: Info:    	sqabs z0\.s, p0/m, z0\.s
 [^ :]+:[0-9]+: Info:    	sqabs z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -1326,9 +1326,9 @@
 [^ :]+:[0-9]+: Info:    	sqadd z0\.d, p0/m, z0\.d, z0\.d
 [^ :]+:[0-9]+: Error: rotate expected to be 90 or 270 at operand 4 -- `sqcadd z0\.b,z0\.b,z0\.b,#180'
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `sqcadd z0\.b,z1\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqcadd z32\.b,z0\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqcadd z0\.b,z32\.b,z0\.b,#90'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqcadd z0\.b,z0\.b,z32\.b,#90'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqcadd z0\.b,z0\.b,z0\.h,#90'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqcadd z0\.b, z0\.b, z0\.b, #90
@@ -1336,23 +1336,23 @@
 [^ :]+:[0-9]+: Info:    	sqcadd z0\.h, z0\.h, z0\.h, #90
 [^ :]+:[0-9]+: Info:    	sqcadd z0\.s, z0\.s, z0\.s, #90
 [^ :]+:[0-9]+: Info:    	sqcadd z0\.d, z0\.d, z0\.d, #90
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1360,9 +1360,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalbt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalbt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalbt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1370,23 +1370,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlalbt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlalbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlalt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlalt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlalt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlalt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlalt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlalt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1394,23 +1394,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1418,9 +1418,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlslb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslbt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslbt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslbt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1428,23 +1428,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlslbt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlslbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmlslt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmlslt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmlslt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmlslt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmlslt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmlslt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1452,8 +1452,8 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmlslt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmlslt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmulh z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1462,8 +1462,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmulh z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmulh z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1472,8 +1472,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmulh z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqdmulh z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1482,9 +1482,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqdmulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmulh z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmulh z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmulh z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1493,23 +1493,23 @@
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqdmulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmullb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1517,23 +1517,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmullb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqdmullt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqdmullt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqdmullt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqdmullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqdmullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqdmullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqdmullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqdmullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqdmullt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqdmullt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqdmullt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1541,9 +1541,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqdmullt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqdmullt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqneg z32\.b,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqneg z32\.b,p0/m,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqneg z0\.b,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqneg z0\.b,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqneg z0\.b,p0/m,z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqneg z0\.b,p0/m,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqneg z0\.b, p0/m, z0\.b
@@ -1558,8 +1558,8 @@
 [^ :]+:[0-9]+: Info:    	sqneg z0\.h, p0/m, z0\.h
 [^ :]+:[0-9]+: Info:    	sqneg z0\.s, p0/m, z0\.s
 [^ :]+:[0-9]+: Info:    	sqneg z0\.d, p0/m, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.h,z0\.h,z0\.h\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.h,z32\.h,z0\.h\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z8\.h\[0\],#0'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[4\],#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.h,z0\.h,z0\.h\[0\],#1'
@@ -1570,8 +1570,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.h,z0\.s,z0\.h\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.s,z0\.s,z0\.s\[0\],#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.s,z32\.s,z0\.s\[0\],#0'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z16\.s\[0\],#0'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[2\],#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.s,z0\.s,z0\.s\[0\],#1'
@@ -1582,9 +1582,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.s,z0\.h,z0\.s\[0\],#0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s\[0\], #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrdcmlah z32\.b,z0\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdcmlah z0\.b,z32\.b,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdcmlah z0\.b,z0\.b,z32\.b,#0'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#1'
 [^ :]+:[0-9]+: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `sqrdcmlah z0\.b,z0\.b,z0\.b,#360'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdcmlah z0\.b,z0\.b,z0\.h,#0'
@@ -1594,8 +1594,8 @@
 [^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.h, z0\.h, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.s, z0\.s, z0\.s, #0
 [^ :]+:[0-9]+: Info:    	sqrdcmlah z0\.d, z0\.d, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlah z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.h\[0\]'
@@ -1604,8 +1604,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlah z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlah z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.h,z0\.s\[0\]'
@@ -1614,8 +1614,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlah z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlah z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.h,z0\.d\[0\]'
@@ -1624,9 +1624,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlah z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlah z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlah z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlah z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlah z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlah z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlah z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlah z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1635,8 +1635,8 @@
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqrdmlah z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmlsh z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1645,8 +1645,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmlsh z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1655,8 +1655,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmlsh z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1665,9 +1665,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmlsh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmlsh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmlsh z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmlsh z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmlsh z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1676,8 +1676,8 @@
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqrdmlsh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.h,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.h,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.h,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `sqrdmulh z0\.h,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.h\[0\]'
@@ -1686,8 +1686,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.h,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.s,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.s,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `sqrdmulh z0\.s,z0\.s,z8\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `sqrdmulh z0\.s,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.h,z0\.s\[0\]'
@@ -1696,8 +1696,8 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.s,z0\.s,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.d,z0\.d,z0\.d\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.d,z32\.d,z0\.d\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `sqrdmulh z0\.d,z0\.d,z16\.d\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 3 -- `sqrdmulh z0\.d,z0\.d,z0\.d\[2\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.h,z0\.d\[0\]'
@@ -1706,9 +1706,9 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.d,z0\.d,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.h, z0\.h, z0\.h\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqrdmulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrdmulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `sqrdmulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrdmulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrdmulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrdmulh z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `sqrdmulh z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrdmulh z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -1717,9 +1717,9 @@
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqrdmulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqrshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshl z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -1736,9 +1736,9 @@
 [^ :]+:[0-9]+: Info:    	sqrshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqrshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqrshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqrshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqrshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqrshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1755,8 +1755,8 @@
 [^ :]+:[0-9]+: Info:    	sqrshlr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqrshlr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqrshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnb z0\.h,z0\.h,#8'
@@ -1770,8 +1770,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrnt z0\.h,z0\.h,#8'
@@ -1784,8 +1784,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrnt z0\.h,z0\.s,#17'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrunb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunb z0\.h,z0\.h,#8'
@@ -1799,8 +1799,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqrshrunb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrunt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqrshrunt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqrshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqrshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqrshrunt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrunt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrunt z0\.h,z0\.h,#8'
@@ -1820,15 +1820,15 @@
 [^ :]+:[0-9]+: Info:    	sqshl z0\.h, p0/m, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sqshl z0\.s, p0/m, z0\.s, #0
 [^ :]+:[0-9]+: Info:    	sqshl z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshl z32\.b,p0/m,z32\.b,#0'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,#0'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshl z0\.h,p0/m,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshl z0\.s,p0/m,z0\.s,#32'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshl z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqshl z0\.b,p0/m,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `sqshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshl z0\.b,p8/m,z0\.b,z0\.b'
@@ -1846,9 +1846,9 @@
 [^ :]+:[0-9]+: Info:    	sqshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1872,15 +1872,15 @@
 [^ :]+:[0-9]+: Info:    	sqshlu z0\.h, p0/m, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sqshlu z0\.s, p0/m, z0\.s, #0
 [^ :]+:[0-9]+: Info:    	sqshlu z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqshlu z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqshlu z32\.b,p0/m,z32\.b,#0'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqshlu z0\.b,p0/m,z1\.b,#0'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqshlu z0\.b,p8/m,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `sqshlu z0\.b,p0/m,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `sqshlu z0\.h,p0/m,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `sqshlu z0\.s,p0/m,z0\.s,#32'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `sqshlu z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnb z0\.h,z0\.h,#8'
@@ -1894,8 +1894,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrnt z0\.h,z0\.h,#8'
@@ -1908,8 +1908,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrnt z0\.h,z0\.s,#17'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrunb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrunb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunb z0\.h,z0\.h,#8'
@@ -1923,8 +1923,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqshrunt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqshrunt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqshrunt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqshrunt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqshrunt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sqshrunt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqshrunt z0\.h,z0\.h,#8'
@@ -1937,9 +1937,9 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqshrunt z0\.h,z0\.s,#17'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sqshrunt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqsub z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsub z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsub z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -1956,9 +1956,9 @@
 [^ :]+:[0-9]+: Info:    	sqsub z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqsub z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `sqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `sqsubr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `sqsubr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `sqsubr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -1975,41 +1975,41 @@
 [^ :]+:[0-9]+: Info:    	sqsubr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	sqsubr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	sqsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtnb z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnb z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqxtnb z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqxtnb z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	sqxtnb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtnt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtnt z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtnt z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqxtnt z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqxtnt z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	sqxtnt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtunb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtunb z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunb z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqxtunb z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqxtunb z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	sqxtunb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sqxtunt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sqxtunt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sqxtunt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sqxtunt z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `sqxtunt z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	sqxtunt z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sqxtunt z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	sqxtunt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `srhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srhadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srhadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srhadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `srhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2033,8 +2033,8 @@
 [^ :]+:[0-9]+: Info:    	sri z0\.h, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	sri z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	sri z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `sri z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sri z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sri z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sri z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `sri z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sri z0\.h,z0\.h,#0'
@@ -2042,9 +2042,9 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `sri z0\.s,z0\.s,#33'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `sri z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshl z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `srshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2061,9 +2061,9 @@
 [^ :]+:[0-9]+: Info:    	srshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	srshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	srshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `srshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `srshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `srshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `srshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2087,7 +2087,7 @@
 [^ :]+:[0-9]+: Info:    	srshr z0\.h, p0/m, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	srshr z0\.s, p0/m, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	srshr z0\.d, p0/m, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srshr z32\.b,p0/m,z32\.b,#1'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `srshr z0\.b,p0/m,z1\.b,#1'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `srshr z0\.b,p8/m,z0\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `srshr z0\.b,p0/m,z0\.b,#0'
@@ -2105,8 +2105,8 @@
 [^ :]+:[0-9]+: Info:    	srsra z0\.h, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	srsra z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	srsra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `srsra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `srsra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `srsra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `srsra z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `srsra z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `srsra z0\.h,z0\.h,#0'
@@ -2120,8 +2120,8 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sshllb z0\.s, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sshllb z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllb z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sshllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sshllb z0\.h,z32\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllb z0\.h,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllb z0\.s,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllb z0\.d,z0\.s,#32'
@@ -2131,8 +2131,8 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	sshllt z0\.s, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	sshllt z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `sshllt z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `sshllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `sshllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sshllt z0\.h,z32\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `sshllt z0\.h,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `sshllt z0\.s,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `sshllt z0\.d,z0\.s,#32'
@@ -2143,8 +2143,8 @@
 [^ :]+:[0-9]+: Info:    	ssra z0\.h, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	ssra z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	ssra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ssra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ssra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssra z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ssra z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ssra z0\.h,z0\.h,#0'
@@ -2152,9 +2152,9 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `ssra z0\.s,z0\.s,#33'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `ssra z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2162,9 +2162,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ssublb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	ssublb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublbt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublbt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublbt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublbt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublbt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublbt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublbt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublbt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2172,9 +2172,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ssublbt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	ssublbt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssublt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssublt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssublt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssublt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssublt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2182,9 +2182,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ssublt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	ssublt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubltb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubltb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubltb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubltb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubltb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubltb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubltb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubltb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2192,9 +2192,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ssubltb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	ssubltb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubwb z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwb z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubwb z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2202,9 +2202,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ssubwb z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	ssubwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ssubwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ssubwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ssubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ssubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ssubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ssubwt z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `ssubwt z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ssubwt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2216,7 +2216,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1b {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.d},p0,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.d},p8,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.d},p0,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.d},p0,\[z0\.d,sp\]'
@@ -2227,7 +2227,7 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1b {z0\.s}, p0, \[z0\.s, xzr\]
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1b {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1b {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1b {z32\.s},p0,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1b {z0\.s},p8,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1b {z0\.s},p0,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1b {z0\.s},p0,\[z0\.s,sp\]'
@@ -2237,7 +2237,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1d {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1d {z0\.d}, p0, \[z0\.d, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1d {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1d {z32\.d},p0,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1d {z0\.d},p8,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1d {z0\.d},p0,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1d {z0\.d},p0,\[z0\.d,sp\]'
@@ -2251,7 +2251,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1h {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.d},p0,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.d},p8,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.d},p0,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.d},p0,\[z0\.d,sp\]'
@@ -2262,7 +2262,7 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1h {z0\.s}, p0, \[z0\.s, xzr\]
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1h {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1h {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1h {z32\.s},p0,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1h {z0\.s},p8,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1h {z0\.s},p0,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1h {z0\.s},p0,\[z0\.s,sp\]'
@@ -2272,7 +2272,7 @@
 [^ :]+:[0-9]+: Error: operand mismatch -- `stnt1w {z0\.d},p0/m,\[z0\.d\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.d},p0,\[z0\.d\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.d},p0,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.d},p8,\[z0\.d\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.d},p0,\[z32\.d\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.d},p0,\[z0\.d,sp\]'
@@ -2283,7 +2283,7 @@
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	stnt1w {z0\.s}, p0, \[z0\.s, xzr\]
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 1 -- `stnt1w {z0\.s,z1\.d},p0,\[z0\.s,x0\]'
-[^ :]+:[0-9]+: Error: operand 1 must be a list of SVE vector registers -- `stnt1w {z32\.s},p0,\[z0\.s\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `stnt1w {z32\.s},p0,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `stnt1w {z0\.s},p8,\[z0\.s\]'
 [^ :]+:[0-9]+: Error: invalid base register at operand 3 -- `stnt1w {z0\.s},p0,\[z32\.s\]'
 [^ :]+:[0-9]+: Error: invalid offset register at operand 3 -- `stnt1w {z0\.s},p0,\[z0\.s,sp\]'
@@ -2295,21 +2295,21 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	subhnb z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	subhnb z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnb z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnb z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnb z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `subhnb z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `subhnb z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `subhnb z0\.b,z0\.h,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `subhnt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	subhnt z0\.b, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	subhnt z0\.h, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	subhnt z0\.s, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `subhnt z32\.b,z0\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `subhnt z0\.b,z32\.h,z0\.h'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `subhnt z0\.b,z0\.h,z32\.h'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `subhnt z32\.b,z0\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `subhnt z0\.b,z32\.h,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `subhnt z0\.b,z0\.h,z32\.h'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `suqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `suqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `suqadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `suqadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `suqadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `suqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2326,10 +2326,10 @@
 [^ :]+:[0-9]+: Info:    	suqadd z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	suqadd z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	suqadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbl z32\.b,{z0\.b,z1\.b},z0\.b'
 [^ :]+:[0-9]+: Error: operand 2 must be a list of SVE vector registers -- `tbl z0\.b,{z31\.b,z32\.b},z0\.b'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.b,{z31\.b,z1\.b},z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbl z0\.b,{z0\.b,z1\.b},z32\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `tbl z0\.b,{z0\.b,z1\.b},z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	tbl z0\.b, {z0\.b, z1\.b}, z0\.b
@@ -2340,9 +2340,9 @@
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.b,z1\.h},z0\.b'
 [^ :]+:[0-9]+: Error: type mismatch in vector register list at operand 2 -- `tbl z0\.b,{z0\.h,z0\.b},z0\.b'
 [^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `tbl z0\.h,{z0\.b,z0\.b},z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `tbx z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `tbx z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `tbx z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `tbx z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `tbx z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `tbx z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `tbx z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `tbx z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2351,9 +2351,9 @@
 [^ :]+:[0-9]+: Info:    	tbx z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	tbx z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	tbx z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaba z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaba z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaba z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uaba z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaba z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaba z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaba z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uaba z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2362,9 +2362,9 @@
 [^ :]+:[0-9]+: Info:    	uaba z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	uaba z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uaba z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabalb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uabalb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2372,9 +2372,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uabalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uabalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabalt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabalt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uabalt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2382,9 +2382,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uabalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uabalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabdlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabdlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabdlb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uabdlb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2392,9 +2392,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uabdlb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uabdlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uabdlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uabdlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uabdlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uabdlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uabdlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uabdlt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uabdlt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uabdlt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2415,11 +2415,11 @@
 [^ :]+:[0-9]+: Info:    	uadalp z0\.s, p0/m, z0\.h
 [^ :]+:[0-9]+: Info:    	uadalp z0\.d, p0/m, z0\.s
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uadalp z0\.h,p8/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uadalp z32\.h,p0/m,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uadalp z0\.h,p0/m,z32\.b'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uadalp z32\.h,p0/m,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uadalp z0\.h,p0/m,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddlb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddlb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddlb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddlb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2427,9 +2427,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uaddlb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uaddlb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddlt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddlt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddlt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddlt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddlt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddlt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddlt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddlt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2437,9 +2437,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uaddlt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uaddlt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddwb z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwb z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddwb z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2447,9 +2447,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uaddwb z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	uaddwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uaddwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uaddwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uaddwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uaddwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uaddwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uaddwt z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `uaddwt z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uaddwt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2457,9 +2457,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uaddwt z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	uaddwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2476,9 +2476,9 @@
 [^ :]+:[0-9]+: Info:    	uhadd z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uhadd z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uhadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uhsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhsub z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsub z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsub z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -2495,9 +2495,9 @@
 [^ :]+:[0-9]+: Info:    	uhsub z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uhsub z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uhsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uhsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uhsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uhsubr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uhsubr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uhsubr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uhsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2514,9 +2514,9 @@
 [^ :]+:[0-9]+: Info:    	uhsubr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uhsubr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uhsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `umaxp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umaxp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `umaxp z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `umaxp z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `umaxp z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umaxp z0\.h,p0/m,z0\.b,z0\.b'
@@ -2533,9 +2533,9 @@
 [^ :]+:[0-9]+: Info:    	umaxp z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umaxp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	umaxp z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `uminp z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uminp z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uminp z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uminp z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uminp z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uminp z0\.h,p0/m,z0\.b,z0\.b'
@@ -2552,23 +2552,23 @@
 [^ :]+:[0-9]+: Info:    	uminp z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uminp z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uminp z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlalb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2576,23 +2576,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umlalb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umlalb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlalt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlalt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlalt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlalt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlalt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlalt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlalt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlalt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlalt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlalt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlalt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlalt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2600,23 +2600,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umlalt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umlalt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlslb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2624,23 +2624,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umlslb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umlslb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umlslt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umlslt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umlslt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umlslt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umlslt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umlslt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umlslt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umlslt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umlslt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umlslt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umlslt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umlslt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2648,9 +2648,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umlslt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umlslt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umulh z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE predicate register -- `umulh z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `umulh z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `umulh z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector or predicate register at operand 2 -- `umulh z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umulh z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umulh z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umulh z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2659,23 +2659,23 @@
 [^ :]+:[0-9]+: Info:    	umulh z0\.b, z0\.b, z0\.b
 [^ :]+:[0-9]+: Info:    	umulh z0\.s, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	umulh z0\.d, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullb z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullb z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullb z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullb z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umullb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2683,23 +2683,23 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umullb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umullb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.s,z0\.h,z0\.h\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.s,z32\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `umullt z0\.s,z0\.h,z8\.h\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `umullt z0\.s,z0\.h,z0\.h\[8\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.h,z0\.h\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.d,z0\.s,z0\.s\[0\]'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.d,z32\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `umullt z0\.d,z0\.s,z16\.s\[0\]'
 [^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `umullt z0\.d,z0\.s,z0\.s\[4\]'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.s,z0\.s,z0\.s\[0\]'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s\[0\]
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `umullt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `umullt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `umullt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `umullt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `umullt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `umullt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `umullt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `umullt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -2707,9 +2707,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	umullt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	umullt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2726,9 +2726,9 @@
 [^ :]+:[0-9]+: Info:    	uqadd z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqadd z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqrshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqrshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqrshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshl z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2745,9 +2745,9 @@
 [^ :]+:[0-9]+: Info:    	uqrshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqrshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqrshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqrshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqrshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqrshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqrshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2764,8 +2764,8 @@
 [^ :]+:[0-9]+: Info:    	uqrshlr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqrshlr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqrshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqrshrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnb z0\.h,z0\.h,#8'
@@ -2779,8 +2779,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqrshrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqrshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqrshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqrshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqrshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqrshrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqrshrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqrshrnt z0\.h,z0\.h,#8'
@@ -2800,15 +2800,15 @@
 [^ :]+:[0-9]+: Info:    	uqshl z0\.h, p0/m, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	uqshl z0\.s, p0/m, z0\.s, #0
 [^ :]+:[0-9]+: Info:    	uqshl z0\.d, p0/m, z0\.d, #0
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqshl z32\.b,p0/m,z32\.b,#0'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,#0'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 4 -- `uqshl z0\.h,p0/m,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 4 -- `uqshl z0\.s,p0/m,z0\.s,#32'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 63 at operand 4 -- `uqshl z0\.d,p0/m,z0\.d,#64'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqshl z0\.b,p0/m,z32\.b,z0\.b'
 [^ :]+:[0-9]+: Error: constant expression required at operand 4 -- `uqshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshl z0\.b,p8/m,z0\.b,z0\.b'
@@ -2826,9 +2826,9 @@
 [^ :]+:[0-9]+: Info:    	uqshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2845,8 +2845,8 @@
 [^ :]+:[0-9]+: Info:    	uqshlr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqshlr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqshlr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnb z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnb z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshrnb z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqshrnb z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnb z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnb z0\.h,z0\.h,#8'
@@ -2860,8 +2860,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnb z0\.s,z0\.d,#33'
 [^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `uqshrnt z0\.b,z0\.h,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqshrnt z32\.b,z0\.h,#8'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqshrnt z0\.b,z32\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqshrnt z32\.b,z0\.h,#8'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqshrnt z0\.b,z32\.h,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `uqshrnt z0\.b,z0\.h,#0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqshrnt z0\.h,z0\.h,#8'
@@ -2874,9 +2874,9 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `uqshrnt z0\.h,z0\.s,#17'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `uqshrnt z0\.s,z0\.d,#33'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `uqsub z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqsub z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqsub z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsub z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsub z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsub z0\.h,p0/m,z0\.b,z0\.b'
@@ -2893,9 +2893,9 @@
 [^ :]+:[0-9]+: Info:    	uqsub z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqsub z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqsub z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqsubr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `uqsubr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `uqsubr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `uqsubr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `uqsubr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqsubr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2912,31 +2912,31 @@
 [^ :]+:[0-9]+: Info:    	uqsubr z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	uqsubr z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	uqsubr z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnb z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnb z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqxtnb z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqxtnb z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnb z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	uqxtnb z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uqxtnb z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	uqxtnb z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `uqxtnt z32\.b,z0\.h'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `uqxtnt z0\.b,z32\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `uqxtnt z32\.b,z0\.h'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `uqxtnt z0\.b,z32\.h'
 [^ :]+:[0-9]+: Error: operand mismatch -- `uqxtnt z0\.b,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	uqxtnt z0\.b, z0\.h
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	uqxtnt z0\.h, z0\.s
 [^ :]+:[0-9]+: Info:    	uqxtnt z0\.s, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urecpe z32\.s,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urecpe z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `urecpe z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urecpe z0\.s,p0/m,z32\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urecpe z0\.s,p8/m,z0\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `urecpe z0\.d,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	urecpe z0\.s, p0/m, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `urhadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urhadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urhadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urhadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urhadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `urhadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -2953,9 +2953,9 @@
 [^ :]+:[0-9]+: Info:    	urhadd z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	urhadd z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	urhadd z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `urshl z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urshl z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urshl z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshl z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshl z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `urshl z0\.h,p0/m,z0\.b,z0\.b'
@@ -2972,9 +2972,9 @@
 [^ :]+:[0-9]+: Info:    	urshl z0\.h, p0/m, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	urshl z0\.s, p0/m, z0\.s, z0\.s
 [^ :]+:[0-9]+: Info:    	urshl z0\.d, p0/m, z0\.d, z0\.d
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `urshlr z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `urshlr z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `urshlr z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshlr z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshlr z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `urshlr z0\.h,p0/m,z0\.b,z0\.b'
@@ -2998,7 +2998,7 @@
 [^ :]+:[0-9]+: Info:    	urshr z0\.h, p0/m, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	urshr z0\.s, p0/m, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	urshr z0\.d, p0/m, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `urshr z32\.b,p0/m,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `urshr z32\.b,p0/m,z32\.b,#1'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `urshr z0\.b,p0/m,z1\.b,#1'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `urshr z0\.b,p8/m,z0\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `urshr z0\.b,p0/m,z0\.b,#0'
@@ -3009,8 +3009,8 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 4 -- `urshr z0\.s,p0/m,z0\.s,#33'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 4 -- `urshr z0\.d,p0/m,z0\.d,#65'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ursqrte z32\.s,p0/m,z0\.s'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `ursqrte z0\.s,p0/m,z32\.s'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `ursqrte z32\.s,p0/m,z0\.s'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `ursqrte z0\.s,p0/m,z32\.s'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `ursqrte z0\.s,p8/m,z0\.s'
 [^ :]+:[0-9]+: Error: operand mismatch -- `ursqrte z0\.d,p0/m,z0\.s'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -3022,8 +3022,8 @@
 [^ :]+:[0-9]+: Info:    	ursra z0\.h, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	ursra z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	ursra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `ursra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ursra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `ursra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ursra z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `ursra z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `ursra z0\.h,z0\.h,#0'
@@ -3037,8 +3037,8 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ushllb z0\.s, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	ushllb z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllb z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllb z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ushllb z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ushllb z0\.h,z32\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllb z0\.h,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllb z0\.s,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllb z0\.d,z0\.s,#32'
@@ -3048,14 +3048,14 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	ushllt z0\.s, z0\.h, #0
 [^ :]+:[0-9]+: Info:    	ushllt z0\.d, z0\.s, #0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `ushllt z32\.h,z0\.b,#0'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `ushllt z0\.h,z32\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `ushllt z32\.h,z0\.b,#0'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `ushllt z0\.h,z32\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 7 at operand 3 -- `ushllt z0\.h,z0\.b,#8'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 15 at operand 3 -- `ushllt z0\.s,z0\.h,#16'
 [^ :]+:[0-9]+: Error: immediate value out of range 0 to 31 at operand 3 -- `ushllt z0\.d,z0\.s,#32'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 4 must be an SVE vector register -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `usqadd z32\.b,p0/m,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usqadd z0\.b,p0/m,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 4 -- `usqadd z0\.b,p0/m,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `usqadd z0\.b,p0/m,z1\.b,z0\.b'
 [^ :]+:[0-9]+: Error: p0-p7 expected at operand 2 -- `usqadd z0\.b,p8/m,z0\.b,z0\.b'
 [^ :]+:[0-9]+: Error: operand mismatch -- `usqadd z0\.h,p0/m,z0\.b,z0\.b'
@@ -3079,8 +3079,8 @@
 [^ :]+:[0-9]+: Info:    	usra z0\.h, z0\.h, #1
 [^ :]+:[0-9]+: Info:    	usra z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	usra z0\.d, z0\.d, #1
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD scalar register -- `usra z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usra z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `usra z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usra z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 3 -- `usra z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `usra z0\.h,z0\.h,#0'
@@ -3088,9 +3088,9 @@
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 32 at operand 3 -- `usra z0\.s,z0\.s,#33'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 64 at operand 3 -- `usra z0\.d,z0\.d,#0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublb z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublb z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublb z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usublb z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usublb z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usublb z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublb z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `usublb z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -3098,9 +3098,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	usublb z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	usublb z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usublt z32\.h,z0\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usublt z0\.h,z32\.b,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usublt z0\.h,z0\.b,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usublt z32\.h,z0\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usublt z0\.h,z32\.b,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usublt z0\.h,z0\.b,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usublt z0\.s,z0\.h,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `usublt z0\.h,z0\.b,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -3108,9 +3108,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	usublt z0\.s, z0\.h, z0\.h
 [^ :]+:[0-9]+: Info:    	usublt z0\.d, z0\.s, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwb z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwb z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwb z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usubwb z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usubwb z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usubwb z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwb z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `usubwb z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -3118,9 +3118,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	usubwb z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	usubwb z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `usubwt z32\.h,z0\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `usubwt z0\.h,z32\.h,z0\.b'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `usubwt z0\.h,z0\.h,z32\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 1 -- `usubwt z32\.h,z0\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `usubwt z0\.h,z32\.h,z0\.b'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `usubwt z0\.h,z0\.h,z32\.b'
 [^ :]+:[0-9]+: Error: unexpected character `x' in element size at operand 3 -- `usubwt z0\.s,z0\.s,z0\.x'
 [^ :]+:[0-9]+: Error: operand mismatch -- `usubwt z0\.h,z0\.h,z0\.h'
 [^ :]+:[0-9]+: Info:    did you mean this\?
@@ -3128,9 +3128,9 @@
 [^ :]+:[0-9]+: Info:    other valid variant\(s\):
 [^ :]+:[0-9]+: Info:    	usubwt z0\.s, z0\.s, z0\.h
 [^ :]+:[0-9]+: Info:    	usubwt z0\.d, z0\.d, z0\.s
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
@@ -3138,8 +3138,8 @@
 [^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x31'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0\.b,x0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
@@ -3154,9 +3154,9 @@
 [^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilege p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilege p0\.b, x0, x0
@@ -3164,11 +3164,11 @@
 [^ :]+:[0-9]+: Info:    	whilege p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilege p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilege p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilege p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
@@ -3176,8 +3176,8 @@
 [^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x31'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0\.b,x0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
@@ -3192,9 +3192,9 @@
 [^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilegt p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilegt p0\.b, x0, x0
@@ -3202,11 +3202,11 @@
 [^ :]+:[0-9]+: Info:    	whilegt p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilegt p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilegt p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilegt p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
@@ -3214,8 +3214,8 @@
 [^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x31'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0\.b,x0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
@@ -3230,9 +3230,9 @@
 [^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehi p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehi p0\.b, x0, x0
@@ -3240,11 +3240,11 @@
 [^ :]+:[0-9]+: Info:    	whilehi p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehi p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehi p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehi p0\.b,w0,w31'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,x0,x0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x32'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
@@ -3252,8 +3252,8 @@
 [^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,x31,x0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,x0,x31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x31,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x31'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0\.b,x0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
@@ -3268,9 +3268,9 @@
 [^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilehs p16\.b,w0,w0'
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w32,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w32'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,w0,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w32,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilehs p0\.b, x0, x0
@@ -3278,8 +3278,8 @@
 [^ :]+:[0-9]+: Info:    	whilehs p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilehs p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilehs p0\.b,w31,w0'
-[^ :]+:[0-9]+: Error: operand 3 must be an integer register -- `whilehs p0\.b,w0,w31'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w31,w0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w31'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilerw p0\.b,w0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilerw p0\.b, x0, x0
@@ -3294,8 +3294,8 @@
 [^ :]+:[0-9]+: Info:    	whilerw p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilerw p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilerw p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilerw p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilerw p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilerw p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilerw p16\.b,x0,x0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `whilewr p0\.b,w0,x0'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	whilewr p0\.b, x0, x0
@@ -3310,8 +3310,8 @@
 [^ :]+:[0-9]+: Info:    	whilewr p0\.h, x0, x0
 [^ :]+:[0-9]+: Info:    	whilewr p0\.s, x0, x0
 [^ :]+:[0-9]+: Info:    	whilewr p0\.d, x0, x0
-[^ :]+:[0-9]+: Error: operand 2 must be an integer register -- `whilewr p0\.b,x32,x0'
-[^ :]+:[0-9]+: Error: operand 1 must be an SVE predicate register -- `whilewr p16\.b,x0,x0'
+[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilewr p0\.b,x32,x0'
+[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilewr p16\.b,x0,x0'
 [^ :]+:[0-9]+: Error: operand mismatch -- `xar z0\.h,z0\.b,z0\.b,#1'
 [^ :]+:[0-9]+: Info:    did you mean this\?
 [^ :]+:[0-9]+: Info:    	xar z0\.b, z0\.b, z0\.b, #1
@@ -3320,8 +3320,8 @@
 [^ :]+:[0-9]+: Info:    	xar z0\.s, z0\.s, z0\.s, #1
 [^ :]+:[0-9]+: Info:    	xar z0\.d, z0\.d, z0\.d, #1
 [^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `xar z0\.b,z1\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 1 must be a SIMD vector register -- `xar z32\.b,z32\.b,z0\.b,#1'
-[^ :]+:[0-9]+: Error: operand 3 must be an SVE vector register -- `xar z0\.b,z0\.b,z32\.b,#1'
+[^ :]+:[0-9]+: Error: expected a vector register at operand 1 -- `xar z32\.b,z32\.b,z0\.b,#1'
+[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 3 -- `xar z0\.b,z0\.b,z32\.b,#1'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#0'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 8 at operand 4 -- `xar z0\.b,z0\.b,z0\.b,#9'
 [^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 4 -- `xar z0\.h,z0\.h,z0\.h,#0'
diff --git a/gas/testsuite/gas/aarch64/legacy_reg_names.l b/gas/testsuite/gas/aarch64/legacy_reg_names.l
index 791bad33a69..f3dde54e418 100644
--- a/gas/testsuite/gas/aarch64/legacy_reg_names.l
+++ b/gas/testsuite/gas/aarch64/legacy_reg_names.l
@@ -1,4 +1,4 @@
 [^:]*: Assembler messages:
 [^:]*:5: Error: indexed vector register expected at operand 1 -- `dup v0.b,v1.b\[7\]'
-[^:]*:6: Error: operand 1 must be an integer register -- `mov r0.w,r1.w'
-[^:]*:7: Error: operand 2 must be a SIMD vector element -- `dup s0,s1\[3\]'
+[^:]*:6: Error: expected a register at operand 1 -- `mov r0.w,r1.w'
+[^:]*:7: Error: expected an Advanced SIMD vector register at operand 2 -- `dup s0,s1\[3\]'
diff --git a/gas/testsuite/gas/aarch64/mops_invalid.l b/gas/testsuite/gas/aarch64/mops_invalid.l
index 8f5e588482c..76a5c30fd1e 100644
--- a/gas/testsuite/gas/aarch64/mops_invalid.l
+++ b/gas/testsuite/gas/aarch64/mops_invalid.l
@@ -10,44 +10,44 @@
 [^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,#0\]!,x2!'
 [^:]+:[0-9]+: Error: operand 2 must be a register source address with writeback -- `cpyfp \[x1\]!,\[x0,xzr\]!,x2!'
 [^:]+:[0-9]+: Error: operand 3 must be an integer register with writeback -- `cpyfp \[x0\]!,\[x1\]!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,!x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,\[x2\]!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[x31\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[sp\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[zr\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w30\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[w0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wsp\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[wzr\]!,\[x0\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[b0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[h0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[s0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[d0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[q0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[v0.2d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[z0.d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[p0.d\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `cpyfp \[foo\]!,\[x1\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[x31\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[sp\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[zr\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[w30\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[w0\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wsp\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x0\]!,\[wzr\]!,x1!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `cpyfp \[x1\]!,\[foo\]!,x2!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,x31!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,sp!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,zr!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,w30!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,w0!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wsp!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x0\]!,\[x1\]!,wzr!'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 3 -- `cpyfp \[x1\]!,\[x2\]!,foo!'
 [^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x0\]!,\[x0\]!,x1!'
 [^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x10\]!,\[x1\]!,x10!'
 [^:]+:[0-9]+: Error: the three register operands must be distinct from one another -- `cpyfp \[x1\]!,\[x30\]!,x30!'
@@ -56,24 +56,24 @@
 [^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0\],x1!,x2'
 [^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,#0\]!,x1!,x2'
 [^:]+:[0-9]+: Error: operand 1 must be a register destination address with writeback -- `setp \[x0,xzr\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[x31\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[sp\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[zr\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w30\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[w0\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wsp\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[wzr\]!,x0!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 1 -- `setp \[foo\]!,x1!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,x31!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,sp!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,zr!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,w30!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,w0!,x2'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wsp!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x0\]!,wzr!,x1'
-[^:]+:[0-9]+: Error: integer 64-bit register expected at operand 2 -- `setp \[x1\]!,foo!,x2'
-[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,sp'
-[^:]+:[0-9]+: Error: operand 3 must be an integer register -- `setp \[x30\]!,x0!,wsp'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[x31\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[sp\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[zr\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w30\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[w0\]!,x1!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wsp\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[wzr\]!,x0!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 1 -- `setp \[foo\]!,x1!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,x31!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,sp!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,zr!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,w30!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,w0!,x2'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wsp!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x0\]!,wzr!,x1'
+[^:]+:[0-9]+: Error: expected a 64-bit integer register at operand 2 -- `setp \[x1\]!,foo!,x2'
+[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,sp'
+[^:]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `setp \[x30\]!,x0!,wsp'
 [^:]+:[0-9]+: Error: operand mismatch -- `setp \[x30\]!,x0!,wzr'
 [^:]+:[0-9]+: Info:    did you mean this\?
 [^:]+:[0-9]+: Info:    	setp \[x30\]!, x0!, xzr
diff --git a/gas/testsuite/gas/aarch64/sme-2-illegal.l b/gas/testsuite/gas/aarch64/sme-2-illegal.l
index b4ce9dc69fd..1df18ef2002 100644
--- a/gas/testsuite/gas/aarch64/sme-2-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-2-illegal.l
@@ -3,7 +3,7 @@
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.h,p0/m,za2h\.h\[w12,#0\]'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.s,p0/m,za4h\.s\[w12,#0\]'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 3 -- `mova z0\.d,p0/m,za8h\.d\[w12,#0\]'
-[^:]*:[0-9]+: Error: operand 3 must be an SME horizontal or vertical vector access register -- `mova z0\.q,p0/m,za16h.q\[w12\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 3 -- `mova z0\.q,p0/m,za16h.q\[w12\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 3 -- `mova z31\.b,p7/m,za0v\.b\[w15,#16\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 3 -- `mova z31\.h,p7/m,za1v\.h\[w15,#8\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 3 -- `mova z31\.s,p7/m,za3v\.s\[w15,#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-3-illegal.l b/gas/testsuite/gas/aarch64/sme-3-illegal.l
index cb8fe4ef47a..717af3b54be 100644
--- a/gas/testsuite/gas/aarch64/sme-3-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-3-illegal.l
@@ -3,7 +3,7 @@
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za2v\.h\[w12,#0\],p0/m,z0.h'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za4v\.s\[w12,#0\],p0/m,z0.s'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `mova za8v\.d\[w12,#0\],p0/m,z0.d'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `mova za16v\.q\[w12\],p0/m,z0.q'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `mova za16v\.q\[w12\],p0/m,z0.q'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 15 at operand 1 -- `mova za0v\.b\[w15,#16\],p7/m,z31.b'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `mova za1v\.h\[w15,#8\],p7/m,z31.h'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 3 at operand 1 -- `mova za3v\.s\[w15,#4\],p7/m,z31.s'
diff --git a/gas/testsuite/gas/aarch64/sme-4-illegal.l b/gas/testsuite/gas/aarch64/sme-4-illegal.l
index 57d7d65c08c..86e315476dd 100644
--- a/gas/testsuite/gas/aarch64/sme-4-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-4-illegal.l
@@ -22,11 +22,11 @@
 [^:]*:[0-9]+: Error: syntax error in register list at operand 1 -- `zero {za,}'
 [^:]*:[0-9]+: Error: unexpected character `}' in element size at operand 1 -- `zero {za.}'
 [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za_}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {za_}'
 [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zaX}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zaX}'
 [^:]*:[0-9]+: Error: missing ZA tile size at operand 1 -- `zero {za0}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {zax}'
+[^:]*:[0-9]+: Error: expected 'za' or a ZA tile at operand 1 -- `zero {zax}'
 [^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
 [^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
 [^:]*:[0-9]+: Error: ZA tile masks do not operate at .Q granularity at operand 1 -- `zero {za0\.q}'
@@ -37,5 +37,5 @@
 [^:]*:[0-9]+: Error: ZA should not have a size suffix at operand 1 -- `zero {za\.q}'
 [^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za.2d}'
 [^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `zero {za0.2d}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0h\.b}'
-[^:]*:[0-9]+: Error: operand 1 must be a list of 64-bit ZA element tiles -- `zero {za0v\.b}'
+[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0h\.b}'
+[^:]*:[0-9]+: Error: expected an unsuffixed ZA tile at operand 1 -- `zero {za0v\.b}'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.l b/gas/testsuite/gas/aarch64/sme-5-illegal.l
index 852f1547634..f892dcd2090 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.l
@@ -35,10 +35,10 @@
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7v.d\[w15,2\]},p7/z,\[x0,x17,lsl#3\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `ld1d {za7h.d\[w15,2\]},p7/z,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16v.q\[w12\]},p0/z,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `ld1q {za16h.q\[w12\]},p0/z,\[sp,x0,lsl#4\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x17\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15h.q\[w15,1\]},p7/z,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `ld1q {za15v.q\[w15,1\]},p7/z,\[x0,x17,lsl#4\]'
@@ -49,3 +49,10 @@
 [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1d {za0h.d\[w12,0\]},p0/z,\[x0,x1,lsl#4\]'
 [^:]*:[0-9]+: Error: invalid addressing mode at operand 3 -- `ld1q {za0v.q\[w12,0\]},p0/z,\[x0,x1,lsl#1\]'
 [^:]*:[0-9]+: Error: missing immediate offset at operand 1 -- `ld1q {za0v.q\[w12\]},p0/z,\[x0,x1,lsl#1\]'
+[^:]*:[0-9]+: Error: missing horizontal or vertical suffix at operand 1 -- `ld1b {za0.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {za.b\[w12,0\]},p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1b za0h.b\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1h za0h.h\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1w za0h.s\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1d za0h.d\[w12,0\],p0/z,\[x0\]'
+[^:]*:[0-9]+: Error: missing braces at operand 1 -- `ld1q za0h.q\[w12,0\],p0/z,\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-5-illegal.s b/gas/testsuite/gas/aarch64/sme-5-illegal.s
index bf65f6af5ce..29f86669043 100644
--- a/gas/testsuite/gas/aarch64/sme-5-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-5-illegal.s
@@ -50,3 +50,10 @@ ld1w {za3v.s[w12, 3]}, p7/z, [x0, x1, lsl #3]
 ld1d {za0h.d[w12, 0]}, p0/z, [x0, x1, lsl #4]
 ld1q {za0v.q[w12, 0]}, p0/z, [x0, x1, lsl #1]
 ld1q {za0v.q[w12]}, p0/z, [x0, x1, lsl #1]
+ld1b {za0.b[w12, 0]}, p0/z, [x0]
+ld1b {za.b[w12, 0]}, p0/z, [x0]
+ld1b za0h.b[w12, 0], p0/z, [x0]
+ld1h za0h.h[w12, 0], p0/z, [x0]
+ld1w za0h.s[w12, 0], p0/z, [x0]
+ld1d za0h.d[w12, 0], p0/z, [x0]
+ld1q za0h.q[w12, 0], p0/z, [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-6-illegal.l b/gas/testsuite/gas/aarch64/sme-6-illegal.l
index 30aea0b75ea..c8141e086ab 100644
--- a/gas/testsuite/gas/aarch64/sme-6-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-6-illegal.l
@@ -35,10 +35,10 @@
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7v.d\[w15,2\]},p7,\[x0,x17,lsl#3\]'
 [^:]*:[0-9]+: Error: immediate offset out of range 0 to 1 at operand 1 -- `st1d {za7h.d\[w15,2\]},p7,\[sp,x17,lsl#3\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
-[^:]*:[0-9]+: Error: operand 1 must be an SME horizontal or vertical vector access register -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16v.q\[w12\]},p0,\[x0,x0,lsl#4\]'
+[^:]*:[0-9]+: Error: expected a ZA tile slice at operand 1 -- `st1q {za16h.q\[w12\]},p0,\[sp,x0,lsl#4\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x17\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15h.q\[w15,1\]},p7,\[sp\]'
 [^:]*:[0-9]+: Error: immediate offset must be 0 at operand 1 -- `st1q {za15v.q\[w15,1\]},p7,\[x0,x17,lsl#4\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.l b/gas/testsuite/gas/aarch64/sme-7-illegal.l
index cf4bca2cd20..0023a84da71 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.l
@@ -48,3 +48,9 @@
 [^:]*:[0-9]+: Info:    	ldr za\[w12, 0\], \[x0\]
 [^:]*:[0-9]+: Error: expected '\[' at operand 1 -- `ldr za/z\[w12,0\],\[x0\]'
 [^:]*:[0-9]+: Error: unexpected character `2' in element size at operand 1 -- `ldr za.2b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0.b\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0h.h\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v\[w12,0\],\[x0\]'
+[^:]*:[0-9]+: Error: expected 'za' rather than a ZA tile at operand 1 -- `ldr za0v.s\[w12,0\],\[x0\]'
diff --git a/gas/testsuite/gas/aarch64/sme-7-illegal.s b/gas/testsuite/gas/aarch64/sme-7-illegal.s
index 0669fe16dd4..75e2810e647 100644
--- a/gas/testsuite/gas/aarch64/sme-7-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-7-illegal.s
@@ -45,3 +45,10 @@ ldr za.d[w12, 0], [x0]
 ldr za.q[w12, 0], [x0]
 ldr za/z[w12, 0], [x0]
 ldr za.2b[w12, 0], [x0]
+
+ldr za0[w12, 0], [x0]
+ldr za0.b[w12, 0], [x0]
+ldr za0h[w12, 0], [x0]
+ldr za0h.h[w12, 0], [x0]
+ldr za0v[w12, 0], [x0]
+ldr za0v.s[w12, 0], [x0]
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.l b/gas/testsuite/gas/aarch64/sme-illegal.l
index efc9b800656..f8d05478cc6 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.l
+++ b/gas/testsuite/gas/aarch64/sme-illegal.l
@@ -4,6 +4,7 @@
 [^:]*:[0-9]+: Error: operand mismatch -- `addha za0.s,p2/m,p3/m,z2.d'
 [^:]*:[0-9]+: Info:    did you mean this\?
 [^:]*:[0-9]+: Info:    	addha za0.d, p2/m, p3/m, z2.d
+[^:]*:[0-9]+: Error: expected a ZA tile at operand 1 -- `addha z0.s,p0/m,p1/m,z1.s'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za8.d,p0/m,p1/m,z1.d'
 [^:]*:[0-9]+: Error: ZA tile number out of range at operand 1 -- `addha za15.d,p2/m,p3/m,z2.d'
 [^:]*:[0-9]+: Error: operand mismatch -- `addha za0.d,p2/m,p3/m,z2.s'
diff --git a/gas/testsuite/gas/aarch64/sme-illegal.s b/gas/testsuite/gas/aarch64/sme-illegal.s
index d543a64217a..512d4523a17 100644
--- a/gas/testsuite/gas/aarch64/sme-illegal.s
+++ b/gas/testsuite/gas/aarch64/sme-illegal.s
@@ -4,6 +4,7 @@
 addha za4.s, p0/m, p1/m, z1.s
 addha za15.s, p2/m, p3/m, z2.s
 addha za0.s, p2/m, p3/m, z2.d
+addha z0.s, p0/m, p1/m, z1.s
 
 /* ADDHA 64-bit variant.  */
 addha za8.d, p0/m, p1/m, z1.d
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index b0750933612..ca447307b9e 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1,5 +1,5 @@
 [^:]*: Assembler messages:
-.*: Error: operand 2 must be an SVE predicate register -- `fmov z1,z2'
+.*: Error: expected an SVE predicate register at operand 2 -- `fmov z1,z2'
 .*: Error: operand mismatch -- `fmov z1,#1\.0'
 .*: Info:    did you mean this\?
 .*: Info:    	fmov z1\.h, #1\.000000000000000000e\+00
@@ -126,7 +126,7 @@
 .*: Info:    	movprfx z0\.s, p1/m, z1\.s
 .*: Info:    	movprfx z0\.d, p1/z, z1\.d
 .*: Info:    	movprfx z0\.d, p1/m, z1\.d
-.*: Error: operand 1 must be an SVE vector register -- `movprfx p0,p1'
+.*: Error: expected an SVE vector register at operand 1 -- `movprfx p0,p1'
 .*: Error: operand mismatch -- `ldr p0\.b,\[x1\]'
 .*: Info:    did you mean this\?
 .*: Info:    	ldr p0, \[x1\]
@@ -184,7 +184,7 @@
 .*: Info:    	add z0\.s, z0\.s, #1
 .*: Info:    	add z0\.d, z0\.d, #1
 .*: Error: constant expression required at operand 2 -- `mov z0\.b,z32\.b'
-.*: Error: operand 2 must be an SVE predicate register -- `mov p0\.b,p16\.b'
+.*: Error: expected an SVE predicate register at operand 2 -- `mov p0\.b,p16\.b'
 .*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p8/z,z1\.b,z2\.b'
 .*: Error: p0-p7 expected at operand 2 -- `cmpeq p0\.b,p15/z,z1\.b,z2\.b'
 .*: Error: operand mismatch -- `ld1w z0\.s,p0,\[x0\]'
@@ -275,12 +275,12 @@
 .*: Error: missing type suffix at operand 1 -- `stnt1h {z0},p1/z,\[x1\]'
 .*: Error: missing type suffix at operand 1 -- `stnt1w {z0},p1/z,\[x1\]'
 .*: Error: missing type suffix at operand 1 -- `stnt1d {z0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {x0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {b0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {h0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {s0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {d0},p1/z,\[x1\]'
-.*: Error: operand 1 must be a list of SVE vector registers -- `ld1b {v0\.2s},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {x0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {b0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {h0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {s0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {d0},p1/z,\[x1\]'
+.*: Error: expected an SVE vector register or ZA tile slice at operand 1 -- `ld1b {v0\.2s},p1/z,\[x1\]'
 .*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1},p1/z,\[x1\]'
 .*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.h},p1/z,\[x1\]'
 .*: Error: type mismatch in vector register list at operand 1 -- `ld2b {z0\.b,z1\.s},p1/z,\[x1\]'
@@ -859,7 +859,7 @@
 .*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#-1'
 .*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#8'
 .*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#9'
-.*: Error: operand 3 must be an SVE vector register -- `lsl z0\.b,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 3 -- `lsl z0\.b,z0\.b,x0'
 .*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#-1'
 .*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#16'
 .*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#17'
@@ -872,7 +872,7 @@
 .*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#-1'
 .*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#8'
 .*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#9'
-.*: Error: operand 4 must be an SVE vector register -- `lsl z0\.b,p1/m,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 4 -- `lsl z0\.b,p1/m,z0\.b,x0'
 .*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#-1'
 .*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#16'
 .*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#17'
@@ -885,7 +885,7 @@
 .*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#-1'
 .*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#0'
 .*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#9'
-.*: Error: operand 3 must be an SVE vector register -- `lsr z0\.b,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 3 -- `lsr z0\.b,z0\.b,x0'
 .*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#-1'
 .*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#0'
 .*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#17'
@@ -898,7 +898,7 @@
 .*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#-1'
 .*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#0'
 .*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#9'
-.*: Error: operand 4 must be an SVE vector register -- `lsr z0\.b,p1/m,z0\.b,x0'
+.*: Error: expected an SVE vector register at operand 4 -- `lsr z0\.b,p1/m,z0\.b,x0'
 .*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#-1'
 .*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#0'
 .*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#17'
@@ -914,8 +914,8 @@
 .*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#16'
 .*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl x0,sp,#-33'
 .*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl sp,x0,#32'
-.*: Error: operand 2 must be an integer register or SP -- `addpl x0,xzr,#1'
-.*: Error: operand 1 must be an integer or stack pointer register -- `addpl xzr,x0,#1'
+.*: Error: expected an integer or stack pointer register at operand 2 -- `addpl x0,xzr,#1'
+.*: Error: expected an integer or stack pointer register at operand 1 -- `addpl xzr,x0,#1'
 .*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#-129'
 .*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#128'
 .*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#-129'
diff --git a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
index 34d6634714a..435d52a721f 100644
--- a/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
+++ b/gas/testsuite/gas/aarch64/sve-reg-diagnostic.l
@@ -1,6 +1,6 @@
 .*: Assembler messages:
-.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,x0'
-.*: Error: operand 3 must be a SIMD vector register -- `cmeq v0\.4s,v1\.4s,s0'
+.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,x0'
+.*: Error: expected an Advanced SIMD vector register at operand 3 -- `cmeq v0\.4s,v1\.4s,s0'
 .*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,p0\.b'
 .*: Error: immediate zero expected at operand 3 -- `cmeq v0\.4s,v1\.4s,#p0\.b'
 .*: Error: invalid base register at operand 2 -- `ldr x1,\[s0\]'
@@ -19,6 +19,6 @@
 .*: Error: immediate out of range at operand 3 -- `and x0,x0,#z0\.s'
 .*: Error: immediate out of range at operand 3 -- `and x0,x0,p0'
 .*: Error: immediate out of range at operand 3 -- `and x0,x0,#p0'
-.*: Error: operand 3 must be an integer register -- `lsl x0,x0,s0'
+.*: Error: expected an integer or zero register at operand 3 -- `lsl x0,x0,s0'
 .*: Error: immediate operand required at operand 1 -- `svc x0'
 .*: Error: immediate operand required at operand 1 -- `svc s0'
diff --git a/gas/testsuite/gas/aarch64/tme-invalid.l b/gas/testsuite/gas/aarch64/tme-invalid.l
index 22f60c5b117..dd1a7d111ce 100644
--- a/gas/testsuite/gas/aarch64/tme-invalid.l
+++ b/gas/testsuite/gas/aarch64/tme-invalid.l
@@ -12,7 +12,7 @@
 .*: Error: constant expression required at operand 1 -- `tcancel wsp'
 .*: Error: constant expression required at operand 1 -- `tcancel xsp'
 .*: Error: constant expression required at operand 1 -- `tcancel sp'
-.*: Error: operand 1 must be an integer register -- `tstart'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart'
 .*: Error: operand mismatch -- `tstart w1'
 .*: Info:    did you mean this\?
 .*: Info:    	tstart x1
@@ -22,5 +22,5 @@
 .*: Error: operand mismatch -- `tstart wzr'
 .*: Info:    did you mean this\?
 .*: Info:    	tstart xzr
-.*: Error: operand 1 must be an integer register -- `tstart wsp'
-.*: Error: operand 1 must be an integer register -- `tstart xsp'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart wsp'
+.*: Error: expected an integer or zero register at operand 1 -- `tstart xsp'
