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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id la21-20020a170906ad9500b009309c7f5650si14311596ejb.23.2023.03.30.03.31.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Mar 2023 03:31:05 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=EO73a47A; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A15D238A815D for ; Thu, 30 Mar 2023 10:27:31 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A15D238A815D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1680172051; bh=C/EHFiCfl5tLnfw0xBJDfvV3aj97MSd+lf1sNpdKOXY=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=EO73a47AP6we3tFSapG8vXt+wbcnmayn5o1VDXy5SUG4U6j0y3PtLlevy/U/pEpzB ARb8u5z0du6Zf4Gt32VLc1ooBMZDdsojaMACfs2DwInlT9gu4eTQ+SNIyBOs5CmlSq HShFOkRZWd+eXNwwq1Oc+YYdecWqVmsOKaVBA1z4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by sourceware.org (Postfix) with ESMTP id EC8F938582BE for ; Thu, 30 Mar 2023 10:24:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EC8F938582BE Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 272C21595; Thu, 30 Mar 2023 03:25:08 -0700 (PDT) Received: from e121540-lin.manchester.arm.com (e121540-lin.manchester.arm.com [10.32.110.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5E75D3F663; Thu, 30 Mar 2023 03:24:23 -0700 (PDT) To: binutils@sourceware.org Cc: Richard Sandiford Subject: [PATCH 13/43] aarch64: Rename za_tile_vector to za_index Date: Thu, 30 Mar 2023 11:23:29 +0100 Message-Id: <20230330102359.3327695-14-richard.sandiford@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230330102359.3327695-1-richard.sandiford@arm.com> References: <20230330102359.3327695-1-richard.sandiford@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-33.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Sandiford via Binutils From: Richard Sandiford Reply-To: Richard Sandiford Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1761788313014585688?= X-GMAIL-MSGID: =?utf-8?q?1761788313014585688?= za_tile_vector is also used for indexing ZA as a whole, rather than just for indexing tiles. The former is more common than the latter in SME2, so this patch generalises the name to "indexed_za". The patch also names the associated structure, so that later patches can reuse it during parsing. --- gas/config/tc-aarch64.c | 18 +++++++++--------- include/opcode/aarch64.h | 23 +++++++++++++---------- opcodes/aarch64-asm.c | 18 +++++++++--------- opcodes/aarch64-dis.c | 34 +++++++++++++++++----------------- opcodes/aarch64-opc.c | 20 ++++++++++---------- 5 files changed, 58 insertions(+), 55 deletions(-) diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 26588cb4596..b06a9379f2e 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -7185,9 +7185,9 @@ parse_operands (char *str, const aarch64_opcode *opcode) if (val == PARSE_FAIL) goto failure; - info->za_tile_vector.regno = val; - info->za_tile_vector.index.regno = index_base_reg; - info->za_tile_vector.index.imm = imm; + info->indexed_za.regno = val; + info->indexed_za.index.regno = index_base_reg; + info->indexed_za.index.imm = imm; info->qualifier = qualifier; break; } @@ -7535,10 +7535,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) &qualifier); if (val == PARSE_FAIL) goto failure; - info->za_tile_vector.regno = val; - info->za_tile_vector.index.regno = vector_select_register; - info->za_tile_vector.index.imm = imm; - info->za_tile_vector.v = slice_indicator; + info->indexed_za.regno = val; + info->indexed_za.index.regno = vector_select_register; + info->indexed_za.index.imm = imm; + info->indexed_za.v = slice_indicator; info->qualifier = qualifier; break; } @@ -7556,8 +7556,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) val = parse_sme_za_array (&str, &imm); if (val == PARSE_FAIL) goto failure; - info->za_tile_vector.index.regno = val; - info->za_tile_vector.index.imm = imm; + info->indexed_za.index.regno = val; + info->indexed_za.index.imm = imm; break; } diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 691247aa934..4a554df2b36 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1108,6 +1108,18 @@ extern const aarch64_cond aarch64_conds[16]; const aarch64_cond* get_cond_from_value (aarch64_insn value); const aarch64_cond* get_inverted_cond (const aarch64_cond *cond); +/* Information about a reference to part of ZA. */ +struct aarch64_indexed_za +{ + int regno; /* */ + struct + { + int regno; /* */ + int imm; /* */ + } index; + unsigned v : 1; /* horizontal or vertical vector indicator. */ +}; + /* Structure representing an operand. */ struct aarch64_opnd_info @@ -1172,16 +1184,7 @@ struct aarch64_opnd_info } sysreg; /* ZA tile vector, e.g. .D[{, }] */ - struct - { - int regno; /* */ - struct - { - int regno; /* */ - int imm; /* */ - } index; - unsigned v : 1; /* horizontal or vertical vector indicator. */ - } za_tile_vector; + struct aarch64_indexed_za indexed_za; const aarch64_cond *cond; /* The encoding of the PSTATE field. */ diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index bfabcb9e3a2..73ee15a0257 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1340,10 +1340,10 @@ aarch64_ins_sme_za_hv_tiles (const aarch64_operand *self, { int fld_size; int fld_q; - int fld_v = info->za_tile_vector.v; - int fld_rv = info->za_tile_vector.index.regno - 12; - int fld_zan_imm = info->za_tile_vector.index.imm; - int regno = info->za_tile_vector.regno; + int fld_v = info->indexed_za.v; + int fld_rv = info->indexed_za.index.regno - 12; + int fld_zan_imm = info->indexed_za.index.imm; + int regno = info->indexed_za.regno; switch (info->qualifier) { @@ -1410,8 +1410,8 @@ aarch64_ins_sme_za_array (const aarch64_operand *self, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int regno = info->za_tile_vector.index.regno - 12; - int imm = info->za_tile_vector.index.imm; + int regno = info->indexed_za.index.regno - 12; + int imm = info->indexed_za.index.imm; insert_field (self->fields[0], code, regno, 0); insert_field (self->fields[1], code, imm, 0); return true; @@ -1464,9 +1464,9 @@ aarch64_ins_sme_pred_reg_with_index (const aarch64_operand *self, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED) { - int fld_pn = info->za_tile_vector.regno; - int fld_rm = info->za_tile_vector.index.regno - 12; - int imm = info->za_tile_vector.index.imm; + int fld_pn = info->indexed_za.regno; + int fld_rm = info->indexed_za.index.regno - 12; + int imm = info->indexed_za.index.imm; int fld_i1, fld_tszh, fld_tshl; insert_field (self->fields[0], code, fld_rm, 0); diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c index 01881ea377d..eabcc9ee586 100644 --- a/opcodes/aarch64-dis.c +++ b/opcodes/aarch64-dis.c @@ -1786,34 +1786,34 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self, /* Deduce qualifier encoded in size and Q fields. */ if (fld_size == 0) { - info->za_tile_vector.regno = 0; - info->za_tile_vector.index.imm = fld_zan_imm; + info->indexed_za.regno = 0; + info->indexed_za.index.imm = fld_zan_imm; } else if (fld_size == 1) { - info->za_tile_vector.regno = fld_zan_imm >> 3; - info->za_tile_vector.index.imm = fld_zan_imm & 0x07; + info->indexed_za.regno = fld_zan_imm >> 3; + info->indexed_za.index.imm = fld_zan_imm & 0x07; } else if (fld_size == 2) { - info->za_tile_vector.regno = fld_zan_imm >> 2; - info->za_tile_vector.index.imm = fld_zan_imm & 0x03; + info->indexed_za.regno = fld_zan_imm >> 2; + info->indexed_za.index.imm = fld_zan_imm & 0x03; } else if (fld_size == 3 && fld_q == 0) { - info->za_tile_vector.regno = fld_zan_imm >> 1; - info->za_tile_vector.index.imm = fld_zan_imm & 0x01; + info->indexed_za.regno = fld_zan_imm >> 1; + info->indexed_za.index.imm = fld_zan_imm & 0x01; } else if (fld_size == 3 && fld_q == 1) { - info->za_tile_vector.regno = fld_zan_imm; - info->za_tile_vector.index.imm = 0; + info->indexed_za.regno = fld_zan_imm; + info->indexed_za.index.imm = 0; } else return false; - info->za_tile_vector.index.regno = fld_rv + 12; - info->za_tile_vector.v = fld_v; + info->indexed_za.index.regno = fld_rv + 12; + info->indexed_za.v = fld_v; return true; } @@ -1847,8 +1847,8 @@ aarch64_ext_sme_za_array (const aarch64_operand *self, { int regno = extract_field (self->fields[0], code, 0) + 12; int imm = extract_field (self->fields[1], code, 0); - info->za_tile_vector.index.regno = regno; - info->za_tile_vector.index.imm = imm; + info->indexed_za.index.regno = regno; + info->indexed_za.index.imm = imm; return true; } @@ -1902,8 +1902,8 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self, aarch64_insn fld_tszl = extract_field (self->fields[4], code, 0); int imm; - info->za_tile_vector.regno = fld_pn; - info->za_tile_vector.index.regno = fld_rm + 12; + info->indexed_za.regno = fld_pn; + info->indexed_za.index.regno = fld_rm + 12; if (fld_tszl & 0x1) imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1); @@ -1916,7 +1916,7 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self, else return false; - info->za_tile_vector.index.imm = imm; + info->indexed_za.index.imm = imm; return true; } diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index a0e6240592c..bbbac418f91 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -2770,7 +2770,7 @@ aarch64_match_operands_constraint (aarch64_inst *inst, case sme_str: assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array); assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL); - if (inst->operands[0].za_tile_vector.index.imm + if (inst->operands[0].indexed_za.index.imm != inst->operands[1].addr.offset.imm) { if (mismatch_detail) @@ -3556,11 +3556,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s%s[%s, %s]%s", opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "", style_reg (styler, "za%d%c.%s", - opnd->za_tile_vector.regno, - opnd->za_tile_vector.v == 1 ? 'v' : 'h', + opnd->indexed_za.regno, + opnd->indexed_za.v == 1 ? 'v' : 'h', aarch64_get_qualifier_name (opnd->qualifier)), - style_reg (styler, "w%d", opnd->za_tile_vector.index.regno), - style_imm (styler, "%d", opnd->za_tile_vector.index.imm), + style_reg (styler, "w%d", opnd->indexed_za.index.regno), + style_imm (styler, "%d", opnd->indexed_za.index.imm), opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : ""); break; @@ -3571,8 +3571,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_ZA_array: snprintf (buf, size, "%s[%s, %s]", style_reg (styler, "za"), - style_reg (styler, "w%d", opnd->za_tile_vector.index.regno), - style_imm (styler, "%d", opnd->za_tile_vector.index.imm)); + style_reg (styler, "w%d", opnd->indexed_za.index.regno), + style_imm (styler, "%d", opnd->indexed_za.index.imm)); break; case AARCH64_OPND_SME_SM_ZA: @@ -3582,10 +3582,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SME_PnT_Wm_imm: snprintf (buf, size, "%s[%s, %s]", - style_reg (styler, "p%d.%s", opnd->za_tile_vector.regno, + style_reg (styler, "p%d.%s", opnd->indexed_za.regno, aarch64_get_qualifier_name (opnd->qualifier)), - style_reg (styler, "w%d", opnd->za_tile_vector.index.regno), - style_imm (styler, "%d", opnd->za_tile_vector.index.imm)); + style_reg (styler, "w%d", opnd->indexed_za.index.regno), + style_imm (styler, "%d", opnd->indexed_za.index.imm)); break; case AARCH64_OPND_CRn: