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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id oz31-20020a1709077d9f00b007c0b03b23b5si12935046ejc.542.2022.12.27.20.07.33 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Dec 2022 20:07:33 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B6448385840A for ; Wed, 28 Dec 2022 04:07:30 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTP id 05D1F3858D37 for ; Wed, 28 Dec 2022 04:07:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 05D1F3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [125.65.12.117]) by APP-05 (Coremail) with SMTP id zQCowADHze31wKtjIr6nCQ--.37475S2; Wed, 28 Dec 2022 12:07:18 +0800 (CST) From: shihua@iscas.ac.cn To: binutils@sourceware.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, lazyparser@gmail.com, jiawei@iscas.ac.cn, Liao Shihua Subject: [RFC] Support RV64-ILP32 Date: Wed, 28 Dec 2022 12:06:49 +0800 Message-Id: <20221228040649.810-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.0.windows.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowADHze31wKtjIr6nCQ--.37475S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZF17Zw1kJr1rtr4UJF4xZwb_yoWruryrpF WFkrZxAF4vvFyfJ3y7ArWxGw15K340k345tF1Fk39rA3Z8Z3yrWrs5Jw1Sk345WFy8WF12 vFy3Gr13ZFWDAa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvS14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j 6r4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26F 4UJVW0owAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwAKzVCY07xG64k0 F24lc2xSY4AK67AK6r45MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI 8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AK xVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI 8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280 aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43 ZEXa7VUjkpnPUUUUU== X-Originating-IP: [125.65.12.117] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiBwAOEWOrshsjZAAAs+ X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1753428983546776621?= X-GMAIL-MSGID: =?utf-8?q?1753429262421705258?= From: Liao Shihua This is an imperfect patch and is only used to verify the relevant patches of gcc I haven't designed the new tuple and check it in cpu-riscv.c, yet. So I canceled a check in elfnn-riscv.c. The gcc patch is bfd/ChangeLog: * elfnn-riscv.c (riscv_merge_arch_attr_info):Remove the constraint between RV64 and ILP32. gas/ChangeLog: * config/tc-riscv.c (riscv_set_abi_by_arch): Remove the constraint between RV64 and ILP32. (riscv_target_format):use abi_xlen instead of xlen (md_begin):Likewise (normalize_constant_expr):Likewise (load_const):Likewise (macro):Likewise (s_riscv_attribute):Likewise --- bfd/elfnn-riscv.c | 9 +-------- gas/config/tc-riscv.c | 22 ++++++++++------------ 2 files changed, 11 insertions(+), 20 deletions(-) diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c index 3d2ddf4e651..c4e635c31f7 100644 --- a/bfd/elfnn-riscv.c +++ b/bfd/elfnn-riscv.c @@ -3596,15 +3596,8 @@ riscv_merge_arch_attr_info (bfd *ibfd, char *in_arch, char *out_arch) return NULL; } - if (xlen_in != ARCH_SIZE) - { - _bfd_error_handler - (_("error: %pB: unsupported XLEN (%u), you might be " - "using wrong emulation"), ibfd, xlen_in); - return NULL; - } - merged_arch_str = riscv_arch_str (ARCH_SIZE, &merged_subsets); + merged_arch_str = riscv_arch_str (xlen_in, &merged_subsets); /* Release the subset lists. */ riscv_release_subset_list (&in_subsets); diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 22385d1baa0..e64fd688139 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -353,8 +353,6 @@ riscv_set_abi_by_arch (void) gas_assert (abi_xlen != 0 && xlen != 0 && float_abi != FLOAT_ABI_DEFAULT); if (abi_xlen > xlen) as_bad ("can't have %d-bit ABI on %d-bit ISA", abi_xlen, xlen); - else if (abi_xlen < xlen) - as_bad ("%d-bit ABI not yet supported on %d-bit ISA", abi_xlen, xlen); if (riscv_subset_supports (&riscv_rps_as, "e") && !rve_abi) as_bad ("only the ilp32e ABI is supported for e extension"); @@ -614,9 +612,9 @@ const char * riscv_target_format (void) { if (target_big_endian) - return xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; + return abi_xlen == 64 ? "elf64-bigriscv" : "elf32-bigriscv"; else - return xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; + return abi_xlen == 64 ? "elf64-littleriscv" : "elf32-littleriscv"; } /* Return the length of instruction INSN. */ @@ -1370,7 +1368,7 @@ init_opcode_hash (const struct riscv_opcode *opcodes, void md_begin (void) { - unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; + unsigned long mach = abi_xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach)) as_warn (_("could not set architecture and machine")); @@ -1618,7 +1616,7 @@ md_assemblef (const char *format, ...) static void normalize_constant_expr (expressionS *ex) { - if (xlen > 32) + if (abi_xlen > 32) return; if ((ex->X_op == O_constant || ex->X_op == O_symbol) && IS_ZEXT_32BIT_NUM (ex->X_add_number)) @@ -1716,7 +1714,7 @@ load_const (int reg, expressionS *ep) return; } - if (xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) + if (abi_xlen > 32 && !IS_SEXT_32BIT_NUM (ep->X_add_number)) { /* Reduce to a signed 32-bit constant using SLLI and ADDI. */ while (((upper.X_add_number >> shift) & 1) == 0) @@ -1979,19 +1977,19 @@ macro (struct riscv_cl_insn *ip, expressionS *imm_expr, break; case M_ZEXTH: - riscv_ext (rd, rs1, xlen - 16, false); + riscv_ext (rd, rs1, abi_xlen - 16, false); break; case M_ZEXTW: - riscv_ext (rd, rs1, xlen - 32, false); + riscv_ext (rd, rs1, abi_xlen - 32, false); break; case M_SEXTB: - riscv_ext (rd, rs1, xlen - 8, true); + riscv_ext (rd, rs1, abi_xlen - 8, true); break; case M_SEXTH: - riscv_ext (rd, rs1, xlen - 16, true); + riscv_ext (rd, rs1, abi_xlen - 16, true); break; case M_VMSGE: @@ -4648,7 +4646,7 @@ s_riscv_attribute (int ignored ATTRIBUTE_UNUSED) if (old_xlen != xlen) { /* We must re-init bfd again if xlen is changed. */ - unsigned long mach = xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; + unsigned long mach = abi_xlen == 64 ? bfd_mach_riscv64 : bfd_mach_riscv32; bfd_find_target (riscv_target_format (), stdoutput); if (! bfd_set_arch_mach (stdoutput, bfd_arch_riscv, mach))