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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id du1-20020a17090772c100b0078dcddc1b8csi5764297ejc.788.2022.10.30.20.09.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 20:09:40 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=gaX23tie; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 929103853835 for ; Mon, 31 Oct 2022 03:08:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 929103853835 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1667185706; bh=MS/u46y3KmZKNce5b/qvU7qFfi7YeiDxtQdDL6BwAbk=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=gaX23tieOGj1hSuqGokx14AZGs0BivZH+L6x+Z8v3MbSTkMtjzR2bDic/dnGXGHm5 OdvL6nc34fchNUC20zBUavrMVLFbcQWNHC5dMJ47BUbUhUDFw8UckRs6iELZcRcc6s U8KE5tcQl6t+Rla5gG8qo4/KXNLrMXmUXxk6/HCA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id F22F0385782F for ; Mon, 31 Oct 2022 03:07:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F22F0385782F X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="309893280" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="309893280" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Oct 2022 20:07:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10516"; a="702363178" X-IronPort-AV: E=Sophos;i="5.95,227,1661842800"; d="scan'208";a="702363178" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga004.fm.intel.com with ESMTP; 30 Oct 2022 20:07:11 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 0E60710056C9; Mon, 31 Oct 2022 11:07:10 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH 5/6] Support Intel WRMSRNS Date: Mon, 31 Oct 2022 11:05:06 +0800 Message-Id: <20221031030507.35588-6-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221031030507.35588-1-haochen.jiang@intel.com> References: <20221031030507.35588-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: "Hu, Lin1" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748170997412267444?= X-GMAIL-MSGID: =?utf-8?q?1748170997412267444?= From: "Hu, Lin1" gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/wrmsrns-intel.d | 5 + gas/testsuite/gas/i386/wrmsrns.d | 12 + gas/testsuite/gas/i386/wrmsrns.s | 8 + gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 5 + gas/testsuite/gas/i386/x86-64-wrmsrns.d | 5 + opcodes/i386-dis.c | 7 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 7839 +++++++++-------- 15 files changed, 4257 insertions(+), 4162 deletions(-) create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.s create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d diff --git a/gas/NEWS b/gas/NEWS index 7cdd429f0b..c448ec7861 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel WRMSRNS instructions. + * Add support for Intel CMPccXADD instructions. * Add support for Intel AVX-VNNI-INT8 instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 99d1a4cfec..d387f93ea0 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), + SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index f98b9fbd9f..47aa02b334 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -198,6 +198,7 @@ accept various extension mnemonics. For example, @code{avx_ifma}, @code{avx_vnni_int8}, @code{cmpccxadd}, +@code{wrmsrns}, @code{amx_int8}, @code{amx_bf16}, @code{amx_fp16}, @@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} -@item @samp{.cmpccxadd} +@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index e9785e64fd..d3797937a7 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -480,6 +480,8 @@ if [gas_32_check] then { run_dump_test "avx-vnni-int8" run_dump_test "avx-vnni-int8-intel" run_list_test "cmpccxadd-inval" + run_dump_test "wrmsrns" + run_dump_test "wrmsrns-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1155,6 +1157,8 @@ if [gas_64_check] then { run_dump_test "x86-64-avx-vnni-int8-intel" run_dump_test "x86-64-cmpccxadd" run_dump_test "x86-64-cmpccxadd-intel" + run_dump_test "x86-64-wrmsrns" + run_dump_test "x86-64-wrmsrns-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d new file mode 100644 index 0000000000..b3be2609d8 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns-intel.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw -Mintel +#name: i386 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d new file mode 100644 index 0000000000..e804adc501 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw +#name: i386 WRMSRNS insns +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s new file mode 100644 index 0000000000..a450b0536d --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.s @@ -0,0 +1,8 @@ +# Check WRMSRNS instructions + + .text +_start: + wrmsrns #WRMSRNS + +.intel_syntax noprefix + wrmsrns #WRMSRNS diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d new file mode 100644 index 0000000000..ff80e55b7c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d new file mode 100644 index 0000000000..047f0a1a7d --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d @@ -0,0 +1,5 @@ +#as: +#objdump: -dw +#name: x86_64 WRMSRNS insns +#source: wrmsrns.s +#dump: wrmsrns.d diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 116450c871..fb1c14b5b5 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -985,6 +985,7 @@ enum enum { PREFIX_90 = 0, + PREFIX_0F01_REG_0_MOD_3_RM_6, PREFIX_0F01_REG_1_RM_4, PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, @@ -2954,6 +2955,11 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ + { + { "wrmsrns", { Skip_MODRM }, 0 }, + }, + /* PREFIX_0F01_REG_1_RM_4 */ { { Bad_Opcode }, @@ -8634,6 +8640,7 @@ static const struct dis386 rm_table[][8] = { { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, { "pconfig", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, }, { /* RM_0F01_REG_1 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 55ed659d3d..a6dc8b904e 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" }, { "CPU_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -457,6 +459,8 @@ static initializer cpu_flag_init[] = "CpuAVX_VNNI_INT8" }, { "CPU_ANY_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_ANY_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, }; static initializer operand_type_init[] = @@ -662,6 +666,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_IFMA), BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuCMPCCXADD), + BITFIELD (CpuWRMSRNS), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 3b9572e2af..f00babfce2 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -217,6 +217,8 @@ enum CpuAVX_VNNI_INT8, /* Intel CMPccXADD instructions support required. */ CpuCMPCCXADD, + /* Intel WRMSRNS Instructions support required */ + CpuWRMSRNS, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -402,6 +404,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_ifma:1; unsigned int cpuavx_vnni_int8:1; unsigned int cpucmpccxadd:1; + unsigned int cpuwrmsrns:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 5fe9cb053f..3e947cd248 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3295,3 +3295,9 @@ prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No cmpxadd, 0x66e, None, CpuCMPCCXADD|Cpu64, Modrm|Vex|Space0F38|VexVVVV|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. + +// WRMSRNS instruction. + +wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// WRMSRNS instruction end.