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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m15-20020a1709060d8f00b0073db9474d06si13167595eji.325.2022.10.19.08.22.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 08:22:31 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=jjHJKOmb; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D7DD538515E2 for ; Wed, 19 Oct 2022 15:20:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D7DD538515E2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666192814; bh=6/xJVBLpl1Q0TmBOjTGcn8rt/IXvQbMjku0cH2Kxe2k=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=jjHJKOmb6lhaVOdwUz6ROwJrm9JmkR47aNFTqY/MxdgyRWysdCs4BIsmI2j+fd7fD lC1UstMPF3m4eowGgFDrPnxP3R6a+hMiLf6ZUPDJALuEDX7eGqOaPKyZb1iEc6k5Zl iwNiHz+rb8n9mvcBIcIH4Q/FY96yoPyPp/fkOkIU= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 9F352385800F for ; Wed, 19 Oct 2022 15:17:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 9F352385800F X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="304056033" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="304056033" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 08:17:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="692434880" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="692434880" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 08:17:41 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 113A81007822; Wed, 19 Oct 2022 23:17:37 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH 08/10] Support Intel MSRLIST Date: Wed, 19 Oct 2022 23:15:32 +0800 Message-Id: <20221019151534.45521-9-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com> References: <20221019151534.45521-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: "Hu, Lin1" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129939902520290?= X-GMAIL-MSGID: =?utf-8?q?1747129939902520290?= From: "Hu, Lin1" gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 2 + gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/msrlist-inval.l | 3 + gas/testsuite/gas/i386/msrlist-inval.s | 7 + gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 14 + gas/testsuite/gas/i386/x86-64-msrlist.d | 14 + gas/testsuite/gas/i386/x86-64-msrlist.s | 11 + opcodes/i386-dis.c | 17 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 516 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7872 +++++++++-------- 15 files changed, 4305 insertions(+), 4172 deletions(-) create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s diff --git a/gas/NEWS b/gas/NEWS index 2d745dfc31..3246e7e825 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel MSRLIST instructions. + * Add support for Intel WRMSRNS instructions. * Add support for Intel RAO-INT instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index a332889f71..c9432e4188 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] = SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), SUBARCH (raoint, RAOINT, ANY_RAOINT, false), SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), + SUBARCH (msrlist, MSRLIST, MSRLIST, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index d8376566be..49582b29a6 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -200,6 +200,7 @@ accept various extension mnemonics. For example, @code{cmpccxadd}, @code{raoint}, @code{wrmsrns}, +@code{msrlist}, @code{amx_int8}, @code{amx_bf16}, @code{amx_tile}, @@ -1494,6 +1495,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} @item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns} +@item @samp{.msrlist} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index c924075180..5da64b4076 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -490,6 +490,7 @@ if [gas_32_check] then { run_dump_test "raoint-intel" run_dump_test "wrmsrns" run_dump_test "wrmsrns-intel" + run_list_test "msrlist-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1170,6 +1171,8 @@ if [gas_64_check] then { run_dump_test "x86-64-raoint-intel" run_dump_test "x86-64-wrmsrns" run_dump_test "x86-64-wrmsrns-intel" + run_dump_test "x86-64-msrlist" + run_dump_test "x86-64-msrlist-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l new file mode 100644 index 0000000000..456f41c38f --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `rdmsrlist' is only supported in 64-bit mode +.*:7: Error: `wrmsrlist' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s new file mode 100644 index 0000000000..3c3258a375 --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.s @@ -0,0 +1,7 @@ +# Check Illegal MSRLIST instructions + + .allow_index_reg + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d new file mode 100644 index 0000000000..97a2a60e43 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 MSRLIST insns (Intel disassembly) +#source: x86-64-msrlist.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d new file mode 100644 index 0000000000..64beed7aa3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw +#name: x86_64 MSRLIST insns +#source: x86-64-msrlist.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s new file mode 100644 index 0000000000..ad57451da9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.s @@ -0,0 +1,11 @@ +# Check 64bit MSRLIST instructions + + .allow_index_reg + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST + +.intel_syntax noprefix + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 064a1bc0ce..0aa41bd5fb 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1281,6 +1281,8 @@ enum X86_64_E9, X86_64_EA, X86_64_0F01_REG_0, + X86_64_0F01_REG_0_MOD_3_RM_6_P_1, + X86_64_0F01_REG_0_MOD_3_RM_6_P_3, X86_64_0F01_REG_1, X86_64_0F01_REG_1_RM_5_PREFIX_2, X86_64_0F01_REG_1_RM_6_PREFIX_2, @@ -2974,6 +2976,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ { { "wrmsrns", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, }, /* PREFIX_0F01_REG_1_RM_4 */ @@ -4315,6 +4320,18 @@ static const struct dis386 x86_64_table[][2] = { { "sgdt", { M }, 0 }, }, + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ + { + { Bad_Opcode }, + { "wrmsrlist", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ + { + { Bad_Opcode }, + { "rdmsrlist", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_1 */ { { "sidt{Q|Q}", { M }, 0 }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 0bfccdc7af..435d67711f 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -257,6 +257,8 @@ static initializer cpu_flag_init[] = "CpuRAOINT" }, { "CPU_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_MSRLIST_FLAGS", + "CpuMSRLIST" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -463,6 +465,8 @@ static initializer cpu_flag_init[] = "CpuRAOINT" }, { "CPU_ANY_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_ANY_MSRLIST_FLAGS", + "CpuMSRLIST" }, }; static initializer operand_type_init[] = @@ -670,6 +674,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuCMPCCXADD), BITFIELD (CpuRAOINT), BITFIELD (CpuWRMSRNS), + BITFIELD (CpuMSRLIST), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 90e0591ae2..75c23aaec6 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -221,6 +221,8 @@ enum CpuRAOINT, /* Intel WRMSRNS Instructions support required */ CpuWRMSRNS, + /* Intel MSRLIST Instructions support required. */ + CpuMSRLIST, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -406,6 +408,7 @@ typedef union i386_cpu_flags unsigned int cpucmpccxadd:1; unsigned int cpuraoint:1; unsigned int cpuwrmsrns:1; + unsigned int cpumsrlist:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index bff32e69c2..42d6423942 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3317,3 +3317,10 @@ axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_l wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // WRMSRNS instruction end. + +// MSRLIST instructions. + +rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} +wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// MSRLIST instructions end.