From patchwork Wed Oct 19 15:15:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 5681 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp385251wrs; Wed, 19 Oct 2022 08:22:09 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7ugek/3hvZ/1PalgJ+SrGsDDAHDKR/L5T4M7FyQZ/jgaAe+K7pXRrTCBq9ZqxGuuC1v/Zd X-Received: by 2002:a05:6402:4301:b0:45d:422b:5d5d with SMTP id m1-20020a056402430100b0045d422b5d5dmr7780705edc.153.1666192929402; Wed, 19 Oct 2022 08:22:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192929; cv=none; d=google.com; s=arc-20160816; b=KQ90vAOaGEgDeecIdUt0kROT82PL0mzVqQWIFq3wS/8mGxdq4RSgHBTqXWhh+e3oYk UUkPALzPLzaFAt1DZB0eLqzUnw6cUSaGKMKequn924sl7AxPTtQaHQ1k5a8ciZzteCD/ CiXCIBbKtBf6unsK9r1tTEWfg3YT8e01LAJtzc7CRZB8ZyrtUrOR3zUAWFvVLtJELLvF L5+wXuMB4q+lM9N5OD+ZrEsSWtVyh/FhRuSgdJNrM1tfJbt7KJODa5jY9nrI/NuVTkOl 6Y4yYPytDTgpgBhhgWY7UyguDfetwxcLcRSjYXZgRKGRj+wS5IXTdT3PpoiAcx0z78XM dHgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:reply-to:from:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :references:in-reply-to:message-id:date:subject:to:dmarc-filter :delivered-to:dkim-signature:dkim-filter; bh=Ps34EwLbHNORaGb8sLfC7LXEGSJ9lIdvs8U63PUVlZA=; b=sQtnNdq2B+J+3++pQdKEEYt61rMMWyqY//kVmj/eh8ZKYDOMYY8WkivocMfv5xg66m ZfFBEws7IduSK2Ml2HigdRFNy6yEtijjXGOyllEJ6fOVoEPZQgA5NUbB1G7iFSseABhf khyoCGSORmVJKNeGWBtrL8qoxH55lnBD17iw8FRCmLf4ZWvFxl0zxDBA6fCPPJPdrBLk 4SLmSgUE527F2wTJxg3DmDo2vHFK3SmoWujAM6Wja3c+NujLRJK/7dR7f/46Pj1hArk/ AqfN0fsAgITqCPqZ/I6t40AdY0IBDa0AWg4M/HKCI1gmss00j4txA0AZkF8wSvwBE0lf 1Mfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Jwh6+8Zy; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id q4-20020a50aa84000000b00458b87a0919si13603223edc.114.2022.10.19.08.22.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 08:22:09 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Jwh6+8Zy; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7E4163851C23 for ; Wed, 19 Oct 2022 15:19:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7E4163851C23 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666192798; bh=Ps34EwLbHNORaGb8sLfC7LXEGSJ9lIdvs8U63PUVlZA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Jwh6+8Zya4FTAC0ibwcjP8+JFlJ0oUpD/gDwFICGc1kxHSCQNxAXzPwVA+LZzpZkW BaizyWuodzVPoGf8fI+F2eCe7cQISkn5Ravsf+0Div3iAF38VCJYJ8QSyZz2Kj3BsU LqJgc0Jtao08vaKhS1owAhx+AminrLD5eJRGxle4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 395563857B9B for ; Wed, 19 Oct 2022 15:17:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 395563857B9B X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="304056023" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="304056023" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 08:17:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="692434875" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="692434875" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga008.fm.intel.com with ESMTP; 19 Oct 2022 08:17:41 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C73D31007813; Wed, 19 Oct 2022 23:17:36 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH 07/10] Support Intel WRMSRNS Date: Wed, 19 Oct 2022 23:15:31 +0800 Message-Id: <20221019151534.45521-8-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221019151534.45521-1-haochen.jiang@intel.com> References: <20221019151534.45521-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: "Hu, Lin1" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129917390724606?= X-GMAIL-MSGID: =?utf-8?q?1747129917390724606?= From: "Hu, Lin1" gas/ChangeLog: * NEWS: Support Intel WRMSRNS. * config/tc-i386.c: Add wrmsrns. * doc/c-i386.texi: Document .wrmsrns. * testsuite/gas/i386/i386.exp: Add WRMSRNS tests. * testsuite/gas/i386/wrmsrns-intel.d: New test. * testsuite/gas/i386/wrmsrns.d: Ditto. * testsuite/gas/i386/wrmsrns.s: Ditto. * testsuite/gas/i386/x86-64-wrmsrns-intel.d: Ditto. * testsuite/gas/i386/x86-64-wrmsrns.d: Ditto. opcodes/ChangeLog: * i386-dis.c (PREFIX_0F01_REG_0_MOD_3_RM_6): New. (prefix_table): Add PREFIX_0F01_REG_0_MOD_3_RM_6. (rm_table): New entry for wrmsrns. * i386-gen.c (cpu_flag_init): Add CPU_WRMSRNS_FLAGS and CPU_ANY_WRMSRNS_FLAGS. (cpu_flags): Add CpuWRMSRNS. * i386-init.h: Regenerated. * i386-opc.h (CpuWRMSRNS): New. (i386_cpu_flags): Add cpuwrmsrns. * i386-opc.tbl: Add WRMSRNS instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/wrmsrns-intel.d | 12 + gas/testsuite/gas/i386/wrmsrns.d | 12 + gas/testsuite/gas/i386/wrmsrns.s | 8 + gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d | 12 + gas/testsuite/gas/i386/x86-64-wrmsrns.d | 12 + opcodes/i386-dis.c | 7 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 6 + opcodes/i386-tbl.h | 7859 +++++++++-------- 15 files changed, 4288 insertions(+), 4172 deletions(-) create mode 100644 gas/testsuite/gas/i386/wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.d create mode 100644 gas/testsuite/gas/i386/wrmsrns.s create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-wrmsrns.d diff --git a/gas/NEWS b/gas/NEWS index f352c5ab89..2d745dfc31 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel WRMSRNS instructions. + * Add support for Intel RAO-INT instructions. * Add support for Intel CMPccXADD instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 0ca9b43610..a332889f71 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1099,6 +1099,7 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), SUBARCH (cmpccxadd, CMPCCXADD, CMPCCXADD, false), SUBARCH (raoint, RAOINT, ANY_RAOINT, false), + SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index e15cf7a7aa..d8376566be 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -199,6 +199,7 @@ accept various extension mnemonics. For example, @code{avx_ne_convert}, @code{cmpccxadd}, @code{raoint}, +@code{wrmsrns}, @code{amx_int8}, @code{amx_bf16}, @code{amx_tile}, @@ -1492,7 +1493,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} -@item @samp{.cmpccxadd} @tab @samp{.raoint} +@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index 1eb0eabb6b..c924075180 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -488,6 +488,8 @@ if [gas_32_check] then { run_list_test "cmpccxadd-inval" run_dump_test "raoint" run_dump_test "raoint-intel" + run_dump_test "wrmsrns" + run_dump_test "wrmsrns-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1166,6 +1168,8 @@ if [gas_64_check] then { run_dump_test "x86-64-cmpccxadd-intel" run_dump_test "x86-64-raoint" run_dump_test "x86-64-raoint-intel" + run_dump_test "x86-64-wrmsrns" + run_dump_test "x86-64-wrmsrns-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/wrmsrns-intel.d b/gas/testsuite/gas/i386/wrmsrns-intel.d new file mode 100644 index 0000000000..83194511a5 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns-intel.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw -Mintel +#name: i386 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/gas/testsuite/gas/i386/wrmsrns.d b/gas/testsuite/gas/i386/wrmsrns.d new file mode 100644 index 0000000000..e804adc501 --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw +#name: i386 WRMSRNS insns +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/gas/testsuite/gas/i386/wrmsrns.s b/gas/testsuite/gas/i386/wrmsrns.s new file mode 100644 index 0000000000..a450b0536d --- /dev/null +++ b/gas/testsuite/gas/i386/wrmsrns.s @@ -0,0 +1,8 @@ +# Check WRMSRNS instructions + + .text +_start: + wrmsrns #WRMSRNS + +.intel_syntax noprefix + wrmsrns #WRMSRNS diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d new file mode 100644 index 0000000000..2f789ed5df --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns-intel.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 WRMSRNS insns (Intel disassembly) +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/gas/testsuite/gas/i386/x86-64-wrmsrns.d b/gas/testsuite/gas/i386/x86-64-wrmsrns.d new file mode 100644 index 0000000000..b8535c266a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-wrmsrns.d @@ -0,0 +1,12 @@ +#as: +#objdump: -dw +#name: x86_64 WRMSRNS insns +#source: wrmsrns.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns +\s*[a-f0-9]+:\s*0f 01 c6\s+wrmsrns diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 3a990e4e63..064a1bc0ce 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1000,6 +1000,7 @@ enum enum { PREFIX_90 = 0, + PREFIX_0F01_REG_0_MOD_3_RM_6, PREFIX_0F01_REG_1_RM_4, PREFIX_0F01_REG_1_RM_5, PREFIX_0F01_REG_1_RM_6, @@ -2970,6 +2971,11 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ + { + { "wrmsrns", { Skip_MODRM }, 0 }, + }, + /* PREFIX_0F01_REG_1_RM_4 */ { { Bad_Opcode }, @@ -8733,6 +8739,7 @@ static const struct dis386 rm_table[][8] = { { "vmresume", { Skip_MODRM }, 0 }, { "vmxoff", { Skip_MODRM }, 0 }, { "pconfig", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, }, { /* RM_0F01_REG_1 */ diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5d75646c7e..0bfccdc7af 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -255,6 +255,8 @@ static initializer cpu_flag_init[] = "CpuCMPCCXADD" }, { "CPU_RAOINT_FLAGS", "CpuRAOINT" }, + { "CPU_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -459,6 +461,8 @@ static initializer cpu_flag_init[] = "CpuCMPCCXADD" }, { "CPU_ANY_RAOINT_FLAGS", "CpuRAOINT" }, + { "CPU_ANY_WRMSRNS_FLAGS", + "CpuWRMSRNS" }, }; static initializer operand_type_init[] = @@ -665,6 +669,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_NE_CONVERT), BITFIELD (CpuCMPCCXADD), BITFIELD (CpuRAOINT), + BITFIELD (CpuWRMSRNS), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index cb6c372203..90e0591ae2 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -219,6 +219,8 @@ enum CpuCMPCCXADD, /* Intel RAO INT Instructions support required. */ CpuRAOINT, + /* Intel WRMSRNS Instructions support required */ + CpuWRMSRNS, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -403,6 +405,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_ne_convert:1; unsigned int cpucmpccxadd:1; unsigned int cpuraoint:1; + unsigned int cpuwrmsrns:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index dacafe1e14..bff32e69c2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3311,3 +3311,9 @@ aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ld axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} // RAOINT instructions end. + +// WRMSRNS instruction. + +wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// WRMSRNS instruction end.