On 19.10.2022 17:15, Haochen Jiang wrote:
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> };
>
> #undef SUBARCH
> @@ -4522,7 +4523,8 @@ load_insn_p (void)
> {
> /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
> + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> + prefetchit1. */
> if (i.tm.opcode_modifier.anysize)
> return 0;
>
There's still no change in this file making sure that the new insns are
_only_ accepted with RIP-relative addressing. See my earlier comments.
Jan
> On 19.10.2022 17:15, Haochen Jiang wrote:
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
> > SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
> > SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
> > SUBARCH (msrlist, MSRLIST, MSRLIST, false),
> > + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
> > };
> >
> > #undef SUBARCH
> > @@ -4522,7 +4523,8 @@ load_insn_p (void)
> > {
> > /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
> > prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
> > - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
> > + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
> > + prefetchit1. */
> > if (i.tm.opcode_modifier.anysize)
> > return 0;
> >
>
> There's still no change in this file making sure that the new insns are _only_
> accepted with RIP-relative addressing. See my earlier comments.
>
Hi Jan,
I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.
Lili.
> Jan
On 25.10.2022 09:49, Cui, Lili wrote:
>> On 19.10.2022 17:15, Haochen Jiang wrote:
>>> --- a/gas/config/tc-i386.c
>>> +++ b/gas/config/tc-i386.c
>>> @@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
>>> SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
>>> SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
>>> SUBARCH (msrlist, MSRLIST, MSRLIST, false),
>>> + SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
>>> };
>>>
>>> #undef SUBARCH
>>> @@ -4522,7 +4523,8 @@ load_insn_p (void)
>>> {
>>> /* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
>>> prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
>>> - bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
>>> + bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
>>> + prefetchit1. */
>>> if (i.tm.opcode_modifier.anysize)
>>> return 0;
>>>
>>
>> There's still no change in this file making sure that the new insns are _only_
>> accepted with RIP-relative addressing. See my earlier comments.
>>
> I'll modify the patch based on your previous comments, do you agree with adding a warning instead of an error for illegal input for assembler. Because it doesn't cause hardware errors.
Personally I think a warning is too little, but if H.J. agrees with you,
then so be it.
Jan
@@ -1,5 +1,7 @@
-*- text -*-
+* Add support for Intel PREFETCHI instructions.
+
* Add support for Intel AMX-FP16 instructions.
* Add support for Intel MSRLIST instructions.
@@ -1102,6 +1102,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (raoint, RAOINT, ANY_RAOINT, false),
SUBARCH (wrmsrns, WRMSRNS, WRMSRNS, false),
SUBARCH (msrlist, MSRLIST, MSRLIST, false),
+ SUBARCH (prefetchi, PREFETCHI, ANY_PREFETCHI, false),
};
#undef SUBARCH
@@ -4522,7 +4523,8 @@ load_insn_p (void)
{
/* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
- bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
+ bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote, prefetchit0
+ prefetchit1. */
if (i.tm.opcode_modifier.anysize)
return 0;
@@ -201,6 +201,7 @@ accept various extension mnemonics. For example,
@code{raoint},
@code{wrmsrns},
@code{msrlist},
+@code{prefetchi},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1496,7 +1497,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
@item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns}
-@item @samp{.msrlist}
+@item @samp{.msrlist} @tab @samp{.prefetchi}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
@@ -1209,6 +1209,9 @@ if [gas_64_check] then {
run_dump_test "x86-64-tdx"
run_dump_test "x86-64-tsxldtrk"
run_dump_test "x86-64-hreset"
+ run_dump_test "x86-64-prefetchi"
+ run_dump_test "x86-64-prefetchi-intel"
+ run_dump_test "x86-64-prefetchi-inval-register"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
@@ -33,6 +33,8 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+ +[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+ +[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
@@ -20,6 +20,8 @@ _start:
prefetcht1 (%rbp)
prefetcht2 (%rbp)
prefetchw (%rbp)
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
pop %fs
popf
xlatb (%rbx)
new file mode 100644
@@ -0,0 +1,16 @@
+#as:
+#objdump: -dwMintel
+#name: x86-64 PREFETCHI insns (Intel disassembly)
+#source: x86-64-prefetchi.s
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
new file mode 100644
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI INVAL REGISTER insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <\.text>:
+[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\)
+[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\)
+#pass
new file mode 100644
@@ -0,0 +1,9 @@
+.text
+ #prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x39
+ #prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
+ .byte 0x0f
+ .byte 0x18
+ .byte 0x31
new file mode 100644
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86-64 PREFETCHI insns
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+#pass
new file mode 100644
@@ -0,0 +1,14 @@
+# Check 64bit PREFETCHI instructions
+
+ .allow_index_reg
+ .text
+_start:
+
+ prefetchit0 0x12345678(%rip)
+ prefetchit1 0x12345678(%rip)
+
+ .intel_syntax noprefix
+
+ prefetchit0 BYTE PTR [rip+0x12345678]
+ prefetchit1 BYTE PTR [rip+0x12345678]
+
@@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
static void MOVSXD_Fixup (instr_info *, int, int);
static void DistinctDest_Fixup (instr_info *, int, int);
+static void PREFETCHI_Fixup (instr_info *, int, int);
/* This character is used to encode style information within the output
buffers. See oappend_insert_style for more details. */
@@ -841,6 +842,8 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
+ MOD_0F18_REG_6,
+ MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
@@ -1297,6 +1300,8 @@ enum
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
+ X86_64_MOD_0F18_REG_6,
+ X86_64_MOD_0F18_REG_7,
X86_64_0F24,
X86_64_0F26,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -2768,8 +2773,8 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_3) },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
- { "nopQ", { Ev }, 0 },
+ { MOD_TABLE (MOD_0F18_REG_6) },
+ { MOD_TABLE (MOD_0F18_REG_7) },
},
/* REG_0F1C_P_0_MOD_0 */
{
@@ -4414,6 +4419,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "psmash", { Skip_MODRM }, 0 },
},
+ /* X86_64_MOD_0F18_REG_6 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
+ /* X86_64_MOD_0F18_REG_7 */
+ {
+ { "nopQ", { Ev }, 0 },
+ { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
+ },
+
{
/* X86_64_0F24 */
{ "movZ", { Em, Td }, 0 },
@@ -8213,6 +8230,16 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
+ {
+ /* MOD_0F18_REG_6 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_6) },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F18_REG_7 */
+ { X86_64_TABLE (X86_64_MOD_0F18_REG_7) },
+ { "nopQ", { Ev }, 0 },
+ },
{
/* MOD_0F1A_PREFIX_0 */
{ "bndldx", { Gbnd, Mv_bnd }, 0 },
@@ -14028,3 +14055,18 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
oappend (ins, "sae}");
}
+
+static void
+PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
+{
+ if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
+ {
+ if (ins->intel_syntax)
+ ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
+ else
+ ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
+ bytemode = v_mode;
+ }
+
+ OP_M (ins, bytemode, sizeflag);
+}
@@ -259,6 +259,8 @@ static initializer cpu_flag_init[] =
"CpuWRMSRNS" },
{ "CPU_MSRLIST_FLAGS",
"CpuMSRLIST" },
+ { "CPU_PREFETCHI_FLAGS",
+ "CpuPREFETCHI"},
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -471,6 +473,8 @@ static initializer cpu_flag_init[] =
"CpuWRMSRNS" },
{ "CPU_ANY_MSRLIST_FLAGS",
"CpuMSRLIST" },
+ { "CPU_ANY_PREFETCHI_FLAGS",
+ "CpuPREFETCHI" },
};
static initializer operand_type_init[] =
@@ -679,6 +683,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuRAOINT),
BITFIELD (CpuWRMSRNS),
BITFIELD (CpuMSRLIST),
+ BITFIELD (CpuPREFETCHI),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
@@ -223,6 +223,8 @@ enum
CpuWRMSRNS,
/* Intel MSRLIST Instructions support required. */
CpuMSRLIST,
+ /* PREFETCHI instruction required */
+ CpuPREFETCHI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -411,6 +413,7 @@ typedef union i386_cpu_flags
unsigned int cpuraoint:1;
unsigned int cpuwrmsrns:1;
unsigned int cpumsrlist:1;
+ unsigned int cpuprefetchi:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
@@ -3325,3 +3325,10 @@ rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|N
wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {}
// MSRLIST instructions end.
+
+// PREFETCHI instructions.
+
+prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
+
+// PREFETCHI instructions end.