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[8.43.85.97]) by mx.google.com with ESMTPS id ji19-20020a170907981300b007823d2b20fdsi1938328ejc.219.2022.10.14.02.17.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 02:17:05 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Af1uwfm2; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AEC93383DB8E for ; Fri, 14 Oct 2022 09:16:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AEC93383DB8E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665738966; bh=u89NRNwQ7lGzH128SOaRMeQw3klCZMlnZvyQlkxYxDM=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Af1uwfm2ipDtaT0mdwik8o+/x4YZfoMnyPi9InPZ+soxnFKato2/+oJ+nOcUILsIj hMO87s1tbMU0uzDt0NvamIaVNVLZ15d5O13EhUA18VlEliYmVHSmjZaJ+8obmj2jFC GRO71HfF7cGyMfW9SB6FDiXEuB6KwKIhswnYrLnQ= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 192233857822 for ; Fri, 14 Oct 2022 09:14:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 192233857822 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="306404319" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="306404319" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 02:14:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="660670268" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="660670268" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga001.jf.intel.com with ESMTP; 14 Oct 2022 02:14:55 -0700 Received: from shliclel314.sh.intel.com (shliclel314.sh.intel.com [10.239.240.214]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9851F100AC5E; Fri, 14 Oct 2022 17:14:50 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH 08/10] Support Intel MSRLIST Date: Fri, 14 Oct 2022 17:12:46 +0800 Message-Id: <20221014091248.4920-9-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20221014091248.4920-1-haochen.jiang@intel.com> References: <20221014091248.4920-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: "Hu, Lin1" Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746653964587200653?= X-GMAIL-MSGID: =?utf-8?q?1746653964587200653?= From: "Hu, Lin1" gas/ChangeLog: * NEWS: Support Intel MSRLIST. * config/tc-i386.c: Add msrlist. * doc/c-i386.texi: Document .msrlist and nomsrlist. * testsuite/gas/i386/i386.exp: Add MSRLIST tests. * testsuite/gas/i386/x86-64-lockbad-1.l: Add msrlist. * testsuite/gas/i386/x86-64-lockbad-1.s: Ditto. * testsuite/gas/i386/msrlist-inval.l: New test. * testsuite/gas/i386/msrlist-inval.s: Ditto. * testsuite/gas/i386/x86-64-msrlist-intel.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.d: Ditto. * testsuite/gas/i386/x86-64-msrlist.s: Ditto. opcodes/ChangeLog: * i386-dis.c (X86_64_0F01_REG_0_MOD_3_RM_6_P_1): New. (X86_64_0F01_REG_0_MOD_3_RM_6_P_3): Ditto. (prefix_table): New entry for msrlist. (x86_64_table): Add X86_64_0F01_REG_0_MOD_3_RM_6_P_1 and X86_64_0F01_REG_0_MOD_3_RM_6_P_3. * i386-gen.c (cpu_flag_init): Add CPU_MSRLIST_FLAGS and CPU_ANY_MSRLIST_FLAGS. * i386-init.h: Regenerated. * i386-opc.h (CpuMSRLIST): New. (i386_cpu_flags): Add cpumsrlist. * i386-opc.tbl: Add MSRLIST instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 1 + gas/doc/c-i386.texi | 3 + gas/testsuite/gas/i386/i386.exp | 3 + gas/testsuite/gas/i386/msrlist-inval.l | 3 + gas/testsuite/gas/i386/msrlist-inval.s | 7 + gas/testsuite/gas/i386/x86-64-lockbad-1.l | 100 +- gas/testsuite/gas/i386/x86-64-lockbad-1.s | 4 + gas/testsuite/gas/i386/x86-64-msrlist-intel.d | 14 + gas/testsuite/gas/i386/x86-64-msrlist.d | 14 + gas/testsuite/gas/i386/x86-64-msrlist.s | 11 + opcodes/i386-dis.c | 17 + opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 516 +- opcodes/i386-opc.h | 3 + opcodes/i386-opc.tbl | 7 + opcodes/i386-tbl.h | 7844 +++++++++-------- 17 files changed, 4350 insertions(+), 4204 deletions(-) create mode 100644 gas/testsuite/gas/i386/msrlist-inval.l create mode 100644 gas/testsuite/gas/i386/msrlist-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.d create mode 100644 gas/testsuite/gas/i386/x86-64-msrlist.s diff --git a/gas/NEWS b/gas/NEWS index 2d745dfc31..3246e7e825 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel MSRLIST instructions. + * Add support for Intel WRMSRNS instructions. * Add support for Intel RAO-INT instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 7f508b2962..981fd9f73d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1100,6 +1100,7 @@ static const arch_entry cpu_arch[] = SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), SUBARCH (raoint, RAOINT, ANY_RAOINT, false), SUBARCH (wrmsrns, WRMSRNS, ANY_WRMSRNS, false), + SUBARCH (msrlist, MSRLIST, ANY_MSRLIST, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index abfbccdfb0..1bf953ef73 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -219,6 +219,7 @@ accept various extension mnemonics. For example, @code{cmpccxadd}, @code{raoint}, @code{wrmsrns}, +@code{msrlist}, @code{noavx512f}, @code{noavx512cd}, @code{noavx512er}, @@ -245,6 +246,7 @@ accept various extension mnemonics. For example, @code{nocmpccxadd}, @code{noraoint}, @code{nowrmsrns}, +@code{nomsrlist}, @code{noenqcmd}, @code{noserialize}, @code{notsxldtrk}, @@ -1547,6 +1549,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} @item @samp{.cmpccxadd} @tab @samp{.raoint} @tab @samp{.wrmsrns} +@item @samp{.msrlist} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index c924075180..5da64b4076 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -490,6 +490,7 @@ if [gas_32_check] then { run_dump_test "raoint-intel" run_dump_test "wrmsrns" run_dump_test "wrmsrns-intel" + run_list_test "msrlist-inval" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1170,6 +1171,8 @@ if [gas_64_check] then { run_dump_test "x86-64-raoint-intel" run_dump_test "x86-64-wrmsrns" run_dump_test "x86-64-wrmsrns-intel" + run_dump_test "x86-64-msrlist" + run_dump_test "x86-64-msrlist-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/msrlist-inval.l b/gas/testsuite/gas/i386/msrlist-inval.l new file mode 100644 index 0000000000..456f41c38f --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.l @@ -0,0 +1,3 @@ +.* Assembler messages: +.*:6: Error: `rdmsrlist' is only supported in 64-bit mode +.*:7: Error: `wrmsrlist' is only supported in 64-bit mode diff --git a/gas/testsuite/gas/i386/msrlist-inval.s b/gas/testsuite/gas/i386/msrlist-inval.s new file mode 100644 index 0000000000..3c3258a375 --- /dev/null +++ b/gas/testsuite/gas/i386/msrlist-inval.s @@ -0,0 +1,7 @@ +# Check Illegal MSRLIST instructions + + .allow_index_reg + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.l b/gas/testsuite/gas/i386/x86-64-lockbad-1.l index 6313e986fd..6469991605 100644 --- a/gas/testsuite/gas/i386/x86-64-lockbad-1.l +++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.l @@ -37,10 +37,10 @@ .*:42: Error: .* .*:43: Error: .* .*:44: Error: .* -.*:47: Error: .* -.*:48: Error: .* +.*:45: Error: .* +.*:46: Error: .* +.*:49: Error: .* .*:50: Error: .* -.*:51: Error: .* .*:52: Error: .* .*:53: Error: .* .*:54: Error: .* @@ -67,14 +67,18 @@ .*:75: Error: .* .*:76: Error: .* .*:77: Error: .* +.*:78: Error: .* .*:79: Error: .* -.*:80: Error: .* .*:81: Error: .* .*:82: Error: .* .*:83: Error: .* .*:84: Error: .* .*:85: Error: .* .*:86: Error: .* +.*:87: Error: .* +.*:88: Error: .* +.*:89: Error: .* +.*:90: Error: .* GAS LISTING .* @@ -122,48 +126,52 @@ GAS LISTING .* [ ]*42[ ]+lock sub \(%rbx\), %eax [ ]*43[ ]+lock xor \(%rbx\), %eax [ ]*44[ ]+lock wrmsrns -[ ]*45[ ]+ -[ ]*46[ ]+\.intel_syntax noprefix -[ ]*47[ ]+lock mov eax,ebx -[ ]*48[ ]+lock mov eax,DWORD PTR \[rbx\] -[ ]*49[ ]+ -[ ]*50[ ]+lock add eax,ebx -[ ]*51[ ]+lock add ebx,0x64 -[ ]*52[ ]+lock adc eax,ebx -[ ]*53[ ]+lock adc ebx,0x64 -[ ]*54[ ]+lock and eax,ebx -[ ]*55[ ]+lock and ebx,0x64 -[ ]*56[ ]+lock btc ebx,eax -[ ]*57[ ]+lock btc ebx,0x64 +[ ]*45[ ]+lock rdmsrlist +[ ]*46[ ]+lock wrmsrlist +[ ]*47[ ]+ +[ ]*48[ ]+\.intel_syntax noprefix +[ ]*49[ ]+lock mov eax,ebx +[ ]*50[ ]+lock mov eax,DWORD PTR \[rbx\] +[ ]*51[ ]+ +[ ]*52[ ]+lock add eax,ebx +[ ]*53[ ]+lock add ebx,0x64 +[ ]*54[ ]+lock adc eax,ebx +[ ]*55[ ]+lock adc ebx,0x64 +[ ]*56[ ]+lock and eax,ebx +[ ]*57[ ]+lock and ebx,0x64 GAS LISTING .* -[ ]*58[ ]+lock btr ebx,eax -[ ]*59[ ]+lock btr ebx,0x64 -[ ]*60[ ]+lock bts ebx,eax -[ ]*61[ ]+lock bts ebx,0x64 -[ ]*62[ ]+lock cmpxchg ebx,eax -[ ]*63[ ]+lock dec ebx -[ ]*64[ ]+lock inc ebx -[ ]*65[ ]+lock neg ebx -[ ]*66[ ]+lock not ebx -[ ]*67[ ]+lock or eax,ebx -[ ]*68[ ]+lock or ebx,0x64 -[ ]*69[ ]+lock sbb eax,ebx -[ ]*70[ ]+lock sbb ebx,0x64 -[ ]*71[ ]+lock sub eax,ebx -[ ]*72[ ]+lock sub ebx,0x64 -[ ]*73[ ]+lock xadd ebx,eax -[ ]*74[ ]+lock xchg ebx,eax -[ ]*75[ ]+lock xchg ebx,eax -[ ]*76[ ]+lock xor eax,ebx -[ ]*77[ ]+lock xor ebx,0x64 -[ ]*78[ ]+ -[ ]*79[ ]+lock add eax,DWORD PTR \[rbx\] -[ ]*80[ ]+lock adc eax,DWORD PTR \[rbx\] -[ ]*81[ ]+lock and eax,DWORD PTR \[rbx\] -[ ]*82[ ]+lock or eax,DWORD PTR \[rbx\] -[ ]*83[ ]+lock sbb eax,DWORD PTR \[rbx\] -[ ]*84[ ]+lock sub eax,DWORD PTR \[rbx\] -[ ]*85[ ]+lock xor eax,DWORD PTR \[rbx\] -[ ]*86[ ]+lock wrmsrns +[ ]*58[ ]+lock btc ebx,eax +[ ]*59[ ]+lock btc ebx,0x64 +[ ]*60[ ]+lock btr ebx,eax +[ ]*61[ ]+lock btr ebx,0x64 +[ ]*62[ ]+lock bts ebx,eax +[ ]*63[ ]+lock bts ebx,0x64 +[ ]*64[ ]+lock cmpxchg ebx,eax +[ ]*65[ ]+lock dec ebx +[ ]*66[ ]+lock inc ebx +[ ]*67[ ]+lock neg ebx +[ ]*68[ ]+lock not ebx +[ ]*69[ ]+lock or eax,ebx +[ ]*70[ ]+lock or ebx,0x64 +[ ]*71[ ]+lock sbb eax,ebx +[ ]*72[ ]+lock sbb ebx,0x64 +[ ]*73[ ]+lock sub eax,ebx +[ ]*74[ ]+lock sub ebx,0x64 +[ ]*75[ ]+lock xadd ebx,eax +[ ]*76[ ]+lock xchg ebx,eax +[ ]*77[ ]+lock xchg ebx,eax +[ ]*78[ ]+lock xor eax,ebx +[ ]*79[ ]+lock xor ebx,0x64 +[ ]*80[ ]+ +[ ]*81[ ]+lock add eax,DWORD PTR \[rbx\] +[ ]*82[ ]+lock adc eax,DWORD PTR \[rbx\] +[ ]*83[ ]+lock and eax,DWORD PTR \[rbx\] +[ ]*84[ ]+lock or eax,DWORD PTR \[rbx\] +[ ]*85[ ]+lock sbb eax,DWORD PTR \[rbx\] +[ ]*86[ ]+lock sub eax,DWORD PTR \[rbx\] +[ ]*87[ ]+lock xor eax,DWORD PTR \[rbx\] +[ ]*88[ ]+lock wrmsrns +[ ]*89[ ]+lock rdmsrlist +[ ]*90[ ]+lock wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-lockbad-1.s b/gas/testsuite/gas/i386/x86-64-lockbad-1.s index 71e9284a1c..fcea969fb9 100644 --- a/gas/testsuite/gas/i386/x86-64-lockbad-1.s +++ b/gas/testsuite/gas/i386/x86-64-lockbad-1.s @@ -42,6 +42,8 @@ foo: lock sub (%rbx), %eax lock xor (%rbx), %eax lock wrmsrns + lock rdmsrlist + lock wrmsrlist .intel_syntax noprefix lock mov eax,ebx @@ -84,3 +86,5 @@ foo: lock sub eax,DWORD PTR [rbx] lock xor eax,DWORD PTR [rbx] lock wrmsrns + lock rdmsrlist + lock wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist-intel.d b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d new file mode 100644 index 0000000000..97a2a60e43 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist-intel.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 MSRLIST insns (Intel disassembly) +#source: x86-64-msrlist.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.d b/gas/testsuite/gas/i386/x86-64-msrlist.d new file mode 100644 index 0000000000..64beed7aa3 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.d @@ -0,0 +1,14 @@ +#as: +#objdump: -dw +#name: x86_64 MSRLIST insns +#source: x86-64-msrlist.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist +\s*[a-f0-9]+:\s*f2 0f 01 c6\s+rdmsrlist +\s*[a-f0-9]+:\s*f3 0f 01 c6\s+wrmsrlist diff --git a/gas/testsuite/gas/i386/x86-64-msrlist.s b/gas/testsuite/gas/i386/x86-64-msrlist.s new file mode 100644 index 0000000000..ad57451da9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-msrlist.s @@ -0,0 +1,11 @@ +# Check 64bit MSRLIST instructions + + .allow_index_reg + .text +_start: + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST + +.intel_syntax noprefix + rdmsrlist #MSRLIST + wrmsrlist #MSRLIST diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 8c88114202..0601bee877 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -1281,6 +1281,8 @@ enum X86_64_E9, X86_64_EA, X86_64_0F01_REG_0, + X86_64_0F01_REG_0_MOD_3_RM_6_P_1, + X86_64_0F01_REG_0_MOD_3_RM_6_P_3, X86_64_0F01_REG_1, X86_64_0F01_REG_1_RM_5_PREFIX_2, X86_64_0F01_REG_1_RM_6_PREFIX_2, @@ -2974,6 +2976,9 @@ static const struct dis386 prefix_table[][4] = { /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ { { "wrmsrns", { Skip_MODRM }, 0 }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, }, /* PREFIX_0F01_REG_1_RM_4 */ @@ -4315,6 +4320,18 @@ static const struct dis386 x86_64_table[][2] = { { "sgdt", { M }, 0 }, }, + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ + { + { Bad_Opcode }, + { "wrmsrlist", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ + { + { Bad_Opcode }, + { "rdmsrlist", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_1 */ { { "sidt{Q|Q}", { M }, 0 }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 5714f731ad..eac229e54d 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -257,6 +257,8 @@ static initializer cpu_flag_init[] = "CpuRAOINT" }, { "CPU_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_MSRLIST_FLAGS", + "CpuMSRLIST" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -463,6 +465,8 @@ static initializer cpu_flag_init[] = "CpuRAOINT" }, { "CPU_ANY_WRMSRNS_FLAGS", "CpuWRMSRNS" }, + { "CPU_ANY_MSRLIST_FLAGS", + "CpuMSRLIST" }, }; static initializer operand_type_init[] = @@ -670,6 +674,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuCMPCCXADD), BITFIELD (CpuRAOINT), BITFIELD (CpuWRMSRNS), + BITFIELD (CpuMSRLIST), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 90e0591ae2..75c23aaec6 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -221,6 +221,8 @@ enum CpuRAOINT, /* Intel WRMSRNS Instructions support required */ CpuWRMSRNS, + /* Intel MSRLIST Instructions support required. */ + CpuMSRLIST, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -406,6 +408,7 @@ typedef union i386_cpu_flags unsigned int cpucmpccxadd:1; unsigned int cpuraoint:1; unsigned int cpuwrmsrns:1; + unsigned int cpumsrlist:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 0b3aa8936e..0dd7106a1c 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3332,3 +3332,10 @@ axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_l wrmsrns, 0x0f01c6, None, CpuWRMSRNS, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // WRMSRNS instructions end. + +// MSRLIST instructions. + +rdmsrlist, 0xf20f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} +wrmsrlist, 0xf30f01c6, None, CpuMSRLIST|Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} + +// MSRLIST instructions end.