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[8.43.85.97]) by mx.google.com with ESMTPS id i19-20020a05640242d300b0045bd55b122fsi2429639edc.57.2022.10.14.02.17.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 02:17:06 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=gt2jjTmG; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BD652383DB92 for ; Fri, 14 Oct 2022 09:16:06 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BD652383DB92 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665738966; bh=0XihcDG3nk6hkMGlRGgkXgwzxffdHBoCIXSLcWKSC/A=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=gt2jjTmGr2pefhm5FgPq5KEI4fKj8o1ORRl3yIIAi2tcWfyb7EULPmlEe69Jx2LW6 6Z7WsQch5fUa5aUG5T/gxNY9JZKWfLC5km3usHkU3Vv2pOQ6+19UjYvxwzV9+OOjSe RW1DBzmewwAVcw1B3jM22cQkjuidf/NznPw6gmn0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by sourceware.org (Postfix) with ESMTPS id DC56C385842F for ; Fri, 14 Oct 2022 09:14:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DC56C385842F X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="369520163" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="369520163" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Oct 2022 02:14:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10499"; a="629873050" X-IronPort-AV: E=Sophos;i="5.95,182,1661842800"; d="scan'208";a="629873050" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 14 Oct 2022 02:14:52 -0700 Received: from shliclel314.sh.intel.com (shliclel314.sh.intel.com [10.239.240.214]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 56E231009C9A; Fri, 14 Oct 2022 17:14:50 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH 06/10] Support Intel RAO-INT Date: Fri, 14 Oct 2022 17:12:44 +0800 Message-Id: <20221014091248.4920-7-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20221014091248.4920-1-haochen.jiang@intel.com> References: <20221014091248.4920-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.8 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: Kong Lingling Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1746653965282559859?= X-GMAIL-MSGID: =?utf-8?q?1746653965282559859?= From: Kong Lingling gas/ChangeLog: * NEWS: Support Intel RAO-INT. * config/tc-i386.c: Add raoint. * doc/c-i386.texi: Document .raoint and noraoint. * testsuite/gas/i386/i386.exp: Run RAOINT tests. * testsuite/gas/i386/raoint-intel.d: New test. * testsuite/gas/i386/raoint.d: Ditto. * testsuite/gas/i386/raoint.s: Ditto. * testsuite/gas/i386/x86-64-raoint-intel.d: Ditto. * testsuite/gas/i386/x86-64-raoint.d: Ditto. * testsuite/gas/i386/x86-64-raoint.s: Ditto. opcodes/ChangeLog: * i386-dis.c (MOD_0F38FC): New. (PREFIX_0F38FC): Ditto. (mod_table): Add MOD_0F38FC. (prefix_table): Add PREFIX_0F38FC. * i386-gen.c: (cpu_flag_init): Add CPU_RAOINT_FLAGS and CPU_ANY_RAOINT_FLAGS. * i386-init.h: Regenerated. * i386-opc.h: (CpuRAOINT): New. (i386_cpu_flags): Add cpuraoint. * i386-opc.tbl: Add RAOINT instructions. * i386-tbl.h: Regenerated. --- gas/NEWS | 2 + gas/config/tc-i386.c | 3 +- gas/doc/c-i386.texi | 4 +- gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/raoint-intel.d | 18 + gas/testsuite/gas/i386/raoint.d | 18 + gas/testsuite/gas/i386/raoint.s | 15 + gas/testsuite/gas/i386/x86-64-raoint-intel.d | 18 + gas/testsuite/gas/i386/x86-64-raoint.d | 18 + gas/testsuite/gas/i386/x86-64-raoint.s | 15 + opcodes/i386-dis.c | 16 +- opcodes/i386-gen.c | 5 + opcodes/i386-init.h | 514 +- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 9 + opcodes/i386-tbl.h | 7874 +++++++++--------- 16 files changed, 4379 insertions(+), 4159 deletions(-) create mode 100644 gas/testsuite/gas/i386/raoint-intel.d create mode 100644 gas/testsuite/gas/i386/raoint.d create mode 100644 gas/testsuite/gas/i386/raoint.s create mode 100644 gas/testsuite/gas/i386/x86-64-raoint-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.d create mode 100644 gas/testsuite/gas/i386/x86-64-raoint.s diff --git a/gas/NEWS b/gas/NEWS index 9757209a9f..f352c5ab89 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Intel RAO-INT instructions. + * Add support for Intel CMPccXADD instructions. * Add support for Intel AVX-NE-CONVERT instructions. diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 7045e18cff..07d72d1af1 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1097,7 +1097,8 @@ static const arch_entry cpu_arch[] = SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false), SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false), SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false), - SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false) + SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false), + SUBARCH (raoint, RAOINT, ANY_RAOINT, false), }; #undef SUBARCH diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 62202157b3..3832628e6e 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -217,6 +217,7 @@ accept various extension mnemonics. For example, @code{avx_vnni_int8}, @code{avx_ne_convert}, @code{cmpccxadd}, +@code{raoint}, @code{noavx512f}, @code{noavx512cd}, @code{noavx512er}, @@ -241,6 +242,7 @@ accept various extension mnemonics. For example, @code{noavx_vnni_int8}, @code{noavx_ne_convert}, @code{nocmpccxadd}, +@code{noraoint}, @code{noenqcmd}, @code{noserialize}, @code{notsxldtrk}, @@ -1542,7 +1544,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt} @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert} -@item @samp{.cmpccxadd} +@item @samp{.cmpccxadd} @tab @samp{.raoint} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp index fb2e2aa446..1eb0eabb6b 100644 --- a/gas/testsuite/gas/i386/i386.exp +++ b/gas/testsuite/gas/i386/i386.exp @@ -486,6 +486,8 @@ if [gas_32_check] then { run_dump_test "avx-ne-convert" run_dump_test "avx-ne-convert-intel" run_list_test "cmpccxadd-inval" + run_dump_test "raoint" + run_dump_test "raoint-intel" run_list_test "sg" run_dump_test "clzero" run_dump_test "invlpgb" @@ -1162,6 +1164,8 @@ if [gas_64_check] then { run_dump_test "x86-64-avx-ne-convert-intel" run_dump_test "x86-64-cmpccxadd" run_dump_test "x86-64-cmpccxadd-intel" + run_dump_test "x86-64-raoint" + run_dump_test "x86-64-raoint-intel" run_dump_test "x86-64-clzero" run_dump_test "x86-64-mwaitx-bdver4" run_list_test "x86-64-mwaitx-reg" diff --git a/gas/testsuite/gas/i386/raoint-intel.d b/gas/testsuite/gas/i386/raoint-intel.d new file mode 100644 index 0000000000..b50d423a5f --- /dev/null +++ b/gas/testsuite/gas/i386/raoint-intel.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw -Mintel +#name: i386 RAOINT insns (Intel disassembly) +#source: raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor DWORD PTR \[eax\],edx +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor DWORD PTR \[eax\],edx diff --git a/gas/testsuite/gas/i386/raoint.d b/gas/testsuite/gas/i386/raoint.d new file mode 100644 index 0000000000..2c310c5cc7 --- /dev/null +++ b/gas/testsuite/gas/i386/raoint.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw +#name: i386 RAOINT insns +#source: raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) +\s*[a-f0-9]+:\s*0f 38 fc 10\s+aadd %edx,\(%eax\) +\s*[a-f0-9]+:\s*66 0f 38 fc 10\s+aand %edx,\(%eax\) +\s*[a-f0-9]+:\s*f2 0f 38 fc 10\s+aor %edx,\(%eax\) +\s*[a-f0-9]+:\s*f3 0f 38 fc 10\s+axor %edx,\(%eax\) diff --git a/gas/testsuite/gas/i386/raoint.s b/gas/testsuite/gas/i386/raoint.s new file mode 100644 index 0000000000..63398dfb82 --- /dev/null +++ b/gas/testsuite/gas/i386/raoint.s @@ -0,0 +1,15 @@ +# Check 32bit AVX-NE-CONVERT instructions + + .allow_index_reg + .text +_start: + aadd %edx, (%eax) #RAO-INT + aand %edx, (%eax) #RAO-INT + aor %edx, (%eax) #RAO-INT + axor %edx, (%eax) #RAO-INT + +.intel_syntax noprefix + aadd DWORD PTR [eax], %edx #RAO-INT + aand DWORD PTR [eax], %edx #RAO-INT + aor DWORD PTR [eax], %edx #RAO-INT + axor DWORD PTR [eax], %edx #RAO-INT diff --git a/gas/testsuite/gas/i386/x86-64-raoint-intel.d b/gas/testsuite/gas/i386/x86-64-raoint-intel.d new file mode 100644 index 0000000000..d7de4849a2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint-intel.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw -Mintel +#name: x86_64 RAOINT insns (Intel disassembly) +#source: x86-64-raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor QWORD PTR \[rax\],rdx +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor QWORD PTR \[rax\],rdx diff --git a/gas/testsuite/gas/i386/x86-64-raoint.d b/gas/testsuite/gas/i386/x86-64-raoint.d new file mode 100644 index 0000000000..711fe48064 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint.d @@ -0,0 +1,18 @@ +#as: +#objdump: -dw +#name: x86_64 RAOINT insns +#source: x86-64-raoint.s + +.*: +file format .* + +Disassembly of section \.text: + +0+ <_start>: +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*48 0f 38 fc 10\s+aadd %rdx,\(%rax\) +\s*[a-f0-9]+:\s*66 48 0f 38 fc 10\s+aand %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f2 48 0f 38 fc 10\s+aor %rdx,\(%rax\) +\s*[a-f0-9]+:\s*f3 48 0f 38 fc 10\s+axor %rdx,\(%rax\) diff --git a/gas/testsuite/gas/i386/x86-64-raoint.s b/gas/testsuite/gas/i386/x86-64-raoint.s new file mode 100644 index 0000000000..28590626ca --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-raoint.s @@ -0,0 +1,15 @@ +# Check 64bit RAOINT instructions + + .allow_index_reg + .text +_start: + aadd %rdx, (%rax) #RAO-INT + aand %rdx, (%rax) #RAO-INT + aor %rdx, (%rax) #RAO-INT + axor %rdx, (%rax) #RAO-INT + +.intel_syntax noprefix + aadd QWORD PTR [rax], %rdx #RAO-INT + aand QWORD PTR [rax], %rdx #RAO-INT + aor QWORD PTR [rax], %rdx #RAO-INT + axor QWORD PTR [rax], %rdx #RAO-INT diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 37bbbd3815..60a334bbd6 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -887,6 +887,7 @@ enum MOD_0F38F9, MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1, + MOD_0F38FC, MOD_0F3A0F_PREFIX_1, MOD_VEX_0F12_PREFIX_0, @@ -1086,6 +1087,7 @@ enum PREFIX_0F38F8, PREFIX_0F38FA, PREFIX_0F38FB, + PREFIX_0F38FC, PREFIX_0F3A0F, PREFIX_VEX_0F10, PREFIX_VEX_0F11, @@ -3598,6 +3600,14 @@ static const struct dis386 prefix_table[][4] = { { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, }, + /* PREFIX_0F38FC */ + { + { "aadd", { Edq, Gdq }, PREFIX_OPCODE }, + { "axor", { Edq, Gdq }, PREFIX_OPCODE }, + { "aand", { Edq, Gdq }, PREFIX_OPCODE }, + { "aor", { Edq, Gdq }, PREFIX_OPCODE }, + }, + /* PREFIX_0F3A0F */ { { Bad_Opcode }, @@ -4802,7 +4812,7 @@ static const struct dis386 three_byte_table[][256] = { { MOD_TABLE (MOD_0F38F9) }, { PREFIX_TABLE (PREFIX_0F38FA) }, { PREFIX_TABLE (PREFIX_0F38FB) }, - { Bad_Opcode }, + { MOD_TABLE (MOD_0F38FC) }, { Bad_Opcode }, { Bad_Opcode }, { Bad_Opcode }, @@ -8374,6 +8384,10 @@ static const struct dis386 mod_table[][2] = { { Bad_Opcode }, { "encodekey256", { Gd, Ed }, 0 }, }, + { + /* MOD_0F38FC */ + { PREFIX_TABLE (PREFIX_0F38FC) }, + }, { /* MOD_0F3A0F_PREFIX_1 */ { Bad_Opcode }, diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index 96d8d2ceb8..3a7511a242 100644 --- a/opcodes/i386-gen.c +++ b/opcodes/i386-gen.c @@ -253,6 +253,8 @@ static initializer cpu_flag_init[] = "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" }, { "CPU_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_RAOINT_FLAGS", + "CpuRAOINT" }, { "CPU_IAMCU_FLAGS", "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" }, { "CPU_ADX_FLAGS", @@ -455,6 +457,8 @@ static initializer cpu_flag_init[] = "CpuAVX_NE_CONVERT" }, { "CPU_ANY_CMPCCXADD_FLAGS", "CpuCMPCCXADD" }, + { "CPU_ANY_RAOINT_FLAGS", + "CpuRAOINT" }, }; static initializer operand_type_init[] = @@ -660,6 +664,7 @@ static bitfield cpu_flags[] = BITFIELD (CpuAVX_VNNI_INT8), BITFIELD (CpuAVX_NE_CONVERT), BITFIELD (CpuCMPCCXADD), + BITFIELD (CpuRAOINT), BITFIELD (CpuMWAITX), BITFIELD (CpuCLZERO), BITFIELD (CpuOSPKE), diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index 052c59b162..cb6c372203 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -217,6 +217,8 @@ enum CpuAVX_NE_CONVERT, /* Intel CMPccXADD instructions support required. */ CpuCMPCCXADD, + /* Intel RAO INT Instructions support required. */ + CpuRAOINT, /* mwaitx instruction required */ CpuMWAITX, /* Clzero instruction required */ @@ -400,6 +402,7 @@ typedef union i386_cpu_flags unsigned int cpuavx_vnni_int8:1; unsigned int cpuavx_ne_convert:1; unsigned int cpucmpccxadd:1; + unsigned int cpuraoint:1; unsigned int cpumwaitx:1; unsigned int cpuclzero:1; unsigned int cpuospke:1; @@ -436,7 +439,7 @@ typedef union i386_cpu_flags unsigned int cpu64:1; unsigned int cpuno64:1; #ifdef CpuUnused - // unsigned int unused:(CpuNumOfBits - CpuUnused); + unsigned int unused:(CpuNumOfBits - CpuUnused); #endif } bitfield; unsigned int array[CpuNumOfUints]; diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index 2b704708a4..4affd056b2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -3317,3 +3317,12 @@ cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|Swa cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex } // CMPCCXADD instructions end. + +// RAOINT instructions. + +aadd, 0xf38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +aand, 0x660f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +aor, 0xf20f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} +axor, 0xf30f38fc, None, CpuRAOINT, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf,{ Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex} + +// RAOINT instructions end.