diff mbox series

[04/10] Support Intel CMPccXADD

Message ID 20221014091248.4920-5-haochen.jiang@intel.com
State Accepted
Headers
Series Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Jiang, Haochen Oct. 14, 2022, 9:12 a.m. UTC 
  gas/ChangeLog:

	* NEWS: Support Intel CMPccXADD.
	* config/tc-i386.c: Add cmpccxadd.
	(build_modrm_byte): Add operations for Vex.VVVV reg
	on operand 0 while have memory operand.
	* doc/c-i386.texi: Document .cmpccxadd, nocmpccxadd.
	* testsuite/gas/i386/i386.exp: Run CMPccXADD tests.
	* testsuite/gas/i386/cmpccxadd-inval.s: New test.
	* testsuite/gas/i386/cmpccxadd-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.s: Ditto.
	* testsuite/gas/i386/x86-64-cmpccxadd.d: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (Mdq): New.
	(MOD_VEX_0F38E0_X86_64): Ditto.
	(MOD_VEX_0F38E1_X86_64): Ditto.
	(MOD_VEX_0F38E2_X86_64): Ditto.
	(MOD_VEX_0F38E3_X86_64): Ditto.
	(MOD_VEX_0F38E4_X86_64): Ditto.
	(MOD_VEX_0F38E5_X86_64): Ditto.
	(MOD_VEX_0F38E6_X86_64): Ditto.
	(MOD_VEX_0F38E7_X86_64): Ditto.
	(MOD_VEX_0F38E8_X86_64): Ditto.
	(MOD_VEX_0F38E9_X86_64): Ditto.
	(MOD_VEX_0F38EA_X86_64): Ditto.
	(MOD_VEX_0F38EB_X86_64): Ditto.
	(MOD_VEX_0F38EC_X86_64): Ditto.
	(MOD_VEX_0F38ED_X86_64): Ditto.
	(MOD_VEX_0F38EE_X86_64): Ditto.
	(MOD_VEX_0F38EF_X86_64): Ditto.
	(X86_64_VEX_0F38E0): Ditto.
	(X86_64_VEX_0F38E1): Ditto.
	(X86_64_VEX_0F38E2): Ditto.
	(X86_64_VEX_0F38E3): Ditto.
	(X86_64_VEX_0F38E4): Ditto.
	(X86_64_VEX_0F38E5): Ditto.
	(X86_64_VEX_0F38E6): Ditto.
	(X86_64_VEX_0F38E7): Ditto.
	(X86_64_VEX_0F38E8): Ditto.
	(X86_64_VEX_0F38E9): Ditto.
	(X86_64_VEX_0F38EA): Ditto.
	(X86_64_VEX_0F38EB): Ditto.
	(X86_64_VEX_0F38EC): Ditto.
	(X86_64_VEX_0F38ED): Ditto.
	(X86_64_VEX_0F38EE): Ditto.
	(X86_64_VEX_0F38EF): Ditto.
	(mod_table): Add MOD_VEX_0F38E0_X86_64, MOD_VEX_0F38E1_X86_64,
	MOD_VEX_0F38E2_X86_64, MOD_VEX_0F38E3_X86_64, MOD_VEX_0F38E4_X86_64,
	MOD_VEX_0F38E5_X86_64, MOD_VEX_0F38E6_X86_64, MOD_VEX_0F38E7_X86_64,
	MOD_VEX_0F38E8_X86_64, MOD_VEX_0F38E9_X86_64, MOD_VEX_0F38EA_X86_64,
	MOD_VEX_0F38EB_X86_64, MOD_VEX_0F38EC_X86_64, MOD_VEX_0F38ED_X86_64,
	MOD_VEX_0F38EE_X86_64, MOD_VEX_0F38EF_X86_64.
	(x86_64_table): Add X86_64_VEX_0F38E0, X86_64_VEX_0F38E1,
	X86_64_VEX_0F38E2, X86_64_VEX_0F38E3, X86_64_VEX_0F38E4,
	X86_64_VEX_0F38E5, X86_64_VEX_0F38E6, X86_64_VEX_0F38E7,
	X86_64_VEX_0F38E8, X86_64_VEX_0F38E9, X86_64_VEX_0F38EA,
	X86_64_VEX_0F38EB, X86_64_VEX_0F38EC, X86_64_VEX_0F38ED,
	X86_64_VEX_0F38EE, X86_64_VEX_0F38EF.
	* i386-gen.c (cpu_flag_init): Add CPU_CMPCCXADD_FLAGS and
	CPU_ANY_CMPCCXADD_FLAGS.
	(cpu_flags): Add CpuCMPCCXADD.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuCMPCCXADD): New.
	(i386_cpu_flags): Add cpucmpccxadd. Comment unused for it is actually 0.
	* i386-opc.tbl: Add Intel CMPccXADD instructions.
	* i386-tbl.h: Regenerated.
---
 gas/NEWS                                      |    2 +
 gas/config/tc-i386.c                          |    7 +
 gas/doc/c-i386.texi                           |    3 +
 gas/testsuite/gas/i386/cmpccxadd-inval.l      |    5 +
 gas/testsuite/gas/i386/cmpccxadd-inval.s      |    9 +
 gas/testsuite/gas/i386/i386.exp               |    3 +
 .../gas/i386/x86-64-cmpccxadd-intel.d         |  266 +
 gas/testsuite/gas/i386/x86-64-cmpccxadd.d     |  266 +
 gas/testsuite/gas/i386/x86-64-cmpccxadd.s     |  263 +
 opcodes/i386-dis.c                            |  227 +-
 opcodes/i386-gen.c                            |    5 +
 opcodes/i386-init.h                           |  514 +-
 opcodes/i386-opc.h                            |    5 +-
 opcodes/i386-opc.tbl                          |   21 +
 opcodes/i386-tbl.h                            | 8068 +++++++++--------
 15 files changed, 5500 insertions(+), 4164 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.l
 create mode 100644 gas/testsuite/gas/i386/cmpccxadd-inval.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-cmpccxadd.s

Comments

Jan Beulich Oct. 14, 2022, 1:46 p.m. UTC | #1 
On 14.10.2022 11:12, Haochen Jiang wrote:
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
>  -*- text -*-
>  
> +* Add support for Intel CMPccXADD instructions.
> +
>  * Add support for Intel AVX-NE-CONVERT instructions.
>  
>  * Add support for Intel AVX-VNNI-INT8 instructions.

I wonder if all of these really need a separate line.

> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
>    SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
>    SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
>    SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> +  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
>  };

No need for ANY_CMPCCXADD, unless you _know_ dependent features will appear.
See e.g. FSGSBASE, i.e. you can use CMPCCXADD twice here.

> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
>  #define Ma { OP_M, a_mode }
>  #define Mb { OP_M, b_mode }
>  #define Md { OP_M, d_mode }
> +#define Mdq { OP_M, dq_mode }

You're decoding via mod_table[], so I don't think you need this. Or (perhaps
better) vice versa - keep this (if there's no pre-existing one that fits) and
avoid the decode step through mod_table[].

> @@ -939,6 +940,22 @@ enum
>    MOD_VEX_0F388E,
>    MOD_VEX_0F38B0,
>    MOD_VEX_0F38B1,
> +  MOD_VEX_0F38E0_X86_64,
> +  MOD_VEX_0F38E1_X86_64,
> +  MOD_VEX_0F38E2_X86_64,
> +  MOD_VEX_0F38E3_X86_64,
> +  MOD_VEX_0F38E4_X86_64,
> +  MOD_VEX_0F38E5_X86_64,
> +  MOD_VEX_0F38E6_X86_64,
> +  MOD_VEX_0F38E7_X86_64,
> +  MOD_VEX_0F38E8_X86_64,
> +  MOD_VEX_0F38E9_X86_64,
> +  MOD_VEX_0F38EA_X86_64,
> +  MOD_VEX_0F38EB_X86_64,
> +  MOD_VEX_0F38EC_X86_64,
> +  MOD_VEX_0F38ED_X86_64,
> +  MOD_VEX_0F38EE_X86_64,
> +  MOD_VEX_0F38EF_X86_64,

Hmm, I really need to split off (and re-submit) the re-usable parts of
"x86-64: Intel64 adjustments for conditional jumps" (see
https://sourceware.org/pipermail/binutils/2020-July/112365.html), to avoid
the need for 16 almost identical entries of several kinds throughout this
patch.

> @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
>      /* MOD_VEX_0F38B1*/
>      { VEX_W_TABLE (VEX_W_0F38B1) },
>    },
> +  {
> +    /* MOD_VEX_0F38E0_X86_64 */
> +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> +  },
> +  {
> +    /* MOD_VEX_0F38E1_X86_64 */
> +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> +  },
> +  {
> +    /* MOD_VEX_0F38E2_X86_64 */
> +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> +  },
> +  {
> +    /* MOD_VEX_0F38E3_X86_64 */
> +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },

I understand the ISA extensions document names the insn this way and doesn't
list cmpaexadd (same for other aliases), but I think this is a mistake in
the doc. I've raised a respective question in the ISA extensions forum: I
think representation of conditions to check for should be uniform among
insns, and hence it should be "ae" here. (That would also be the effect if
you used %C<whatever> here.)

> @@ -433,7 +436,7 @@ typedef union i386_cpu_flags
>        unsigned int cpu64:1;
>        unsigned int cpuno64:1;
>  #ifdef CpuUnused
> -      unsigned int unused:(CpuNumOfBits - CpuUnused);
> +      // unsigned int unused:(CpuNumOfBits - CpuUnused);
>  #endif

No - you should instead comment out the #define of CpuUnused - see the
comment there.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
>  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>  
>  // AVX_VNNI_INT8 instructions end.
> +
> +// CMPCCXADD instructions.
> +
> +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }

Along the lines of the earlier comment - you want to use the <cc>
template here, eliminating the need for 16 almost identical lines _and_
supplying all condition code representation in one go.

Apart from that you forgot CheckRegSize here afaict. And please again
VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
Vex instead of Vex128. Further these insns should allow for l and q
suffixes in AT&T mode.

And finally - is SwapSources really appropriate to use here? There's only
one pure source operand, the other two are also serving as destinations.
I wonder whether an attribute is necessary here in the first place: Vex-
encoded insns with a memory destination never have two further register
operands, so that property should suffice for identifying the case in
build_modrm_byte(). Alternatively you could also simply use the CPU flag.

Jan
H.J. Lu Oct. 14, 2022, 6:27 p.m. UTC | #2 
On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > --- a/gas/NEWS
> > +++ b/gas/NEWS
> > @@ -1,5 +1,7 @@
> >  -*- text -*-
> >
> > +* Add support for Intel CMPccXADD instructions.
> > +
> >  * Add support for Intel AVX-NE-CONVERT instructions.
> >
> >  * Add support for Intel AVX-VNNI-INT8 instructions.
>
> I wonder if all of these really need a separate line.
>
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
> >    SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> >    SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> >    SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> > +  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> >  };
>
> No need for ANY_CMPCCXADD, unless you _know_ dependent features will appear.
> See e.g. FSGSBASE, i.e. you can use CMPCCXADD twice here.
>
> > --- a/opcodes/i386-dis.c
> > +++ b/opcodes/i386-dis.c
> > @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
> >  #define Ma { OP_M, a_mode }
> >  #define Mb { OP_M, b_mode }
> >  #define Md { OP_M, d_mode }
> > +#define Mdq { OP_M, dq_mode }
>
> You're decoding via mod_table[], so I don't think you need this. Or (perhaps
> better) vice versa - keep this (if there's no pre-existing one that fits) and
> avoid the decode step through mod_table[].
>
> > @@ -939,6 +940,22 @@ enum
> >    MOD_VEX_0F388E,
> >    MOD_VEX_0F38B0,
> >    MOD_VEX_0F38B1,
> > +  MOD_VEX_0F38E0_X86_64,
> > +  MOD_VEX_0F38E1_X86_64,
> > +  MOD_VEX_0F38E2_X86_64,
> > +  MOD_VEX_0F38E3_X86_64,
> > +  MOD_VEX_0F38E4_X86_64,
> > +  MOD_VEX_0F38E5_X86_64,
> > +  MOD_VEX_0F38E6_X86_64,
> > +  MOD_VEX_0F38E7_X86_64,
> > +  MOD_VEX_0F38E8_X86_64,
> > +  MOD_VEX_0F38E9_X86_64,
> > +  MOD_VEX_0F38EA_X86_64,
> > +  MOD_VEX_0F38EB_X86_64,
> > +  MOD_VEX_0F38EC_X86_64,
> > +  MOD_VEX_0F38ED_X86_64,
> > +  MOD_VEX_0F38EE_X86_64,
> > +  MOD_VEX_0F38EF_X86_64,
>
> Hmm, I really need to split off (and re-submit) the re-usable parts of
> "x86-64: Intel64 adjustments for conditional jumps" (see
> https://sourceware.org/pipermail/binutils/2020-July/112365.html), to avoid
> the need for 16 almost identical entries of several kinds throughout this
> patch.
>
> > @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
> >      /* MOD_VEX_0F38B1*/
> >      { VEX_W_TABLE (VEX_W_0F38B1) },
> >    },
> > +  {
> > +    /* MOD_VEX_0F38E0_X86_64 */
> > +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > +  },
> > +  {
> > +    /* MOD_VEX_0F38E1_X86_64 */
> > +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > +  },
> > +  {
> > +    /* MOD_VEX_0F38E2_X86_64 */
> > +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > +  },
> > +  {
> > +    /* MOD_VEX_0F38E3_X86_64 */
> > +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
>
> I understand the ISA extensions document names the insn this way and doesn't
> list cmpaexadd (same for other aliases), but I think this is a mistake in

Lack of aliases is a bad thing.  In any case, assembler should follow
the spec.

> the doc. I've raised a respective question in the ISA extensions forum: I
> think representation of conditions to check for should be uniform among
> insns, and hence it should be "ae" here. (That would also be the effect if
> you used %C<whatever> here.)
>
> > @@ -433,7 +436,7 @@ typedef union i386_cpu_flags
> >        unsigned int cpu64:1;
> >        unsigned int cpuno64:1;
> >  #ifdef CpuUnused
> > -      unsigned int unused:(CpuNumOfBits - CpuUnused);
> > +      // unsigned int unused:(CpuNumOfBits - CpuUnused);
> >  #endif
>
> No - you should instead comment out the #define of CpuUnused - see the
> comment there.
>
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
> >  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> >
> >  // AVX_VNNI_INT8 instructions end.
> > +
> > +// CMPCCXADD instructions.
> > +
> > +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>
> Along the lines of the earlier comment - you want to use the <cc>
> template here, eliminating the need for 16 almost identical lines _and_
> supplying all condition code representation in one go.
>
> Apart from that you forgot CheckRegSize here afaict. And please again
> VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
> Vex instead of Vex128. Further these insns should allow for l and q
> suffixes in AT&T mode.

l and q suffixes here are totally unnecessary.  For new instructions,
suffixes should be required only if needed.

> And finally - is SwapSources really appropriate to use here? There's only
> one pure source operand, the other two are also serving as destinations.
> I wonder whether an attribute is necessary here in the first place: Vex-
> encoded insns with a memory destination never have two further register
> operands, so that property should suffice for identifying the case in
> build_modrm_byte(). Alternatively you could also simply use the CPU flag.
>
> Jan
H.J. Lu Oct. 14, 2022, 9:51 p.m. UTC | #3 
On Fri, Oct 14, 2022 at 11:27 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
>  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 14.10.2022 11:12, Haochen Jiang wrote:
> > > --- a/gas/NEWS
> > > +++ b/gas/NEWS
> > > @@ -1,5 +1,7 @@
> > >  -*- text -*-
> > >
> > > +* Add support for Intel CMPccXADD instructions.
> > > +
> > >  * Add support for Intel AVX-NE-CONVERT instructions.
> > >
> > >  * Add support for Intel AVX-VNNI-INT8 instructions.
> >
> > I wonder if all of these really need a separate line.
> >
> > > --- a/gas/config/tc-i386.c
> > > +++ b/gas/config/tc-i386.c
> > > @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
> > >    SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> > >    SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> > >    SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
> > > +  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> > >  };
> >
> > No need for ANY_CMPCCXADD, unless you _know_ dependent features will appear.
> > See e.g. FSGSBASE, i.e. you can use CMPCCXADD twice here.
> >
> > > --- a/opcodes/i386-dis.c
> > > +++ b/opcodes/i386-dis.c
> > > @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
> > >  #define Ma { OP_M, a_mode }
> > >  #define Mb { OP_M, b_mode }
> > >  #define Md { OP_M, d_mode }
> > > +#define Mdq { OP_M, dq_mode }
> >
> > You're decoding via mod_table[], so I don't think you need this. Or (perhaps
> > better) vice versa - keep this (if there's no pre-existing one that fits) and
> > avoid the decode step through mod_table[].
> >
> > > @@ -939,6 +940,22 @@ enum
> > >    MOD_VEX_0F388E,
> > >    MOD_VEX_0F38B0,
> > >    MOD_VEX_0F38B1,
> > > +  MOD_VEX_0F38E0_X86_64,
> > > +  MOD_VEX_0F38E1_X86_64,
> > > +  MOD_VEX_0F38E2_X86_64,
> > > +  MOD_VEX_0F38E3_X86_64,
> > > +  MOD_VEX_0F38E4_X86_64,
> > > +  MOD_VEX_0F38E5_X86_64,
> > > +  MOD_VEX_0F38E6_X86_64,
> > > +  MOD_VEX_0F38E7_X86_64,
> > > +  MOD_VEX_0F38E8_X86_64,
> > > +  MOD_VEX_0F38E9_X86_64,
> > > +  MOD_VEX_0F38EA_X86_64,
> > > +  MOD_VEX_0F38EB_X86_64,
> > > +  MOD_VEX_0F38EC_X86_64,
> > > +  MOD_VEX_0F38ED_X86_64,
> > > +  MOD_VEX_0F38EE_X86_64,
> > > +  MOD_VEX_0F38EF_X86_64,
> >
> > Hmm, I really need to split off (and re-submit) the re-usable parts of
> > "x86-64: Intel64 adjustments for conditional jumps" (see
> > https://sourceware.org/pipermail/binutils/2020-July/112365.html), to avoid
> > the need for 16 almost identical entries of several kinds throughout this
> > patch.
> >
> > > @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
> > >      /* MOD_VEX_0F38B1*/
> > >      { VEX_W_TABLE (VEX_W_0F38B1) },
> > >    },
> > > +  {
> > > +    /* MOD_VEX_0F38E0_X86_64 */
> > > +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > > +  },
> > > +  {
> > > +    /* MOD_VEX_0F38E1_X86_64 */
> > > +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > > +  },
> > > +  {
> > > +    /* MOD_VEX_0F38E2_X86_64 */
> > > +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> > > +  },
> > > +  {
> > > +    /* MOD_VEX_0F38E3_X86_64 */
> > > +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >
> > I understand the ISA extensions document names the insn this way and doesn't
> > list cmpaexadd (same for other aliases), but I think this is a mistake in
>
> Lack of aliases is a bad thing.  In any case, assembler should follow

Oops.  I meant "Lack of aliases isn't a bad thing."   Aliases make me
wonder if 2 different jcc are really different.

> the spec.
>
> > the doc. I've raised a respective question in the ISA extensions forum: I
> > think representation of conditions to check for should be uniform among
> > insns, and hence it should be "ae" here. (That would also be the effect if
> > you used %C<whatever> here.)
> >
> > > @@ -433,7 +436,7 @@ typedef union i386_cpu_flags
> > >        unsigned int cpu64:1;
> > >        unsigned int cpuno64:1;
> > >  #ifdef CpuUnused
> > > -      unsigned int unused:(CpuNumOfBits - CpuUnused);
> > > +      // unsigned int unused:(CpuNumOfBits - CpuUnused);
> > >  #endif
> >
> > No - you should instead comment out the #define of CpuUnused - see the
> > comment there.
> >
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
> > >  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> > >
> > >  // AVX_VNNI_INT8 instructions end.
> > > +
> > > +// CMPCCXADD instructions.
> > > +
> > > +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> >
> > Along the lines of the earlier comment - you want to use the <cc>
> > template here, eliminating the need for 16 almost identical lines _and_
> > supplying all condition code representation in one go.
> >
> > Apart from that you forgot CheckRegSize here afaict. And please again
> > VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
> > Vex instead of Vex128. Further these insns should allow for l and q
> > suffixes in AT&T mode.
>
> l and q suffixes here are totally unnecessary.  For new instructions,
> suffixes should be required only if needed.
>
> > And finally - is SwapSources really appropriate to use here? There's only
> > one pure source operand, the other two are also serving as destinations.
> > I wonder whether an attribute is necessary here in the first place: Vex-
> > encoded insns with a memory destination never have two further register
> > operands, so that property should suffice for identifying the case in
> > build_modrm_byte(). Alternatively you could also simply use the CPU flag.
> >
> > Jan
>
>
>
> --
> H.J.
Jan Beulich Oct. 16, 2022, 6:19 a.m. UTC | #4 
On 14.10.2022 15:46, Jan Beulich wrote:
> On 14.10.2022 11:12, Haochen Jiang wrote:
>> --- a/opcodes/i386-dis.c
>> +++ b/opcodes/i386-dis.c
>> @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
>>  #define Ma { OP_M, a_mode }
>>  #define Mb { OP_M, b_mode }
>>  #define Md { OP_M, d_mode }
>> +#define Mdq { OP_M, dq_mode }
> 
> You're decoding via mod_table[], so I don't think you need this. Or (perhaps
> better) vice versa - keep this (if there's no pre-existing one that fits) and
> avoid the decode step through mod_table[].

In any event you will want to add a decode step through vex_len_table[],
unless I've forgot about some mechanism making this unnecessary for e.g.
all VEX-encoded GPR insns collectively.

Jan
Jan Beulich Oct. 16, 2022, 6:25 a.m. UTC | #5 
On 14.10.2022 20:27, H.J. Lu wrote:
>  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>> --- a/opcodes/i386-opc.tbl
>>> +++ b/opcodes/i386-opc.tbl
>>> @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
>>>  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
>>>
>>>  // AVX_VNNI_INT8 instructions end.
>>> +
>>> +// CMPCCXADD instructions.
>>> +
>>> +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
>>
>> Along the lines of the earlier comment - you want to use the <cc>
>> template here, eliminating the need for 16 almost identical lines _and_
>> supplying all condition code representation in one go.
>>
>> Apart from that you forgot CheckRegSize here afaict. And please again
>> VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
>> Vex instead of Vex128. Further these insns should allow for l and q
>> suffixes in AT&T mode.
> 
> l and q suffixes here are totally unnecessary.  For new instructions,
> suffixes should be required only if needed.

I disagree, and I'd like to ask that decisions like this not be made behind
closed doors at Intel. As said many times - there needs to be consistency,
which is a prereq for predictability. A programmer shall not be required to
read gas sources to know for which insns suffixes are permitted and for
which they aren't. Plus do you realize that "new insns" also covers RAO-INT,
where suffixes are permitted (as expected)?

Jan
Jan Beulich Oct. 16, 2022, 6:34 a.m. UTC | #6 
On 14.10.2022 23:51, H.J. Lu wrote:
> On Fri, Oct 14, 2022 at 11:27 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>>  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>> @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
>>>>      /* MOD_VEX_0F38B1*/
>>>>      { VEX_W_TABLE (VEX_W_0F38B1) },
>>>>    },
>>>> +  {
>>>> +    /* MOD_VEX_0F38E0_X86_64 */
>>>> +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
>>>> +  },
>>>> +  {
>>>> +    /* MOD_VEX_0F38E1_X86_64 */
>>>> +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
>>>> +  },
>>>> +  {
>>>> +    /* MOD_VEX_0F38E2_X86_64 */
>>>> +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
>>>> +  },
>>>> +  {
>>>> +    /* MOD_VEX_0F38E3_X86_64 */
>>>> +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
>>>
>>> I understand the ISA extensions document names the insn this way and doesn't
>>> list cmpaexadd (same for other aliases), but I think this is a mistake in
>>
>> Lack of aliases is a bad thing.  In any case, assembler should follow
> 
> Oops.  I meant "Lack of aliases isn't a bad thing."   Aliases make me
> wonder if 2 different jcc are really different.

Have you taken the time to read through my question raised in the forum?
There is a reason for there being multiple names for a single condition
code: What is meant depends on context. As said there, JZ makes sense to
use with e.g. TEST or SUB, but it doesn't make sense to use with CMP
(where JE is the appropriate mnemonic). Here we're talking of only CMP
(an advanced form of it), so not being able to use CMPEXADD (for there
only being CMPZXADD) is an issue.

>> the spec.

First of all the (early) spec should be sanitized. I'd be surprised if
there were actually rational reasons for the choice of mnemonics which
the doc currently lists; the set looks rather arbitrary to me. If the
spec cannot be relied on, I think it's better to defer implementation of
something that's questionable.

Plus: What harm would there be if gas supported the full set of mnemonics
even without the spec listing them all? It's not like there's any non-
negligible risk of these mnemonics later gaining some different meaning.

Jan

>>> the doc. I've raised a respective question in the ISA extensions forum: I
>>> think representation of conditions to check for should be uniform among
>>> insns, and hence it should be "ae" here. (That would also be the effect if
>>> you used %C<whatever> here.)
H.J. Lu Oct. 17, 2022, 11:31 p.m. UTC | #7 
On Sat, Oct 15, 2022 at 11:34 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.10.2022 23:51, H.J. Lu wrote:
> > On Fri, Oct 14, 2022 at 11:27 AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >>  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
> >>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>> @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
> >>>>      /* MOD_VEX_0F38B1*/
> >>>>      { VEX_W_TABLE (VEX_W_0F38B1) },
> >>>>    },
> >>>> +  {
> >>>> +    /* MOD_VEX_0F38E0_X86_64 */
> >>>> +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >>>> +  },
> >>>> +  {
> >>>> +    /* MOD_VEX_0F38E1_X86_64 */
> >>>> +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >>>> +  },
> >>>> +  {
> >>>> +    /* MOD_VEX_0F38E2_X86_64 */
> >>>> +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >>>> +  },
> >>>> +  {
> >>>> +    /* MOD_VEX_0F38E3_X86_64 */
> >>>> +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >>>
> >>> I understand the ISA extensions document names the insn this way and doesn't
> >>> list cmpaexadd (same for other aliases), but I think this is a mistake in
> >>
> >> Lack of aliases is a bad thing.  In any case, assembler should follow
> >
> > Oops.  I meant "Lack of aliases isn't a bad thing."   Aliases make me
> > wonder if 2 different jcc are really different.
>
> Have you taken the time to read through my question raised in the forum?
> There is a reason for there being multiple names for a single condition
> code: What is meant depends on context. As said there, JZ makes sense to
> use with e.g. TEST or SUB, but it doesn't make sense to use with CMP
> (where JE is the appropriate mnemonic). Here we're talking of only CMP
> (an advanced form of it), so not being able to use CMPEXADD (for there
> only being CMPZXADD) is an issue.

You have a point here.

> >> the spec.
>
> First of all the (early) spec should be sanitized. I'd be surprised if
> there were actually rational reasons for the choice of mnemonics which
> the doc currently lists; the set looks rather arbitrary to me. If the
> spec cannot be relied on, I think it's better to defer implementation of
> something that's questionable.
>
> Plus: What harm would there be if gas supported the full set of mnemonics
> even without the spec listing them all? It's not like there's any non-
> negligible risk of these mnemonics later gaining some different meaning.
>
> Jan
>
> >>> the doc. I've raised a respective question in the ISA extensions forum: I
> >>> think representation of conditions to check for should be uniform among
> >>> insns, and hence it should be "ae" here. (That would also be the effect if
> >>> you used %C<whatever> here.)
>
H.J. Lu Oct. 17, 2022, 11:44 p.m. UTC | #8 
On Sat, Oct 15, 2022 at 11:25 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 14.10.2022 20:27, H.J. Lu wrote:
> >  On Fri, Oct 14, 2022 at 6:46 AM Jan Beulich <jbeulich@suse.com> wrote:
> >> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>> --- a/opcodes/i386-opc.tbl
> >>> +++ b/opcodes/i386-opc.tbl
> >>> @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
> >>>  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
> >>>
> >>>  // AVX_VNNI_INT8 instructions end.
> >>> +
> >>> +// CMPCCXADD instructions.
> >>> +
> >>> +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
> >>
> >> Along the lines of the earlier comment - you want to use the <cc>
> >> template here, eliminating the need for 16 almost identical lines _and_
> >> supplying all condition code representation in one go.
> >>
> >> Apart from that you forgot CheckRegSize here afaict. And please again
> >> VexVVVV alone, without =1. Also for non-vector insns perhaps better plain
> >> Vex instead of Vex128. Further these insns should allow for l and q
> >> suffixes in AT&T mode.
> >
> > l and q suffixes here are totally unnecessary.  For new instructions,
> > suffixes should be required only if needed.
>
> I disagree, and I'd like to ask that decisions like this not be made behind
> closed doors at Intel. As said many times - there needs to be consistency,
> which is a prereq for predictability. A programmer shall not be required to
> read gas sources to know for which insns suffixes are permitted and for

We can improve documentation.  A programmer should use SDM first.
Suffixes should be used only when SDM doesn't address AT&T syntax
needs.

> which they aren't. Plus do you realize that "new insns" also covers RAO-INT,
> where suffixes are permitted (as expected)?

There is a discrepancy.

> Jan
Frager, Neal via Binutils Oct. 24, 2022, 5:55 a.m. UTC | #9 
Sorry for forgetting removing the changes in regenerated files changes in files
in all patches so the community did not see the mail. I am resending all the
patches.

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 14, 2022 9:47 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> 
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > --- a/gas/NEWS
> > +++ b/gas/NEWS
> > @@ -1,5 +1,7 @@
> >  -*- text -*-
> >
> > +* Add support for Intel CMPccXADD instructions.
> > +
> >  * Add support for Intel AVX-NE-CONVERT instructions.
> >
> >  * Add support for Intel AVX-VNNI-INT8 instructions.
> 
> I wonder if all of these really need a separate line.
> 
> > --- a/gas/config/tc-i386.c
> > +++ b/gas/config/tc-i386.c
> > @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
> >    SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> >    SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> >    SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> > false),
> > +  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> >  };
> 
> No need for ANY_CMPCCXADD, unless you _know_ dependent features will
> appear.
> See e.g. FSGSBASE, i.e. you can use CMPCCXADD twice here.

Changed to CMPCCXADD. BTW, do we need to remove them in i386-gen.c?

> 
> > --- a/opcodes/i386-dis.c
> > +++ b/opcodes/i386-dis.c
> > @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info,
> > bfd_byte *addr)  #define Ma { OP_M, a_mode }  #define Mb { OP_M,
> > b_mode }  #define Md { OP_M, d_mode }
> > +#define Mdq { OP_M, dq_mode }
> 
> You're decoding via mod_table[], so I don't think you need this. Or (perhaps
> better) vice versa - keep this (if there's no pre-existing one that fits) and avoid
> the decode step through mod_table[].

Yes, OP_M will check modrm by itself, removed the pass of mod_table.

> 
> > @@ -939,6 +940,22 @@ enum
> >    MOD_VEX_0F388E,
> >    MOD_VEX_0F38B0,
> >    MOD_VEX_0F38B1,
> > +  MOD_VEX_0F38E0_X86_64,
> > +  MOD_VEX_0F38E1_X86_64,
> > +  MOD_VEX_0F38E2_X86_64,
> > +  MOD_VEX_0F38E3_X86_64,
> > +  MOD_VEX_0F38E4_X86_64,
> > +  MOD_VEX_0F38E5_X86_64,
> > +  MOD_VEX_0F38E6_X86_64,
> > +  MOD_VEX_0F38E7_X86_64,
> > +  MOD_VEX_0F38E8_X86_64,
> > +  MOD_VEX_0F38E9_X86_64,
> > +  MOD_VEX_0F38EA_X86_64,
> > +  MOD_VEX_0F38EB_X86_64,
> > +  MOD_VEX_0F38EC_X86_64,
> > +  MOD_VEX_0F38ED_X86_64,
> > +  MOD_VEX_0F38EE_X86_64,
> > +  MOD_VEX_0F38EF_X86_64,
> 
> Hmm, I really need to split off (and re-submit) the re-usable parts of
> "x86-64: Intel64 adjustments for conditional jumps" (see
> https://sourceware.org/pipermail/binutils/2020-July/112365.html), to avoid the
> need for 16 almost identical entries of several kinds throughout this patch.

Currently I am still using 16 almost identical entries. We can put this in further
discussion.

> 
> > @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
> >      /* MOD_VEX_0F38B1*/
> >      { VEX_W_TABLE (VEX_W_0F38B1) },
> >    },
> > +  {
> > +    /* MOD_VEX_0F38E0_X86_64 */
> > +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > +    /* MOD_VEX_0F38E1_X86_64 */
> > +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > +    /* MOD_VEX_0F38E2_X86_64 */
> > +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > +    /* MOD_VEX_0F38E3_X86_64 */
> > +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> 
> I understand the ISA extensions document names the insn this way and doesn't
> list cmpaexadd (same for other aliases), but I think this is a mistake in the doc.
> I've raised a respective question in the ISA extensions forum: I think
> representation of conditions to check for should be uniform among insns, and
> hence it should be "ae" here. (That would also be the effect if you
> used %C<whatever> here.)

I changed the table to <cc> so that when developer input something like
cmpaexadd, assembler could also recognize it. For the disassembler part, it still
only have one identical name.

> 
> > @@ -433,7 +436,7 @@ typedef union i386_cpu_flags
> >        unsigned int cpu64:1;
> >        unsigned int cpuno64:1;
> >  #ifdef CpuUnused
> > -      unsigned int unused:(CpuNumOfBits - CpuUnused);
> > +      // unsigned int unused:(CpuNumOfBits - CpuUnused);
> >  #endif
> 
> No - you should instead comment out the #define of CpuUnused - see the
> comment there.

Fixed this wrong comment.

> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8,
> > Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
> >  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8,
> >
> Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|N
> o_lSuf
> > |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex,
> > RegXMM|RegYMM, RegXMM|RegYMM }
> >
> >  // AVX_VNNI_INT8 instructions end.
> > +
> > +// CMPCCXADD instructions.
> > +
> > +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64,
> >
> +Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No
> _lSuf|
> > +No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
> > +Dword|Qword|Unspecified|BaseIndex }
> 
> Along the lines of the earlier comment - you want to use the <cc> template here,
> eliminating the need for 16 almost identical lines _and_ supplying all condition
> code representation in one go.

Mentioned above.

> 
> Apart from that you forgot CheckRegSize here afaict. And please again VexVVVV
> alone, without =1. Also for non-vector insns perhaps better plain Vex instead of
> Vex128. Further these insns should allow for l and q suffixes in AT&T mode.

Done.

> 
> And finally - is SwapSources really appropriate to use here? There's only one
> pure source operand, the other two are also serving as destinations.
> I wonder whether an attribute is necessary here in the first place: Vex- encoded
> insns with a memory destination never have two further register operands, so
> that property should suffice for identifying the case in build_modrm_byte().
> Alternatively you could also simply use the CPU flag.

We may need a special identifier for CMPccXADD since we have VVVV at
operand 3, where it is always at operand 2 for all other insts which
have VVVV. That is the reason we reuse SwapSources. It might be not
that same as the original meaning. But we want to avoid adding a bit
for this very rare case. Do we need to change that?

Haochen

> 
> Jan
H.J. Lu Oct. 24, 2022, 7:12 p.m. UTC | #10 
On Sun, Oct 23, 2022 at 7:30 PM Jiang, Haochen <haochen.jiang@intel.com> wrote:
>
> > -----Original Message-----
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Friday, October 14, 2022 9:47 PM
> > To: Jiang, Haochen <haochen.jiang@intel.com>
> > Cc: hjl.tools@gmail.com; binutils@sourceware.org
> > Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> >
> > On 14.10.2022 11:12, Haochen Jiang wrote:
> > > --- a/gas/NEWS
> > > +++ b/gas/NEWS
> > > @@ -1,5 +1,7 @@
> > >  -*- text -*-
> > >
> > > +* Add support for Intel CMPccXADD instructions.
> > > +
> > >  * Add support for Intel AVX-NE-CONVERT instructions.
> > >
> > >  * Add support for Intel AVX-VNNI-INT8 instructions.
> >
> > I wonder if all of these really need a separate line.
> >
> > > --- a/gas/config/tc-i386.c
> > > +++ b/gas/config/tc-i386.c
> > > @@ -1097,6 +1097,7 @@ static const arch_entry cpu_arch[] =
> > >    SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
> > >    SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
> > >    SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT,
> > > false),
> > > +  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
> > >  };
> >
> > No need for ANY_CMPCCXADD, unless you _know_ dependent features will
> > appear.
> > See e.g. FSGSBASE, i.e. you can use CMPCCXADD twice here.
>
> Changed to CMPCCXADD. BTW, do we need to remove them in i386-gen.c?

Since it isn't used, please remove it.

> >
> > > --- a/opcodes/i386-dis.c
> > > +++ b/opcodes/i386-dis.c
> > > @@ -366,6 +366,7 @@ fetch_data (struct disassemble_info *info,
> > > bfd_byte *addr)  #define Ma { OP_M, a_mode }  #define Mb { OP_M,
> > > b_mode }  #define Md { OP_M, d_mode }
> > > +#define Mdq { OP_M, dq_mode }
> >
> > You're decoding via mod_table[], so I don't think you need this. Or (perhaps
> > better) vice versa - keep this (if there's no pre-existing one that fits) and avoid
> > the decode step through mod_table[].
>
> Yes, OP_M will check modrm by itself, removed the pass of mod_table.
>
> >
> > > @@ -939,6 +940,22 @@ enum
> > >    MOD_VEX_0F388E,
> > >    MOD_VEX_0F38B0,
> > >    MOD_VEX_0F38B1,
> > > +  MOD_VEX_0F38E0_X86_64,
> > > +  MOD_VEX_0F38E1_X86_64,
> > > +  MOD_VEX_0F38E2_X86_64,
> > > +  MOD_VEX_0F38E3_X86_64,
> > > +  MOD_VEX_0F38E4_X86_64,
> > > +  MOD_VEX_0F38E5_X86_64,
> > > +  MOD_VEX_0F38E6_X86_64,
> > > +  MOD_VEX_0F38E7_X86_64,
> > > +  MOD_VEX_0F38E8_X86_64,
> > > +  MOD_VEX_0F38E9_X86_64,
> > > +  MOD_VEX_0F38EA_X86_64,
> > > +  MOD_VEX_0F38EB_X86_64,
> > > +  MOD_VEX_0F38EC_X86_64,
> > > +  MOD_VEX_0F38ED_X86_64,
> > > +  MOD_VEX_0F38EE_X86_64,
> > > +  MOD_VEX_0F38EF_X86_64,
> >
> > Hmm, I really need to split off (and re-submit) the re-usable parts of
> > "x86-64: Intel64 adjustments for conditional jumps" (see
> > https://sourceware.org/pipermail/binutils/2020-July/112365.html), to avoid the
> > need for 16 almost identical entries of several kinds throughout this patch.
>
> Currently I am still using 16 almost identical entries. We can put this in further
> discussion.
>
> >
> > > @@ -8480,6 +8609,70 @@ static const struct dis386 mod_table[][2] = {
> > >      /* MOD_VEX_0F38B1*/
> > >      { VEX_W_TABLE (VEX_W_0F38B1) },
> > >    },
> > > +  {
> > > +    /* MOD_VEX_0F38E0_X86_64 */
> > > +    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > > +    /* MOD_VEX_0F38E1_X86_64 */
> > > +    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > > +    /* MOD_VEX_0F38E2_X86_64 */
> > > +    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },  },  {
> > > +    /* MOD_VEX_0F38E3_X86_64 */
> > > +    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
> >
> > I understand the ISA extensions document names the insn this way and doesn't
> > list cmpaexadd (same for other aliases), but I think this is a mistake in the doc.
> > I've raised a respective question in the ISA extensions forum: I think
> > representation of conditions to check for should be uniform among insns, and
> > hence it should be "ae" here. (That would also be the effect if you
> > used %C<whatever> here.)
>
> I changed the table to <cc> so that when developer input something like
> cmpaexadd, assembler could also recognize it. For the disassembler part, it still
> only have one identical name.
>
> >
> > > @@ -433,7 +436,7 @@ typedef union i386_cpu_flags
> > >        unsigned int cpu64:1;
> > >        unsigned int cpuno64:1;
> > >  #ifdef CpuUnused
> > > -      unsigned int unused:(CpuNumOfBits - CpuUnused);
> > > +      // unsigned int unused:(CpuNumOfBits - CpuUnused);
> > >  #endif
> >
> > No - you should instead comment out the #define of CpuUnused - see the
> > comment there.
>
> Fixed this wrong comment.
>
> >
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3296,3 +3296,24 @@ vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8,
> > > Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
> > >  vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8,
> > >
> > Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|N
> > o_lSuf
> > > |No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex,
> > > RegXMM|RegYMM, RegXMM|RegYMM }
> > >
> > >  // AVX_VNNI_INT8 instructions end.
> > > +
> > > +// CMPCCXADD instructions.
> > > +
> > > +cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64,
> > >
> > +Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No
> > _lSuf|
> > > +No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64,
> > > +Dword|Qword|Unspecified|BaseIndex }
> >
> > Along the lines of the earlier comment - you want to use the <cc> template here,
> > eliminating the need for 16 almost identical lines _and_ supplying all condition
> > code representation in one go.
>
> Mentioned above.
>
> >
> > Apart from that you forgot CheckRegSize here afaict. And please again VexVVVV
> > alone, without =1. Also for non-vector insns perhaps better plain Vex instead of
> > Vex128. Further these insns should allow for l and q suffixes in AT&T mode.
>
> Done.
>
> >
> > And finally - is SwapSources really appropriate to use here? There's only one
> > pure source operand, the other two are also serving as destinations.
> > I wonder whether an attribute is necessary here in the first place: Vex- encoded
> > insns with a memory destination never have two further register operands, so
> > that property should suffice for identifying the case in build_modrm_byte().
> > Alternatively you could also simply use the CPU flag.
>
> We may need a special identifier for CMPccXADD since we have VVVV at
> operand 3, where it is always at operand 2 for all other insts which
> have VVVV. That is the reason we reuse SwapSources. It might be not
> that same as the original meaning. But we want to avoid adding a bit
> for this very rare case. Do we need to change that?
>
> Haochen
>
> >
> > Jan
Jan Beulich Oct. 25, 2022, 6:53 a.m. UTC | #11 
On 24.10.2022 07:55, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Friday, October 14, 2022 9:47 PM
>>
>> On 14.10.2022 11:12, Haochen Jiang wrote:
>> And finally - is SwapSources really appropriate to use here? There's only one
>> pure source operand, the other two are also serving as destinations.
>> I wonder whether an attribute is necessary here in the first place: Vex- encoded
>> insns with a memory destination never have two further register operands, so
>> that property should suffice for identifying the case in build_modrm_byte().
>> Alternatively you could also simply use the CPU flag.
> 
> We may need a special identifier for CMPccXADD since we have VVVV at
> operand 3, where it is always at operand 2 for all other insts which
> have VVVV. That is the reason we reuse SwapSources. It might be not
> that same as the original meaning. But we want to avoid adding a bit
> for this very rare case. Do we need to change that?

Re-using existing attributes is certainly preferred. But the question here
was whether _any_ special attribute is needed. Did you try out my suggestion,
and it didn't work out for some reason? Avoiding the (ab)use of an
inappropriately (for the purpose here) named attribute would imo be preferable.

Jan
Frager, Neal via Binutils Oct. 26, 2022, 3:03 a.m. UTC | #12 
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, October 25, 2022 2:53 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> 
> On 24.10.2022 07:55, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Friday, October 14, 2022 9:47 PM
> >>
> >> On 14.10.2022 11:12, Haochen Jiang wrote:
> >> And finally - is SwapSources really appropriate to use here? There's only
> one
> >> pure source operand, the other two are also serving as destinations.
> >> I wonder whether an attribute is necessary here in the first place: Vex-
> encoded
> >> insns with a memory destination never have two further register
> operands, so
> >> that property should suffice for identifying the case in
> build_modrm_byte().
> >> Alternatively you could also simply use the CPU flag.
> >
> > We may need a special identifier for CMPccXADD since we have VVVV at
> > operand 3, where it is always at operand 2 for all other insts which
> > have VVVV. That is the reason we reuse SwapSources. It might be not
> > that same as the original meaning. But we want to avoid adding a bit
> > for this very rare case. Do we need to change that?
> 
> Re-using existing attributes is certainly preferred. But the question here
> was whether _any_ special attribute is needed. Did you try out my
> suggestion,
> and it didn't work out for some reason? Avoiding the (ab)use of an
> inappropriately (for the purpose here) named attribute would imo be
> preferable.

Actually we have some similar instructions. For example, vmaskmovps/d.
It could also take one memory operand as dest and two register operands
as source.

However, cmp<cc>xadd has a different encoding pattern with it. The default
behavior for previous insts like vmaskmovps/d in Intel syntax is to encode
first register operand as vvvv and second register operand as modrm:reg.
In cmp<cc>xadd, it is swapped, with first register operand as modrm:reg and
second register operand as vvvv. I suppose it makes sense to use SwapSource
and it is quite hard or might be dirty to just use the number of registers to
identify them in build_modrm_byte().

Haochen

> 
> Jan
Jan Beulich Oct. 26, 2022, 8:49 a.m. UTC | #13 
On 26.10.2022 05:03, Jiang, Haochen wrote:
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Tuesday, October 25, 2022 2:53 PM
>> To: Jiang, Haochen <haochen.jiang@intel.com>
>> Cc: hjl.tools@gmail.com; binutils@sourceware.org
>> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
>>
>> On 24.10.2022 07:55, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Friday, October 14, 2022 9:47 PM
>>>>
>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>> And finally - is SwapSources really appropriate to use here? There's only
>> one
>>>> pure source operand, the other two are also serving as destinations.
>>>> I wonder whether an attribute is necessary here in the first place: Vex-
>> encoded
>>>> insns with a memory destination never have two further register
>> operands, so
>>>> that property should suffice for identifying the case in
>> build_modrm_byte().
>>>> Alternatively you could also simply use the CPU flag.
>>>
>>> We may need a special identifier for CMPccXADD since we have VVVV at
>>> operand 3, where it is always at operand 2 for all other insts which
>>> have VVVV. That is the reason we reuse SwapSources. It might be not
>>> that same as the original meaning. But we want to avoid adding a bit
>>> for this very rare case. Do we need to change that?
>>
>> Re-using existing attributes is certainly preferred. But the question here
>> was whether _any_ special attribute is needed. Did you try out my
>> suggestion,
>> and it didn't work out for some reason? Avoiding the (ab)use of an
>> inappropriately (for the purpose here) named attribute would imo be
>> preferable.
> 
> Actually we have some similar instructions. For example, vmaskmovps/d.
> It could also take one memory operand as dest and two register operands
> as source.

As you say there are two _source_ operands here, whereas ...

> However, cmp<cc>xadd has a different encoding pattern with it. The default
> behavior for previous insts like vmaskmovps/d in Intel syntax is to encode
> first register operand as vvvv and second register operand as modrm:reg.
> In cmp<cc>xadd, it is swapped, with first register operand as modrm:reg and
> second register operand as vvvv. I suppose it makes sense to use SwapSource
> and it is quite hard or might be dirty to just use the number of registers to
> identify them in build_modrm_byte().

... this has two destinations (memory and a register). Which is why using
SwapSource at best is a slight abuse (which, as said, I'd prefer to avoid).
But yes, I agree that going _just_ from a memory destination with two
further register ops is not sufficient.

Seeing what H.J. and I are suggesting for the PREFETCHI change: How about
using the CPU flag in the conditional that you add?

Jan
Frager, Neal via Binutils Oct. 27, 2022, 3:09 a.m. UTC | #14 
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, October 26, 2022 4:50 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> 
> On 26.10.2022 05:03, Jiang, Haochen wrote:
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Tuesday, October 25, 2022 2:53 PM
> >> To: Jiang, Haochen <haochen.jiang@intel.com>
> >> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> >> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> >>
> >> On 24.10.2022 07:55, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Friday, October 14, 2022 9:47 PM
> >>>>
> >>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>> And finally - is SwapSources really appropriate to use here?
> >>>> There's only
> >> one
> >>>> pure source operand, the other two are also serving as destinations.
> >>>> I wonder whether an attribute is necessary here in the first place:
> >>>> Vex-
> >> encoded
> >>>> insns with a memory destination never have two further register
> >> operands, so
> >>>> that property should suffice for identifying the case in
> >> build_modrm_byte().
> >>>> Alternatively you could also simply use the CPU flag.
> >>>
> >>> We may need a special identifier for CMPccXADD since we have VVVV at
> >>> operand 3, where it is always at operand 2 for all other insts which
> >>> have VVVV. That is the reason we reuse SwapSources. It might be not
> >>> that same as the original meaning. But we want to avoid adding a bit
> >>> for this very rare case. Do we need to change that?
> >>
> >> Re-using existing attributes is certainly preferred. But the question
> >> here was whether _any_ special attribute is needed. Did you try out
> >> my suggestion, and it didn't work out for some reason? Avoiding the
> >> (ab)use of an inappropriately (for the purpose here) named attribute
> >> would imo be preferable.
> >
> > Actually we have some similar instructions. For example, vmaskmovps/d.
> > It could also take one memory operand as dest and two register
> > operands as source.
> 
> As you say there are two _source_ operands here, whereas ...
> 
> > However, cmp<cc>xadd has a different encoding pattern with it. The
> > default behavior for previous insts like vmaskmovps/d in Intel syntax
> > is to encode first register operand as vvvv and second register operand as
> modrm:reg.
> > In cmp<cc>xadd, it is swapped, with first register operand as
> > modrm:reg and second register operand as vvvv. I suppose it makes
> > sense to use SwapSource and it is quite hard or might be dirty to just
> > use the number of registers to identify them in build_modrm_byte().
> 
> ... this has two destinations (memory and a register). Which is why using
> SwapSource at best is a slight abuse (which, as said, I'd prefer to avoid).
> But yes, I agree that going _just_ from a memory destination with two
> further register ops is not sufficient.
> 
> Seeing what H.J. and I are suggesting for the PREFETCHI change: How about
> using the CPU flag in the conditional that you add?

That is ok for me. I suppose the cmpccxadd might be the special one for very
long time. 

However, the potential problem is when the same scenario happen again. We
will have to add another cpuid at that condition again, which is a little dirty.

Haochen

> 
> Jan
Jan Beulich Oct. 27, 2022, 6:37 a.m. UTC | #15 
On 27.10.2022 05:09, Jiang, Haochen wrote:
> 
> 
>> -----Original Message-----
>> From: Jan Beulich <jbeulich@suse.com>
>> Sent: Wednesday, October 26, 2022 4:50 PM
>> To: Jiang, Haochen <haochen.jiang@intel.com>
>> Cc: hjl.tools@gmail.com; binutils@sourceware.org
>> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
>>
>> On 26.10.2022 05:03, Jiang, Haochen wrote:
>>>> -----Original Message-----
>>>> From: Jan Beulich <jbeulich@suse.com>
>>>> Sent: Tuesday, October 25, 2022 2:53 PM
>>>> To: Jiang, Haochen <haochen.jiang@intel.com>
>>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org
>>>> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
>>>>
>>>> On 24.10.2022 07:55, Jiang, Haochen wrote:
>>>>>> -----Original Message-----
>>>>>> From: Jan Beulich <jbeulich@suse.com>
>>>>>> Sent: Friday, October 14, 2022 9:47 PM
>>>>>>
>>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
>>>>>> And finally - is SwapSources really appropriate to use here?
>>>>>> There's only
>>>> one
>>>>>> pure source operand, the other two are also serving as destinations.
>>>>>> I wonder whether an attribute is necessary here in the first place:
>>>>>> Vex-
>>>> encoded
>>>>>> insns with a memory destination never have two further register
>>>> operands, so
>>>>>> that property should suffice for identifying the case in
>>>> build_modrm_byte().
>>>>>> Alternatively you could also simply use the CPU flag.
>>>>>
>>>>> We may need a special identifier for CMPccXADD since we have VVVV at
>>>>> operand 3, where it is always at operand 2 for all other insts which
>>>>> have VVVV. That is the reason we reuse SwapSources. It might be not
>>>>> that same as the original meaning. But we want to avoid adding a bit
>>>>> for this very rare case. Do we need to change that?
>>>>
>>>> Re-using existing attributes is certainly preferred. But the question
>>>> here was whether _any_ special attribute is needed. Did you try out
>>>> my suggestion, and it didn't work out for some reason? Avoiding the
>>>> (ab)use of an inappropriately (for the purpose here) named attribute
>>>> would imo be preferable.
>>>
>>> Actually we have some similar instructions. For example, vmaskmovps/d.
>>> It could also take one memory operand as dest and two register
>>> operands as source.
>>
>> As you say there are two _source_ operands here, whereas ...
>>
>>> However, cmp<cc>xadd has a different encoding pattern with it. The
>>> default behavior for previous insts like vmaskmovps/d in Intel syntax
>>> is to encode first register operand as vvvv and second register operand as
>> modrm:reg.
>>> In cmp<cc>xadd, it is swapped, with first register operand as
>>> modrm:reg and second register operand as vvvv. I suppose it makes
>>> sense to use SwapSource and it is quite hard or might be dirty to just
>>> use the number of registers to identify them in build_modrm_byte().
>>
>> ... this has two destinations (memory and a register). Which is why using
>> SwapSource at best is a slight abuse (which, as said, I'd prefer to avoid).
>> But yes, I agree that going _just_ from a memory destination with two
>> further register ops is not sufficient.
>>
>> Seeing what H.J. and I are suggesting for the PREFETCHI change: How about
>> using the CPU flag in the conditional that you add?
> 
> That is ok for me. I suppose the cmpccxadd might be the special one for very
> long time. 
> 
> However, the potential problem is when the same scenario happen again. We
> will have to add another cpuid at that condition again, which is a little dirty.

I guess we can decide at that point whether a 2nd CPU check is preferable
over whatever alternative.

Jan
Frager, Neal via Binutils Oct. 28, 2022, 12:59 a.m. UTC | #16 
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Thursday, October 27, 2022 2:38 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> 
> On 27.10.2022 05:09, Jiang, Haochen wrote:
> >
> >
> >> -----Original Message-----
> >> From: Jan Beulich <jbeulich@suse.com>
> >> Sent: Wednesday, October 26, 2022 4:50 PM
> >> To: Jiang, Haochen <haochen.jiang@intel.com>
> >> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> >> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> >>
> >> On 26.10.2022 05:03, Jiang, Haochen wrote:
> >>>> -----Original Message-----
> >>>> From: Jan Beulich <jbeulich@suse.com>
> >>>> Sent: Tuesday, October 25, 2022 2:53 PM
> >>>> To: Jiang, Haochen <haochen.jiang@intel.com>
> >>>> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> >>>> Subject: Re: [PATCH 04/10] Support Intel CMPccXADD
> >>>>
> >>>> On 24.10.2022 07:55, Jiang, Haochen wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Jan Beulich <jbeulich@suse.com>
> >>>>>> Sent: Friday, October 14, 2022 9:47 PM
> >>>>>>
> >>>>>> On 14.10.2022 11:12, Haochen Jiang wrote:
> >>>>>> And finally - is SwapSources really appropriate to use here?
> >>>>>> There's only
> >>>> one
> >>>>>> pure source operand, the other two are also serving as destinations.
> >>>>>> I wonder whether an attribute is necessary here in the first place:
> >>>>>> Vex-
> >>>> encoded
> >>>>>> insns with a memory destination never have two further register
> >>>> operands, so
> >>>>>> that property should suffice for identifying the case in
> >>>> build_modrm_byte().
> >>>>>> Alternatively you could also simply use the CPU flag.
> >>>>>
> >>>>> We may need a special identifier for CMPccXADD since we have VVVV
> >>>>> at operand 3, where it is always at operand 2 for all other insts
> >>>>> which have VVVV. That is the reason we reuse SwapSources. It might
> >>>>> be not that same as the original meaning. But we want to avoid
> >>>>> adding a bit for this very rare case. Do we need to change that?
> >>>>
> >>>> Re-using existing attributes is certainly preferred. But the
> >>>> question here was whether _any_ special attribute is needed. Did
> >>>> you try out my suggestion, and it didn't work out for some reason?
> >>>> Avoiding the (ab)use of an inappropriately (for the purpose here)
> >>>> named attribute would imo be preferable.
> >>>
> >>> Actually we have some similar instructions. For example, vmaskmovps/d.
> >>> It could also take one memory operand as dest and two register
> >>> operands as source.
> >>
> >> As you say there are two _source_ operands here, whereas ...
> >>
> >>> However, cmp<cc>xadd has a different encoding pattern with it. The
> >>> default behavior for previous insts like vmaskmovps/d in Intel
> >>> syntax is to encode first register operand as vvvv and second
> >>> register operand as
> >> modrm:reg.
> >>> In cmp<cc>xadd, it is swapped, with first register operand as
> >>> modrm:reg and second register operand as vvvv. I suppose it makes
> >>> sense to use SwapSource and it is quite hard or might be dirty to
> >>> just use the number of registers to identify them in
> build_modrm_byte().
> >>
> >> ... this has two destinations (memory and a register). Which is why
> >> using SwapSource at best is a slight abuse (which, as said, I'd prefer to
> avoid).
> >> But yes, I agree that going _just_ from a memory destination with two
> >> further register ops is not sufficient.
> >>
> >> Seeing what H.J. and I are suggesting for the PREFETCHI change: How
> >> about using the CPU flag in the conditional that you add?
> >
> > That is ok for me. I suppose the cmpccxadd might be the special one
> > for very long time.
> >
> > However, the potential problem is when the same scenario happen again.
> > We will have to add another cpuid at that condition again, which is a little
> dirty.
> 
> I guess we can decide at that point whether a 2nd CPU check is preferable
> over whatever alternative.

That sounds reasonable. Thanks for the whole discussion.

Haochen

> 
> Jan
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index d5e06bd1de..9757209a9f 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for Intel CMPccXADD instructions.
+
 * Add support for Intel AVX-NE-CONVERT instructions.
 
 * Add support for Intel AVX-VNNI-INT8 instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 42579bb701..0d161d60ef 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1097,6 +1097,7 @@  static const arch_entry cpu_arch[] =
   SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
   SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
   SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
+  SUBARCH (cmpccxadd, CMPCCXADD, ANY_CMPCCXADD, false)
 };
 
 #undef SUBARCH
@@ -8568,6 +8569,12 @@  build_modrm_byte (void)
 		      gas_assert (mem == (vex_reg + 1)
 				  && op < i.operands);
 		    }
+		  else if (i.tm.opcode_modifier.swapsources)
+		    {
+		      /* Set Vex_reg as operand 0.  */
+		      vex_reg = op++;
+		      gas_assert(vex_reg < i.operands);
+		    }
 		  else
 		    {
 		      vex_reg = op + 1;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index a0204ca48d..62202157b3 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -216,6 +216,7 @@  accept various extension mnemonics.  For example,
 @code{avx_ifma},
 @code{avx_vnni_int8},
 @code{avx_ne_convert},
+@code{cmpccxadd},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -239,6 +240,7 @@  accept various extension mnemonics.  For example,
 @code{noavx_ifma},
 @code{noavx_vnni_int8},
 @code{noavx_ne_convert},
+@code{nocmpccxadd},
 @code{noenqcmd},
 @code{noserialize},
 @code{notsxldtrk},
@@ -1540,6 +1542,7 @@  supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
 @item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
+@item @samp{.cmpccxadd}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.l b/gas/testsuite/gas/i386/cmpccxadd-inval.l
new file mode 100644
index 0000000000..32538867aa
--- /dev/null
+++ b/gas/testsuite/gas/i386/cmpccxadd-inval.l
@@ -0,0 +1,5 @@ 
+.* Assembler messages:
+.*:6: Error: `cmpbexadd' is only supported in 64-bit mode
+.*:7: Error: `cmpbxadd' is only supported in 64-bit mode
+.*:8: Error: `cmplexadd' is only supported in 64-bit mode
+.*:9: Error: `cmplxadd' is only supported in 64-bit mode
diff --git a/gas/testsuite/gas/i386/cmpccxadd-inval.s b/gas/testsuite/gas/i386/cmpccxadd-inval.s
new file mode 100644
index 0000000000..a349628863
--- /dev/null
+++ b/gas/testsuite/gas/i386/cmpccxadd-inval.s
@@ -0,0 +1,9 @@ 
+# Check Illegal CMPccXADD instructions
+
+	.allow_index_reg
+	.text
+_start:
+	cmpbexadd	%eax, %eax, 0x10000000(%esp, %esi, 8)
+	cmpbxadd	%ebx, %ebx, (%ecx)
+	cmplexadd	%eax, %eax, 508(%ecx)
+	cmplxadd	%ebx, %ebx, -512(%edx)
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index d03c2187ea..fb2e2aa446 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -485,6 +485,7 @@  if [gas_32_check] then {
     run_dump_test "avx-vnni-int8-intel"
     run_dump_test "avx-ne-convert"
     run_dump_test "avx-ne-convert-intel"
+    run_list_test "cmpccxadd-inval"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
@@ -1159,6 +1160,8 @@  if [gas_64_check] then {
     run_dump_test "x86-64-avx-vnni-int8-intel"
     run_dump_test "x86-64-avx-ne-convert"
     run_dump_test "x86-64-avx-ne-convert-intel"
+    run_dump_test "x86-64-cmpccxadd"
+    run_dump_test "x86-64-cmpccxadd-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
new file mode 100644
index 0000000000..0b906330b7
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd-intel.d
@@ -0,0 +1,266 @@ 
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 CMPCCXADD insns (Intel disassembly)
+#source: x86-64-cmpccxadd.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd QWORD PTR \[rdx-0x400\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd DWORD PTR \[rbp\+r14\*8\+0x10000000\],ecx,eax
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd DWORD PTR \[r9\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd DWORD PTR \[rcx\+0x1fc\],ecx,eax
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd DWORD PTR \[rdx-0x200\],ecx,ebx
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd QWORD PTR \[rbp\+r14\*8\+0x10000000\],rcx,rax
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd QWORD PTR \[r9\],rcx,rbx
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd QWORD PTR \[rcx\+0x3f8\],rcx,rax
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd QWORD PTR \[rdx-0x400\],rcx,rbx
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.d b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
new file mode 100644
index 0000000000..b24af38d1c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.d
@@ -0,0 +1,266 @@ 
+#as:
+#objdump: -dw
+#name: x86_64 CMPCCXADD insns
+#source: x86-64-cmpccxadd.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e6 8c f5 00 00 00 10\s+cmpbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e6 09\s+cmpbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e6 89 fc 01 00 00\s+cmpbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e6 8a 00 fe ff ff\s+cmpbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e6 8c f5 00 00 00 10\s+cmpbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e6 09\s+cmpbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e6 89 f8 03 00 00\s+cmpbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e6 8a 00 fc ff ff\s+cmpbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e2 8c f5 00 00 00 10\s+cmpbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e2 09\s+cmpbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e2 89 fc 01 00 00\s+cmpbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e2 8a 00 fe ff ff\s+cmpbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e2 8c f5 00 00 00 10\s+cmpbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e2 09\s+cmpbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e2 89 f8 03 00 00\s+cmpbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e2 8a 00 fc ff ff\s+cmpbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ee 8c f5 00 00 00 10\s+cmplexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ee 09\s+cmplexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ee 89 fc 01 00 00\s+cmplexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ee 8a 00 fe ff ff\s+cmplexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ee 8c f5 00 00 00 10\s+cmplexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ee 09\s+cmplexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ee 89 f8 03 00 00\s+cmplexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ee 8a 00 fc ff ff\s+cmplexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ec 8c f5 00 00 00 10\s+cmplxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ec 09\s+cmplxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ec 89 fc 01 00 00\s+cmplxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ec 8a 00 fe ff ff\s+cmplxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ec 8c f5 00 00 00 10\s+cmplxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ec 09\s+cmplxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ec 89 f8 03 00 00\s+cmplxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ec 8a 00 fc ff ff\s+cmplxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e7 8c f5 00 00 00 10\s+cmpnbexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e7 09\s+cmpnbexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e7 89 fc 01 00 00\s+cmpnbexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e7 8a 00 fe ff ff\s+cmpnbexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e7 8c f5 00 00 00 10\s+cmpnbexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e7 09\s+cmpnbexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e7 89 f8 03 00 00\s+cmpnbexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e7 8a 00 fc ff ff\s+cmpnbexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e3 8c f5 00 00 00 10\s+cmpnbxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e3 09\s+cmpnbxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e3 89 fc 01 00 00\s+cmpnbxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e3 8a 00 fe ff ff\s+cmpnbxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e3 8c f5 00 00 00 10\s+cmpnbxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e3 09\s+cmpnbxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e3 89 f8 03 00 00\s+cmpnbxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e3 8a 00 fc ff ff\s+cmpnbxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ef 8c f5 00 00 00 10\s+cmpnlexadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ef 09\s+cmpnlexadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ef 89 fc 01 00 00\s+cmpnlexadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ef 8a 00 fe ff ff\s+cmpnlexadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ef 8c f5 00 00 00 10\s+cmpnlexadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ef 09\s+cmpnlexadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ef 89 f8 03 00 00\s+cmpnlexadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ef 8a 00 fc ff ff\s+cmpnlexadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ed 8c f5 00 00 00 10\s+cmpnlxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ed 09\s+cmpnlxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ed 89 fc 01 00 00\s+cmpnlxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ed 8a 00 fe ff ff\s+cmpnlxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ed 8c f5 00 00 00 10\s+cmpnlxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ed 09\s+cmpnlxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ed 89 f8 03 00 00\s+cmpnlxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ed 8a 00 fc ff ff\s+cmpnlxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e1 8c f5 00 00 00 10\s+cmpnoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e1 09\s+cmpnoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e1 89 fc 01 00 00\s+cmpnoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e1 8a 00 fe ff ff\s+cmpnoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e1 8c f5 00 00 00 10\s+cmpnoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e1 09\s+cmpnoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e1 89 f8 03 00 00\s+cmpnoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e1 8a 00 fc ff ff\s+cmpnoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 eb 8c f5 00 00 00 10\s+cmpnpxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 eb 09\s+cmpnpxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 eb 89 fc 01 00 00\s+cmpnpxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 eb 8a 00 fe ff ff\s+cmpnpxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 eb 8c f5 00 00 00 10\s+cmpnpxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 eb 09\s+cmpnpxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 eb 89 f8 03 00 00\s+cmpnpxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 eb 8a 00 fc ff ff\s+cmpnpxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e9 8c f5 00 00 00 10\s+cmpnsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e9 09\s+cmpnsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e9 89 fc 01 00 00\s+cmpnsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e9 8a 00 fe ff ff\s+cmpnsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e9 8c f5 00 00 00 10\s+cmpnsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e9 09\s+cmpnsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e9 89 f8 03 00 00\s+cmpnsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e9 8a 00 fc ff ff\s+cmpnsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e5 8c f5 00 00 00 10\s+cmpnzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e5 09\s+cmpnzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e5 89 fc 01 00 00\s+cmpnzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e5 8a 00 fe ff ff\s+cmpnzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e5 8c f5 00 00 00 10\s+cmpnzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e5 09\s+cmpnzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e5 89 f8 03 00 00\s+cmpnzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e5 8a 00 fc ff ff\s+cmpnzxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e0 8c f5 00 00 00 10\s+cmpoxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e0 09\s+cmpoxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e0 89 fc 01 00 00\s+cmpoxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e0 8a 00 fe ff ff\s+cmpoxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e0 8c f5 00 00 00 10\s+cmpoxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e0 09\s+cmpoxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e0 89 f8 03 00 00\s+cmpoxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e0 8a 00 fc ff ff\s+cmpoxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 ea 8c f5 00 00 00 10\s+cmppxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 ea 09\s+cmppxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 ea 89 fc 01 00 00\s+cmppxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 ea 8a 00 fe ff ff\s+cmppxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 ea 8c f5 00 00 00 10\s+cmppxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 ea 09\s+cmppxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 ea 89 f8 03 00 00\s+cmppxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 ea 8a 00 fc ff ff\s+cmppxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e8 8c f5 00 00 00 10\s+cmpsxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e8 09\s+cmpsxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e8 89 fc 01 00 00\s+cmpsxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e8 8a 00 fe ff ff\s+cmpsxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e8 8c f5 00 00 00 10\s+cmpsxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e8 09\s+cmpsxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e8 89 f8 03 00 00\s+cmpsxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e8 8a 00 fc ff ff\s+cmpsxadd %rbx,%rcx,-0x400\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 79 e4 8c f5 00 00 00 10\s+cmpzxadd %eax,%ecx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 61 e4 09\s+cmpzxadd %ebx,%ecx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 79 e4 89 fc 01 00 00\s+cmpzxadd %eax,%ecx,0x1fc\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 61 e4 8a 00 fe ff ff\s+cmpzxadd %ebx,%ecx,-0x200\(%rdx\)
+\s*[a-f0-9]+:\s*c4 a2 f9 e4 8c f5 00 00 00 10\s+cmpzxadd %rax,%rcx,0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*c4 c2 e1 e4 09\s+cmpzxadd %rbx,%rcx,\(%r9\)
+\s*[a-f0-9]+:\s*c4 e2 f9 e4 89 f8 03 00 00\s+cmpzxadd %rax,%rcx,0x3f8\(%rcx\)
+\s*[a-f0-9]+:\s*c4 e2 e1 e4 8a 00 fc ff ff\s+cmpzxadd %rbx,%rcx,-0x400\(%rdx\)
diff --git a/gas/testsuite/gas/i386/x86-64-cmpccxadd.s b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s
new file mode 100644
index 0000000000..f2eb84a1a3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-cmpccxadd.s
@@ -0,0 +1,263 @@ 
+# Check 64bit CMPccXADD instructions
+
+	.allow_index_reg
+	.text
+_start:
+	cmpbexadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpbexadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpbexadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpbexadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpbexadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpbexadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpbexadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpbexadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpbxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpbxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpbxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpbxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpbxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpbxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpbxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpbxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmplexadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmplexadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmplexadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmplexadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmplexadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmplexadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmplexadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmplexadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmplxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmplxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmplxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmplxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmplxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmplxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmplxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmplxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnbexadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnbexadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnbexadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnbexadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnbexadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnbexadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnbexadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnbexadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnbxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnbxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnbxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnbxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnbxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnbxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnbxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnbxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnlexadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnlexadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnlexadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnlexadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnlexadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnlexadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnlexadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnlexadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnlxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnlxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnlxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnlxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnlxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnlxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnlxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnlxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnoxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnoxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnoxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnoxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnoxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnoxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnoxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnoxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnpxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnpxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnpxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnpxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnpxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnpxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnpxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnpxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnsxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnsxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnsxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnsxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnsxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnsxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnsxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnsxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpnzxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnzxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpnzxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpnzxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpnzxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpnzxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpnzxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpnzxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpoxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpoxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpoxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpoxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpoxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpoxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpoxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpoxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmppxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmppxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmppxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmppxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmppxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmppxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmppxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmppxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpsxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpsxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpsxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpsxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpsxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpsxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpsxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpsxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+	cmpzxadd	%eax, %ecx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpzxadd	%ebx, %ecx, (%r9)	 #CMPCCXADD
+	cmpzxadd	%eax, %ecx, 508(%rcx)	 #CMPCCXADD Disp32(fc010000)
+	cmpzxadd	%ebx, %ecx, -512(%rdx)	 #CMPCCXADD Disp32(00feffff)
+	cmpzxadd	%rax, %rcx, 0x10000000(%rbp, %r14, 8)	 #CMPCCXADD
+	cmpzxadd	%rbx, %rcx, (%r9)	 #CMPCCXADD
+	cmpzxadd	%rax, %rcx, 1016(%rcx)	 #CMPCCXADD Disp32(f8030000)
+	cmpzxadd	%rbx, %rcx, -1024(%rdx)	 #CMPCCXADD Disp32(00fcffff)
+
+.intel_syntax noprefix
+	cmpbexadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpbexadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpbexadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpbexadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpbexadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpbexadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpbexadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpbexadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpbxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpbxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpbxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpbxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpbxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpbxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpbxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpbxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmplexadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmplexadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmplexadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmplexadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmplexadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmplexadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmplexadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmplexadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmplxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmplxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmplxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmplxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmplxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmplxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmplxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmplxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnbexadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnbexadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnbexadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnbexadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnbexadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnbexadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnbexadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnbexadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnbxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnbxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnbxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnbxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnbxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnbxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnbxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnbxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnlexadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnlexadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnlexadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnlexadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnlexadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnlexadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnlexadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnlexadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnlxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnlxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnlxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnlxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnlxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnlxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnlxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnlxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnoxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnoxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnoxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnoxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnoxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnoxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnoxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnoxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnpxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnpxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnpxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnpxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnpxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnpxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnpxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnpxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnsxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnsxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnsxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnsxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnsxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnsxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnsxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnsxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpnzxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpnzxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpnzxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpnzxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpnzxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpnzxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpnzxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpnzxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpoxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpoxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpoxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpoxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpoxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpoxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpoxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpoxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmppxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmppxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmppxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmppxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmppxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmppxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmppxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmppxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpsxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpsxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpsxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpsxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpsxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpsxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpsxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpsxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
+	cmpzxadd	DWORD PTR [rbp+r14*8+0x10000000], ecx, eax	 #CMPCCXADD
+	cmpzxadd	DWORD PTR [r9], ecx, ebx	 #CMPCCXADD
+	cmpzxadd	DWORD PTR [rcx+508], ecx, eax	 #CMPCCXADD Disp32(fc010000)
+	cmpzxadd	DWORD PTR [rdx-512], ecx, ebx	 #CMPCCXADD Disp32(00feffff)
+	cmpzxadd	QWORD PTR [rbp+r14*8+0x10000000], rcx, rax	 #CMPCCXADD
+	cmpzxadd	QWORD PTR [r9], rcx, rbx	 #CMPCCXADD
+	cmpzxadd	QWORD PTR [rcx+1016], rcx, rax	 #CMPCCXADD Disp32(f8030000)
+	cmpzxadd	QWORD PTR [rdx-1024], rcx, rbx	 #CMPCCXADD Disp32(00fcffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index e0e99c83b9..37bbbd3815 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -366,6 +366,7 @@  fetch_data (struct disassemble_info *info, bfd_byte *addr)
 #define Ma { OP_M, a_mode }
 #define Mb { OP_M, b_mode }
 #define Md { OP_M, d_mode }
+#define Mdq { OP_M, dq_mode }
 #define Mo { OP_M, o_mode }
 #define Mp { OP_M, f_mode }		/* 32 or 48 bit memory operand for LDS, LES etc */
 #define Mq { OP_M, q_mode }
@@ -939,6 +940,22 @@  enum
   MOD_VEX_0F388E,
   MOD_VEX_0F38B0,
   MOD_VEX_0F38B1,
+  MOD_VEX_0F38E0_X86_64,
+  MOD_VEX_0F38E1_X86_64,
+  MOD_VEX_0F38E2_X86_64,
+  MOD_VEX_0F38E3_X86_64,
+  MOD_VEX_0F38E4_X86_64,
+  MOD_VEX_0F38E5_X86_64,
+  MOD_VEX_0F38E6_X86_64,
+  MOD_VEX_0F38E7_X86_64,
+  MOD_VEX_0F38E8_X86_64,
+  MOD_VEX_0F38E9_X86_64,
+  MOD_VEX_0F38EA_X86_64,
+  MOD_VEX_0F38EB_X86_64,
+  MOD_VEX_0F38EC_X86_64,
+  MOD_VEX_0F38ED_X86_64,
+  MOD_VEX_0F38EE_X86_64,
+  MOD_VEX_0F38EF_X86_64,
   MOD_VEX_0F3A30_L_0,
   MOD_VEX_0F3A31_L_0,
   MOD_VEX_0F3A32_L_0,
@@ -1281,7 +1298,23 @@  enum
   X86_64_VEX_0F3849,
   X86_64_VEX_0F384B,
   X86_64_VEX_0F385C,
-  X86_64_VEX_0F385E
+  X86_64_VEX_0F385E,
+  X86_64_VEX_0F38E0,
+  X86_64_VEX_0F38E1,
+  X86_64_VEX_0F38E2,
+  X86_64_VEX_0F38E3,
+  X86_64_VEX_0F38E4,
+  X86_64_VEX_0F38E5,
+  X86_64_VEX_0F38E6,
+  X86_64_VEX_0F38E7,
+  X86_64_VEX_0F38E8,
+  X86_64_VEX_0F38E9,
+  X86_64_VEX_0F38EA,
+  X86_64_VEX_0F38EB,
+  X86_64_VEX_0F38EC,
+  X86_64_VEX_0F38ED,
+  X86_64_VEX_0F38EE,
+  X86_64_VEX_0F38EF,
 };
 
 enum
@@ -4383,6 +4416,102 @@  static const struct dis386 x86_64_table[][2] = {
     { Bad_Opcode },
     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
   },
+
+  /* X86_64_VEX_0F38E0 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E0_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E1 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E1_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E2 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E2_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E3 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E3_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E4 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E4_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E5 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E5_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E6 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E6_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E7 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E7_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E8 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E8_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38E9 */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38E9_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38EA */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38EA_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38EB */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38EB_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38EC */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38EC_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38ED */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38ED_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38EE */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38EE_X86_64) },
+  },
+
+  /* X86_64_VEX_0F38EF */
+  {
+    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38EF_X86_64) },
+  },
 };
 
 static const struct dis386 three_byte_table[][256] = {
@@ -6394,23 +6523,23 @@  static const struct dis386 vex_table[][256] = {
     { "vaesdec",	{ XM, Vex, EXx }, PREFIX_DATA },
     { "vaesdeclast",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* e0 */
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_VEX_0F38E0) },
+    { X86_64_TABLE (X86_64_VEX_0F38E1) },
+    { X86_64_TABLE (X86_64_VEX_0F38E2) },
+    { X86_64_TABLE (X86_64_VEX_0F38E3) },
+    { X86_64_TABLE (X86_64_VEX_0F38E4) },
+    { X86_64_TABLE (X86_64_VEX_0F38E5) },
+    { X86_64_TABLE (X86_64_VEX_0F38E6) },
+    { X86_64_TABLE (X86_64_VEX_0F38E7) },
     /* e8 */
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_VEX_0F38E8) },
+    { X86_64_TABLE (X86_64_VEX_0F38E9) },
+    { X86_64_TABLE (X86_64_VEX_0F38EA) },
+    { X86_64_TABLE (X86_64_VEX_0F38EB) },
+    { X86_64_TABLE (X86_64_VEX_0F38EC) },
+    { X86_64_TABLE (X86_64_VEX_0F38ED) },
+    { X86_64_TABLE (X86_64_VEX_0F38EE) },
+    { X86_64_TABLE (X86_64_VEX_0F38EF) },
     /* f0 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -8480,6 +8609,70 @@  static const struct dis386 mod_table[][2] = {
     /* MOD_VEX_0F38B1*/
     { VEX_W_TABLE (VEX_W_0F38B1) },
   },
+  {
+    /* MOD_VEX_0F38E0_X86_64 */
+    { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E1_X86_64 */
+    { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E2_X86_64 */
+    { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E3_X86_64 */
+    { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E4_X86_64 */
+    { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E5_X86_64 */
+    { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E6_X86_64 */
+    { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E7_X86_64 */
+    { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E8_X86_64 */
+    { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38E9_X86_64 */
+    { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38EA_X86_64 */
+    { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38EB_X86_64 */
+    { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38EC_X86_64 */
+    { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38ED_X86_64 */
+    { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38EE_X86_64 */
+    { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
+  {
+    /* MOD_VEX_0F38EF_X86_64 */
+    { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
+  },
   {
     /* MOD_VEX_0F3A30_L_0 */
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 6c69ebf29b..96d8d2ceb8 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -251,6 +251,8 @@  static initializer cpu_flag_init[] =
     "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
   { "CPU_AVX_NE_CONVERT_FLAGS",
     "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
+  { "CPU_CMPCCXADD_FLAGS",
+    "CpuCMPCCXADD" },
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
   { "CPU_ADX_FLAGS",
@@ -451,6 +453,8 @@  static initializer cpu_flag_init[] =
     "CpuAVX_VNNI_INT8" },
   { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
     "CpuAVX_NE_CONVERT" },
+  { "CPU_ANY_CMPCCXADD_FLAGS",
+    "CpuCMPCCXADD" },
 };
 
 static initializer operand_type_init[] =
@@ -655,6 +659,7 @@  static bitfield cpu_flags[] =
   BITFIELD (CpuAVX_IFMA),
   BITFIELD (CpuAVX_VNNI_INT8),
   BITFIELD (CpuAVX_NE_CONVERT),
+  BITFIELD (CpuCMPCCXADD),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index c5212aaf12..052c59b162 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -215,6 +215,8 @@  enum
   CpuAVX_VNNI_INT8,
   /* Intel AVX NE CONVERT Instructions support required.  */
   CpuAVX_NE_CONVERT,
+  /* Intel CMPccXADD instructions support required.  */
+  CpuCMPCCXADD,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -397,6 +399,7 @@  typedef union i386_cpu_flags
       unsigned int cpuavx_ifma:1;
       unsigned int cpuavx_vnni_int8:1;
       unsigned int cpuavx_ne_convert:1;
+      unsigned int cpucmpccxadd:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
@@ -433,7 +436,7 @@  typedef union i386_cpu_flags
       unsigned int cpu64:1;
       unsigned int cpuno64:1;
 #ifdef CpuUnused
-      unsigned int unused:(CpuNumOfBits - CpuUnused);
+      // unsigned int unused:(CpuNumOfBits - CpuUnused);
 #endif
     } bitfield;
   unsigned int array[CpuNumOfUints];
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index daff6669de..2b704708a4 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3296,3 +3296,24 @@  vpdpbsud, 0xf350, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|Chec
 vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT8, Modrm|Vex|Space0F38|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|Unspecified|BaseIndex, RegXMM|RegYMM, RegXMM|RegYMM }
 
 // AVX_VNNI_INT8 instructions end.
+
+// CMPCCXADD instructions.
+
+cmpbexadd, 0x66e6, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpbxadd, 0x66e2, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmplexadd, 0x66ee, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmplxadd, 0x66ec, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnbexadd, 0x66e7, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnbxadd, 0x66e3, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnlexadd, 0x66ef, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnlxadd, 0x66ed, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnoxadd, 0x66e1, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnpxadd, 0x66eb, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnsxadd, 0x66e9, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpnzxadd, 0x66e5, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpoxadd, 0x66e0, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmppxadd, 0x66ea, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpsxadd, 0x66e8, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+cmpzxadd, 0x66e4, None, CpuCMPCCXADD|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|SwapSources|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Reg64, Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
+
+// CMPCCXADD instructions end.