diff mbox series

[03/10] Support Intel AVX-NE-CONVERT

Message ID 20221014091248.4920-4-haochen.jiang@intel.com
State Accepted
Headers
Series Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions |

Checks

Context Check Description
snail/binutils-gdb-check success Github commit url

Commit Message

Jiang, Haochen Oct. 14, 2022, 9:12 a.m. UTC 
  From: Kong Lingling <lingling.kong@intel.com>

gas/ChangeLog:

	* NEWS: Support Intel AVX-NE-CONVERT.
	* config/tc-i386.c: Add avx_ne_convert.
	* doc/c-i386.texi: Document .avx_ne_convert, noavx_ne_convert.
	* testsuite/gas/i386/i386.exp: Run AVX NE CONVERT tests.
	* testsuite/gas/i386/avx-ne-convert-intel.d: New test.
	* testsuite/gas/i386/avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/avx-ne-convert.s: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.d: Ditto.
	* testsuite/gas/i386/x86-64-avx-ne-convert.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F3872): New.
	(PREFIX_VEX_0F38B0): Ditto.
	(PREFIX_VEX_0F38B1): Ditto.
	(VEX_W_0F3872_P_1): Ditto.
	(VEX_W_0F38B0_P_0): Ditto.
	(VEX_W_0F38B0_P_1): Ditto.
	(VEX_W_0F38B0_P_2): Ditto.
	(VEX_W_0F38B0_P_3): Ditto.
	(VEX_W_0F38B1_P_1): Ditto.
	(VEX_W_0F38B1_P_2): Ditto.
	(prefix_table): Add PREFIX_VEX_0F3872, PREFIX_VEX_0F38B0,
	PREFIX_VEX_0F38B1.
	(vex_table): Add VEX_W_0F3872_P_1, VEX_W_0F38B0_P_0,
	VEX_W_0F38B0_P_1, VEX_W_0F38B0_P_2, VEX_W_0F38B0_P_3,
	VEX_W_0F38B1_P_1,VEX_W_0F38B1_P_2.
	* i386-gen.c (cpu_flag_init): Add CPU_AVX_NE_CONVERT_FLGAS and
	CPU_ANY_AVX_NE_CONVERT_FLAGS.
	(cpu_flags): Add CpuAVX_NE_CONVERT.
	* i386-init.h: Regenerated.
	* i386-opc.h (CpuAVX_NE CONVERT): New.
	(i386_cpu_flags): Add cpuavx_ne_convert.
	* i386-opc.tbl: Add Intel AVX-NE-CONVERT instructions.
	* i386-tbl.h: Regenerated.
---
 gas/NEWS                                      |    2 +
 gas/config/tc-i386.c                          |    1 +
 gas/doc/c-i386.texi                           |    4 +-
 gas/testsuite/gas/i386/avx-ne-convert-intel.d |  170 +
 gas/testsuite/gas/i386/avx-ne-convert.d       |  170 +
 gas/testsuite/gas/i386/avx-ne-convert.s       |  167 +
 gas/testsuite/gas/i386/i386.exp               |    4 +
 .../gas/i386/x86-64-avx-ne-convert-intel.d    |  170 +
 .../gas/i386/x86-64-avx-ne-convert.d          |  170 +
 .../gas/i386/x86-64-avx-ne-convert.s          |  167 +
 opcodes/i386-dis.c                            |   58 +-
 opcodes/i386-gen.c                            |    5 +
 opcodes/i386-init.h                           |  516 +-
 opcodes/i386-opc.h                            |    3 +
 opcodes/i386-opc.tbl                          |   15 +
 opcodes/i386-tbl.h                            | 7950 +++++++++--------
 16 files changed, 5419 insertions(+), 4153 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/avx-ne-convert-intel.d
 create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.d
 create mode 100644 gas/testsuite/gas/i386/avx-ne-convert.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx-ne-convert.s

Comments

Jan Beulich Oct. 14, 2022, 12:58 p.m. UTC | #1 
On 14.10.2022 11:12, Haochen Jiang wrote:
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -937,6 +937,8 @@ enum
>    MOD_VEX_0F385E_X86_64_P_3_W_0,
>    MOD_VEX_0F388C,
>    MOD_VEX_0F388E,
> +  MOD_VEX_0F38B0,
> +  MOD_VEX_0F38B1,
>    MOD_VEX_0F3A30_L_0,
>    MOD_VEX_0F3A31_L_0,
>    MOD_VEX_0F3A32_L_0,
> @@ -1132,6 +1134,9 @@ enum
>    PREFIX_VEX_0F3851_W_0,
>    PREFIX_VEX_0F385C_X86_64,
>    PREFIX_VEX_0F385E_X86_64,
> +  PREFIX_VEX_0F3872,
> +  PREFIX_VEX_0F38B0,
> +  PREFIX_VEX_0F38B1,

PREFIX_VEX_0F38B0_M_1_W_0 and PREFIX_VEX_0F38B1_M_1_W_0 respectively,
please. These enumerators are supposed to show the already decoded
components. Plus they need to be unambiguous if insns appear which
vary in (here) permitted ModR/M forms or the VEX.W bit.

> @@ -1526,8 +1531,11 @@ enum
>    VEX_W_0F385E_X86_64_P_1,
>    VEX_W_0F385E_X86_64_P_2,
>    VEX_W_0F385E_X86_64_P_3,
> +  VEX_W_0F3872_P_1,
>    VEX_W_0F3878,
>    VEX_W_0F3879,
> +  VEX_W_0F38B0,
> +  VEX_W_0F38B1,

VEX_W_0F38B0_M_1 and VEX_W_0F38B1_M_1 respectively, please.

> @@ -7618,6 +7654,14 @@ static const struct dis386 vex_w_table[][2] = {
>      /* VEX_W_0F3879 */
>      { "vpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
>    },
> +  {
> +  /* VEX_W_0F38B0 */

Nit: Indentation.

> @@ -8428,6 +8472,14 @@ static const struct dis386 mod_table[][2] = {
>      /* MOD_VEX_0F388E */
>      { "vpmaskmov%DQ",	{ Mx, Vex, XM }, PREFIX_DATA },
>    },
> +  {
> +    /* MOD_VEX_0F38B0*/
> +    { VEX_W_TABLE (VEX_W_0F38B0) },
> +  },
> +  {
> +    /* MOD_VEX_0F38B1*/
> +    { VEX_W_TABLE (VEX_W_0F38B1) },
> +  },

Nit: Blanks missing in both of the comments.

> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -249,6 +249,8 @@ static initializer cpu_flag_init[] =
>      "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
>    { "CPU_AVX_VNNI_INT8_FLAGS",
>      "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
> +  { "CPU_AVX_NE_CONVERT_FLAGS",
> +    "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
>    { "CPU_IAMCU_FLAGS",
>      "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
>    { "CPU_ADX_FLAGS",
> @@ -447,6 +449,8 @@ static initializer cpu_flag_init[] =
>      "CpuAVX_IFMA" },
>    { "CPU_ANY_AVX_VNNI_INT8_FLAGS",
>      "CpuAVX_VNNI_INT8" },
> +  { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
> +    "CpuAVX_NE_CONVERT" },
>  };

Like for patches 1 and 2 - CPU_ANY_AVX2_FLAGS also need adjusting.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3027,6 +3027,21 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified|
>  
>  // MOVEDIR instructions end.
>  
> +// AVX_NE_CONVERT instructions.
> +
> +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
> +vbcstnesh2ps,   0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}

Why CheckRegSize?

> +vcvtneoph2ps,   0xb0,   None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
> +vcvtneebf162ps, 0xf3b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
> +vcvtneeph2ps,   0x66b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
> +vcvtneobf162ps, 0xf2b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
> +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
> +vcvtneps2bf16x, 0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> +vcvtneps2bf16y,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}

Nit: Excess blank after the first comma on the last of the above lines, and
excess blanks on all vcvt* lines before CpuAVX_NE_CONVERT.

Unnecessary Xmmword / Ymmword on the last four lines. And there again - why
CheckRegSize? But these would anyway benefit from using the AVX instance of
the <xy> template - then AT&T syntax handling for the suffix-less variant
would automatically be correct (it isn't in your code). Problem is that it
wasn't clear that there'll be a need to re-use xy's AVX instance this late
in the file, so the overloading of the name (commit e07ae9a3efee) will need
undoing. To keep names short (see commit 390ddd6f6812) I'd recommend using
Vxy and Exy (for the VEX and EVEX variants respectively).

Like for the earlier patches I disagree with the uses of PseudoVexPrefix
here (as said - the attribute should really go away again, and I have a
patch doing so), but then ...

> +
> +// AVX_NE_CONVERT instructions end.
> +
>  // AVX512_BF16 instructions.
>  
>  vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }

... the new insns (at least the ones having AVX512 counterparts) need to be
placed after the AVX512 ones (which you'll note use the <xy> template.

Jan
Frager, Neal via Binutils Oct. 24, 2022, 5:59 a.m. UTC | #2 
Hi Jan,

Thanks you so much for reviewing this patch.  I really appreciate it. For these review comments, I have made some changes.
Sorry, Forgot to delete i386-init.h and  i386-tbl.h in last email attachment.

> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, October 14, 2022 8:59 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> binutils@sourceware.org
> Subject: Re: [PATCH 03/10] Support Intel AVX-NE-CONVERT
> 
> On 14.10.2022 11:12, Haochen Jiang wrote:
> > --- a/opcodes/i386-dis.c
> > +++ b/opcodes/i386-dis.c
> > @@ -937,6 +937,8 @@ enum
> >    MOD_VEX_0F385E_X86_64_P_3_W_0,
> >    MOD_VEX_0F388C,
> >    MOD_VEX_0F388E,
> > +  MOD_VEX_0F38B0,
> > +  MOD_VEX_0F38B1,
> >    MOD_VEX_0F3A30_L_0,
> >    MOD_VEX_0F3A31_L_0,
> >    MOD_VEX_0F3A32_L_0,
> > @@ -1132,6 +1134,9 @@ enum
> >    PREFIX_VEX_0F3851_W_0,
> >    PREFIX_VEX_0F385C_X86_64,
> >    PREFIX_VEX_0F385E_X86_64,
> > +  PREFIX_VEX_0F3872,
> > +  PREFIX_VEX_0F38B0,
> > +  PREFIX_VEX_0F38B1,
> 
> PREFIX_VEX_0F38B0_M_1_W_0 and PREFIX_VEX_0F38B1_M_1_W_0
> respectively, please. These enumerators are supposed to show the already
> decoded components. Plus they need to be unambiguous if insns appear which
> vary in (here) permitted ModR/M forms or the VEX.W bit.

Yes, I changed it to PREFIX_VEX_0F38B0_M_1_W_0 and PREFIX_VEX_0F38B1_M_1_W_0.

> > @@ -1526,8 +1531,11 @@ enum
> >    VEX_W_0F385E_X86_64_P_1,
> >    VEX_W_0F385E_X86_64_P_2,
> >    VEX_W_0F385E_X86_64_P_3,
> > +  VEX_W_0F3872_P_1,
> >    VEX_W_0F3878,
> >    VEX_W_0F3879,
> > +  VEX_W_0F38B0,
> > +  VEX_W_0F38B1,
> 
> VEX_W_0F38B0_M_1 and VEX_W_0F38B1_M_1 respectively, please.
> 
> > @@ -7618,6 +7654,14 @@ static const struct dis386 vex_w_table[][2] = {
> >      /* VEX_W_0F3879 */
> >      { "vpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
> >    },
> > +  {
> > +  /* VEX_W_0F38B0 */
> 
> Nit: Indentation.

 Fixed.

> > @@ -8428,6 +8472,14 @@ static const struct dis386 mod_table[][2] = {
> >      /* MOD_VEX_0F388E */
> >      { "vpmaskmov%DQ",	{ Mx, Vex, XM }, PREFIX_DATA },
> >    },
> > +  {
> > +    /* MOD_VEX_0F38B0*/
> > +    { VEX_W_TABLE (VEX_W_0F38B0) },
> > +  },
> > +  {
> > +    /* MOD_VEX_0F38B1*/
> > +    { VEX_W_TABLE (VEX_W_0F38B1) },
> > +  },
> 
> Nit: Blanks missing in both of the comments.

Fixed.

> > --- a/opcodes/i386-gen.c
> > +++ b/opcodes/i386-gen.c
> > @@ -249,6 +249,8 @@ static initializer cpu_flag_init[] =
> >      "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
> >    { "CPU_AVX_VNNI_INT8_FLAGS",
> >      "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
> > +  { "CPU_AVX_NE_CONVERT_FLAGS",
> > +    "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
> >    { "CPU_IAMCU_FLAGS",
> >      "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> >    { "CPU_ADX_FLAGS",
> > @@ -447,6 +449,8 @@ static initializer cpu_flag_init[] =
> >      "CpuAVX_IFMA" },
> >    { "CPU_ANY_AVX_VNNI_INT8_FLAGS",
> >      "CpuAVX_VNNI_INT8" },
> > +  { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
> > +    "CpuAVX_NE_CONVERT" },
> >  };
> 
> Like for patches 1 and 2 - CPU_ANY_AVX2_FLAGS also need adjusting.

Fixed.

> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3027,6 +3027,21 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64B,
> > Modrm|AddrPrefixOpReg, { Unspecified|
> >
> >  // MOVEDIR instructions end.
> >
> > +// AVX_NE_CONVERT instructions.
> > +
> > +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
> > +vbcstnesh2ps,   0x66b1, None, CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
> 
> Why CheckRegSize?

Removed the CheckRegSize.

> > +vcvtneoph2ps,   0xb0,   None,   CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM}
> > +vcvtneebf162ps, 0xf3b0, None,   CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM}
> > +vcvtneeph2ps,   0x66b0, None,   CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM}
> > +vcvtneobf162ps, 0xf2b0, None,   CpuAVX_NE_CONVERT,
> Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> RegXMM|RegYMM}
> > +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT,
> Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|
> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> > +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT,
> Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|
> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
> > +vcvtneps2bf16x, 0xf372, None,   CpuAVX_NE_CONVERT,
> Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|
> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax,
> {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> > +vcvtneps2bf16y,  0xf372, None,   CpuAVX_NE_CONVERT,
> Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|
> No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax,
> {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
> 
> Nit: Excess blank after the first comma on the last of the above lines, and excess
> blanks on all vcvt* lines before CpuAVX_NE_CONVERT.

Fixed.

> Unnecessary Xmmword / Ymmword on the last four lines. And there again - why
> CheckRegSize? But these would anyway benefit from using the AVX instance of
> the <xy> template - then AT&T syntax handling for the suffix-less variant would
> automatically be correct (it isn't in your code). Problem is that it wasn't clear
> that there'll be a need to re-use xy's AVX instance this late in the file, so the
> overloading of the name (commit e07ae9a3efee) will need undoing. To keep
> names short (see commit 390ddd6f6812) I'd recommend using Vxy and Exy (for
> the VEX and EVEX variants respectively).
> 
> Like for the earlier patches I disagree with the uses of PseudoVexPrefix here (as
> said - the attribute should really go away again, and I have a patch doing so), but
> then ...

Removed the CheckRegSize, Xmmword / Ymmword and PseudoVexPrefix.
And added <Vxy> and <Exy>.

> > +
> > +// AVX_NE_CONVERT instructions end.
> > +
> >  // AVX512_BF16 instructions.
> >
> >  vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16,
> >
> Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|Chec
> kRe
> > gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
> > RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> > RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> 
> ... the new insns (at least the ones having AVX512 counterparts) need to be
> placed after the AVX512 ones (which you'll note use the <xy> template.
> 
> Jan

Yes, Now placed after the AVX512 ones.

Thanks,
Lingling
H.J. Lu Oct. 24, 2022, 7:25 p.m. UTC | #3 
On Sun, Oct 23, 2022 at 10:59 PM Kong, Lingling <lingling.kong@intel.com> wrote:
>
>
> Hi Jan,
>
> Thanks you so much for reviewing this patch.  I really appreciate it. For these review comments, I have made some changes.
> Sorry, Forgot to delete i386-init.h and  i386-tbl.h in last email attachment.
>
> > -----Original Message-----
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Friday, October 14, 2022 8:59 PM
> > To: Jiang, Haochen <haochen.jiang@intel.com>
> > Cc: hjl.tools@gmail.com; Kong, Lingling <lingling.kong@intel.com>;
> > binutils@sourceware.org
> > Subject: Re: [PATCH 03/10] Support Intel AVX-NE-CONVERT
> >
> > On 14.10.2022 11:12, Haochen Jiang wrote:
> > > --- a/opcodes/i386-dis.c
> > > +++ b/opcodes/i386-dis.c
> > > @@ -937,6 +937,8 @@ enum
> > >    MOD_VEX_0F385E_X86_64_P_3_W_0,
> > >    MOD_VEX_0F388C,
> > >    MOD_VEX_0F388E,
> > > +  MOD_VEX_0F38B0,
> > > +  MOD_VEX_0F38B1,
> > >    MOD_VEX_0F3A30_L_0,
> > >    MOD_VEX_0F3A31_L_0,
> > >    MOD_VEX_0F3A32_L_0,
> > > @@ -1132,6 +1134,9 @@ enum
> > >    PREFIX_VEX_0F3851_W_0,
> > >    PREFIX_VEX_0F385C_X86_64,
> > >    PREFIX_VEX_0F385E_X86_64,
> > > +  PREFIX_VEX_0F3872,
> > > +  PREFIX_VEX_0F38B0,
> > > +  PREFIX_VEX_0F38B1,
> >
> > PREFIX_VEX_0F38B0_M_1_W_0 and PREFIX_VEX_0F38B1_M_1_W_0
> > respectively, please. These enumerators are supposed to show the already
> > decoded components. Plus they need to be unambiguous if insns appear which
> > vary in (here) permitted ModR/M forms or the VEX.W bit.
>
> Yes, I changed it to PREFIX_VEX_0F38B0_M_1_W_0 and PREFIX_VEX_0F38B1_M_1_W_0.
>
> > > @@ -1526,8 +1531,11 @@ enum
> > >    VEX_W_0F385E_X86_64_P_1,
> > >    VEX_W_0F385E_X86_64_P_2,
> > >    VEX_W_0F385E_X86_64_P_3,
> > > +  VEX_W_0F3872_P_1,
> > >    VEX_W_0F3878,
> > >    VEX_W_0F3879,
> > > +  VEX_W_0F38B0,
> > > +  VEX_W_0F38B1,
> >
> > VEX_W_0F38B0_M_1 and VEX_W_0F38B1_M_1 respectively, please.
> >
> > > @@ -7618,6 +7654,14 @@ static const struct dis386 vex_w_table[][2] = {
> > >      /* VEX_W_0F3879 */
> > >      { "vpbroadcastw",      { XM, EXw }, PREFIX_DATA },
> > >    },
> > > +  {
> > > +  /* VEX_W_0F38B0 */
> >
> > Nit: Indentation.
>
>  Fixed.
>
> > > @@ -8428,6 +8472,14 @@ static const struct dis386 mod_table[][2] = {
> > >      /* MOD_VEX_0F388E */
> > >      { "vpmaskmov%DQ",      { Mx, Vex, XM }, PREFIX_DATA },
> > >    },
> > > +  {
> > > +    /* MOD_VEX_0F38B0*/
> > > +    { VEX_W_TABLE (VEX_W_0F38B0) },
> > > +  },
> > > +  {
> > > +    /* MOD_VEX_0F38B1*/
> > > +    { VEX_W_TABLE (VEX_W_0F38B1) },
> > > +  },
> >
> > Nit: Blanks missing in both of the comments.
>
> Fixed.
>
> > > --- a/opcodes/i386-gen.c
> > > +++ b/opcodes/i386-gen.c
> > > @@ -249,6 +249,8 @@ static initializer cpu_flag_init[] =
> > >      "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
> > >    { "CPU_AVX_VNNI_INT8_FLAGS",
> > >      "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
> > > +  { "CPU_AVX_NE_CONVERT_FLAGS",
> > > +    "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
> > >    { "CPU_IAMCU_FLAGS",
> > >      "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
> > >    { "CPU_ADX_FLAGS",
> > > @@ -447,6 +449,8 @@ static initializer cpu_flag_init[] =
> > >      "CpuAVX_IFMA" },
> > >    { "CPU_ANY_AVX_VNNI_INT8_FLAGS",
> > >      "CpuAVX_VNNI_INT8" },
> > > +  { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
> > > +    "CpuAVX_NE_CONVERT" },
> > >  };
> >
> > Like for patches 1 and 2 - CPU_ANY_AVX2_FLAGS also need adjusting.
>
> Fixed.
>
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3027,6 +3027,21 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64B,
> > > Modrm|AddrPrefixOpReg, { Unspecified|
> > >
> > >  // MOVEDIR instructions end.
> > >
> > > +// AVX_NE_CONVERT instructions.
> > > +
> > > +vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
> > > +vbcstnesh2ps,   0x66b1, None, CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
> >
> > Why CheckRegSize?
>
> Removed the CheckRegSize.
>
> > > +vcvtneoph2ps,   0xb0,   None,   CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> > RegXMM|RegYMM}
> > > +vcvtneebf162ps, 0xf3b0, None,   CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> > RegXMM|RegYMM}
> > > +vcvtneeph2ps,   0x66b0, None,   CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> > RegXMM|RegYMM}
> > > +vcvtneobf162ps, 0xf2b0, None,   CpuAVX_NE_CONVERT,
> > Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No
> > _sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex,
> > RegXMM|RegYMM}
> > > +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT,
> > Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|
> > No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> > {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> > > +vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT,
> > Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|
> > No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf,
> > {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
> > > +vcvtneps2bf16x, 0xf372, None,   CpuAVX_NE_CONVERT,
> > Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|
> > No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax,
> > {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
> > > +vcvtneps2bf16y,  0xf372, None,   CpuAVX_NE_CONVERT,
> > Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|
> > No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax,
> > {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
> >
> > Nit: Excess blank after the first comma on the last of the above lines, and excess
> > blanks on all vcvt* lines before CpuAVX_NE_CONVERT.
>
> Fixed.
>
> > Unnecessary Xmmword / Ymmword on the last four lines. And there again - why
> > CheckRegSize? But these would anyway benefit from using the AVX instance of
> > the <xy> template - then AT&T syntax handling for the suffix-less variant would
> > automatically be correct (it isn't in your code). Problem is that it wasn't clear
> > that there'll be a need to re-use xy's AVX instance this late in the file, so the
> > overloading of the name (commit e07ae9a3efee) will need undoing. To keep
> > names short (see commit 390ddd6f6812) I'd recommend using Vxy and Exy (for
> > the VEX and EVEX variants respectively).
> >
> > Like for the earlier patches I disagree with the uses of PseudoVexPrefix here (as
> > said - the attribute should really go away again, and I have a patch doing so), but
> > then ...
>
> Removed the CheckRegSize, Xmmword / Ymmword and PseudoVexPrefix.
> And added <Vxy> and <Exy>.
>
> > > +
> > > +// AVX_NE_CONVERT instructions end.
> > > +
> > >  // AVX512_BF16 instructions.
> > >
> > >  vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16,
> > >
> > Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|Chec
> > kRe
> > > gSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {
> > > RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> > > RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> >
> > ... the new insns (at least the ones having AVX512 counterparts) need to be
> > placed after the AVX512 ones (which you'll note use the <xy> template.
> >
> > Jan
>
> Yes, Now placed after the AVX512 ones.
>
> Thanks,
> Lingling

Please add some comments to explain how <Exy> and <Vxy> are
used, something like <Vxy> is used on VEX instructions with x/y
suffixes and <Exy> is used on EVEX instructions with x/y suffixes.

Thanks.
Jan Beulich Oct. 25, 2022, 6:44 a.m. UTC | #4 
On 24.10.2022 07:59, Kong, Lingling wrote:
> Thanks you so much for reviewing this patch.  I really appreciate it. For these review comments, I have made some changes.

I guess the conversion to Vxy / Exy would better have been a separate,
prereq patch.

Like for the earlier patches - maybe better move the insertion in
opcodes/i386-opc.tbl to immediately after the related, pre-existing
templates? Plus vcvtne*2ps are all still lacking CheckRegSize afaict.
And then within a group we usually strive to sort alphabetically
when no other, more relevant ordering criteria exist (here putting
the two BF16 and the two PH ones each next to one another might be
another option, to make it easier to see their similarity).

Also like said for an earlier patch - please send new versions as new
mails and please avoid sending patches as (only) attachments. See my
earlier reply for why that is.

Jan
diff mbox series

Patch

diff --git a/gas/NEWS b/gas/NEWS
index 86996be2f5..d5e06bd1de 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@ 
 -*- text -*-
 
+* Add support for Intel AVX-NE-CONVERT instructions.
+
 * Add support for Intel AVX-VNNI-INT8 instructions.
 
 * Add support for Intel AVX-IFMA instructions.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 8329529d38..42579bb701 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1096,6 +1096,7 @@  static const arch_entry cpu_arch[] =
   SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
   SUBARCH (avx_ifma, AVX_IFMA, ANY_AVX_IFMA, false),
   SUBARCH (avx_vnni_int8, AVX_VNNI_INT8, ANY_AVX_VNNI_INT8, false),
+  SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
 };
 
 #undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 18fa30072b..a0204ca48d 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -215,6 +215,7 @@  accept various extension mnemonics.  For example,
 @code{avx512_fp16},
 @code{avx_ifma},
 @code{avx_vnni_int8},
+@code{avx_ne_convert},
 @code{noavx512f},
 @code{noavx512cd},
 @code{noavx512er},
@@ -237,6 +238,7 @@  accept various extension mnemonics.  For example,
 @code{noavx512_fp16},
 @code{noavx_ifma},
 @code{noavx_vnni_int8},
+@code{noavx_ne_convert},
 @code{noenqcmd},
 @code{noserialize},
 @code{notsxldtrk},
@@ -1537,7 +1539,7 @@  supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
 @item @samp{.tdx} @tab @samp{.avx_vnni}  @tab @samp{.avx512_fp16}
 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
-@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
+@item @samp{.avx_ifma} @tab @samp{.avx_vnni_int8} @tab @samp{.avx_ne_convert}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/avx-ne-convert-intel.d b/gas/testsuite/gas/i386/avx-ne-convert-intel.d
new file mode 100644
index 0000000000..490fd9516f
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert-intel.d
@@ -0,0 +1,170 @@ 
+#as:
+#objdump: -dw -Mintel
+#name: i386 AVX-NE-CONVERT insns (Intel disassembly)
+#source: avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[ecx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[edx-0x100\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[ecx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[edx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[ecx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[edx-0x1000\]
diff --git a/gas/testsuite/gas/i386/avx-ne-convert.d b/gas/testsuite/gas/i386/avx-ne-convert.d
new file mode 100644
index 0000000000..24f6ae09fe
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert.d
@@ -0,0 +1,170 @@ 
+#as:
+#objdump: -dw
+#name: i386 AVX-NE-CONVERT insns
+#source: avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 31\s+vbcstnebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b4 f4 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 31\s+vbcstnebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 31\s+vbcstnesh2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b4 f4 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 31\s+vbcstnesh2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 31\s+vcvtneebf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b4 f4 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 31\s+vcvtneebf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 31\s+vcvtneeph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b4 f4 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 31\s+vcvtneeph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 31\s+vcvtneobf162ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b4 f4 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 31\s+vcvtneobf162ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 31\s+vcvtneoph2ps \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b4 f4 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%esp,%esi,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 31\s+vcvtneoph2ps \(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%ecx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%edx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 b4 f4 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b4 f4 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%esp,%esi,8\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 31\s+vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%ecx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%edx\),%xmm6
diff --git a/gas/testsuite/gas/i386/avx-ne-convert.s b/gas/testsuite/gas/i386/avx-ne-convert.s
new file mode 100644
index 0000000000..7fb866630d
--- /dev/null
+++ b/gas/testsuite/gas/i386/avx-ne-convert.s
@@ -0,0 +1,167 @@ 
+# Check 32bit AVX-NE-CONVERT instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vbcstnebf162ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	254(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	-256(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnebf162ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	254(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	-256(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	254(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	-256(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	254(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	-256(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vcvtneebf162ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneebf162ps	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneebf162ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	4064(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneebf162ps	-4096(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneeph2ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneeph2ps	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneeph2ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	4064(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneeph2ps	-4096(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneobf162ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneobf162ps	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneobf162ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	4064(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneobf162ps	-4096(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneoph2ps	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneoph2ps	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneoph2ps	0x10000000(%esp, %esi, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	(%ecx), %ymm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	4064(%ecx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneoph2ps	-4096(%edx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16x	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16x	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16x	0x10000000(%esp, %esi, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16x	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16x	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16x	(%ecx), %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{evex} vcvtneps2bf16x	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex}  vcvtneps2bf16x	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex3} vcvtneps2bf16x	2032(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneps2bf16x	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{evex} vcvtneps2bf16x	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex}  vcvtneps2bf16x	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex3} vcvtneps2bf16x	-2048(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneps2bf16y	4064(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{evex} vcvtneps2bf16y	4064(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex}  vcvtneps2bf16y	4064(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex3} vcvtneps2bf16y	4064(%ecx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneps2bf16y	-4096(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{evex} vcvtneps2bf16y	-4096(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex}  vcvtneps2bf16y	-4096(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex3} vcvtneps2bf16y	-4096(%edx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+
+.intel_syntax noprefix
+	vbcstnebf162ps	xmm6, WORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	xmm6, WORD PTR [ecx]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	xmm6, WORD PTR [ecx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	xmm6, WORD PTR [edx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnebf162ps	ymm6, WORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	ymm6, WORD PTR [ecx]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	ymm6, WORD PTR [ecx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	ymm6, WORD PTR [edx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	xmm6, WORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	xmm6, WORD PTR [ecx]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	xmm6, WORD PTR [ecx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	xmm6, WORD PTR [edx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	ymm6, WORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	ymm6, WORD PTR [ecx]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	ymm6, WORD PTR [ecx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	ymm6, WORD PTR [edx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vcvtneebf162ps	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneebf162ps	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneebf162ps	ymm6, YMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	ymm6, YMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	ymm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneebf162ps	ymm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneeph2ps	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneeph2ps	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneeph2ps	ymm6, YMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	ymm6, YMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	ymm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneeph2ps	ymm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneobf162ps	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneobf162ps	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneobf162ps	ymm6, YMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	ymm6, YMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	ymm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneobf162ps	ymm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneoph2ps	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneoph2ps	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneoph2ps	ymm6, YMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	ymm6, YMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	ymm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneoph2ps	ymm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [esp+esi*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	{vex}  vcvtneps2bf16	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [ecx]	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex}  vcvtneps2bf16	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [ecx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneps2bf16	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex}  vcvtneps2bf16	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [edx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneps2bf16	xmm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{evex} vcvtneps2bf16	xmm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex}  vcvtneps2bf16	xmm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex3} vcvtneps2bf16	xmm6, YMMWORD PTR [ecx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneps2bf16	xmm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{evex} vcvtneps2bf16	xmm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex}  vcvtneps2bf16	xmm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex3} vcvtneps2bf16	xmm6, YMMWORD PTR [edx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index 08774c38d9..d03c2187ea 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -483,6 +483,8 @@  if [gas_32_check] then {
     run_list_test "avx-ifma-inval"
     run_dump_test "avx-vnni-int8"
     run_dump_test "avx-vnni-int8-intel"
+    run_dump_test "avx-ne-convert"
+    run_dump_test "avx-ne-convert-intel"
     run_list_test "sg"
     run_dump_test "clzero"
     run_dump_test "invlpgb"
@@ -1155,6 +1157,8 @@  if [gas_64_check] then {
     run_list_test "x86-64-avx-ifma-inval"
     run_dump_test "x86-64-avx-vnni-int8"
     run_dump_test "x86-64-avx-vnni-int8-intel"
+    run_dump_test "x86-64-avx-ne-convert"
+    run_dump_test "x86-64-avx-ne-convert-intel"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
new file mode 100644
index 0000000000..96ec69a12c
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert-intel.d
@@ -0,0 +1,170 @@ 
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 AVX-NE-CONVERT insns (Intel disassembly)
+#source: x86-64-avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps xmm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps xmm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps xmm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps xmm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps ymm6,WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps ymm6,WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps ymm6,WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps ymm6,WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps ymm6,YMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps ymm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,xmm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 xmm6,ymm5
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[r9\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rcx\+0x7f0\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,XMMWORD PTR \[rdx-0x800\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rcx\+0xfe0\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16 xmm6,YMMWORD PTR \[rdx-0x1000\]
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
new file mode 100644
index 0000000000..6bd8391ed5
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.d
@@ -0,0 +1,170 @@ 
+#as:
+#objdump: -dw
+#name: x86_64 AVX-NE-CONVERT insns
+#source: x86-64-avx-ne-convert.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b1 31\s+vbcstnebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b1 b4 f5 00 00 00 10\s+vbcstnebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b1 31\s+vbcstnebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b1 fe 00 00 00\s+vbcstnebf162ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b1 b2 00 ff ff ff\s+vbcstnebf162ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b1 31\s+vbcstnesh2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b1 b4 f5 00 00 00 10\s+vbcstnesh2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b1 31\s+vbcstnesh2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b1 fe 00 00 00\s+vbcstnesh2ps 0xfe\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b1 b2 00 ff ff ff\s+vbcstnesh2ps -0x100\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7a b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a b0 31\s+vcvtneebf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b1 f0 07 00 00\s+vcvtneebf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a b0 b2 00 f8 ff ff\s+vcvtneebf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7e b0 b4 f5 00 00 00 10\s+vcvtneebf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7e b0 31\s+vcvtneebf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b1 e0 0f 00 00\s+vcvtneebf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7e b0 b2 00 f0 ff ff\s+vcvtneebf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 79 b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 79 b0 31\s+vcvtneeph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b1 f0 07 00 00\s+vcvtneeph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 79 b0 b2 00 f8 ff ff\s+vcvtneeph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7d b0 b4 f5 00 00 00 10\s+vcvtneeph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7d b0 31\s+vcvtneeph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b1 e0 0f 00 00\s+vcvtneeph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7d b0 b2 00 f0 ff ff\s+vcvtneeph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 7b b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7b b0 31\s+vcvtneobf162ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b1 f0 07 00 00\s+vcvtneobf162ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7b b0 b2 00 f8 ff ff\s+vcvtneobf162ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7f b0 b4 f5 00 00 00 10\s+vcvtneobf162ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7f b0 31\s+vcvtneobf162ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b1 e0 0f 00 00\s+vcvtneobf162ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7f b0 b2 00 f0 ff ff\s+vcvtneobf162ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*c4 a2 78 b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 78 b0 31\s+vcvtneoph2ps \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b1 f0 07 00 00\s+vcvtneoph2ps 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 78 b0 b2 00 f8 ff ff\s+vcvtneoph2ps -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7c b0 b4 f5 00 00 00 10\s+vcvtneoph2ps 0x10000000\(%rbp,%r14,8\),%ymm6
+\s*[a-f0-9]+:\s*c4 c2 7c b0 31\s+vcvtneoph2ps \(%r9\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b1 e0 0f 00 00\s+vcvtneoph2ps 0xfe0\(%rcx\),%ymm6
+\s*[a-f0-9]+:\s*c4 e2 7c b0 b2 00 f0 ff ff\s+vcvtneoph2ps -0x1000\(%rdx\),%ymm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 f5\s+vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 f5\s+\{vex\} vcvtneps2bf16 %xmm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 f5\s+vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 f5\s+\{vex\} vcvtneps2bf16 %ymm5,%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 b2 7e 08 72 b4 f5 00 00 00 10\s+vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*c4 a2 7a 72 b4 f5 00 00 00 10\s+\{vex\} vcvtneps2bf16x 0x10000000\(%rbp,%r14,8\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 d2 7e 08 72 31\s+vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*c4 c2 7a 72 31\s+\{vex\} vcvtneps2bf16x \(%r9\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 71 7f\s+vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b1 f0 07 00 00\s+\{vex\} vcvtneps2bf16x 0x7f0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 08 72 72 80\s+vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7a 72 b2 00 f8 ff ff\s+\{vex\} vcvtneps2bf16x -0x800\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 71 7f\s+vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b1 e0 0f 00 00\s+\{vex\} vcvtneps2bf16y 0xfe0\(%rcx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*62 f2 7e 28 72 72 80\s+vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
+\s*[a-f0-9]+:\s*c4 e2 7e 72 b2 00 f0 ff ff\s+\{vex\} vcvtneps2bf16y -0x1000\(%rdx\),%xmm6
diff --git a/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s
new file mode 100644
index 0000000000..c01a95d943
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx-ne-convert.s
@@ -0,0 +1,167 @@ 
+# Check 64bit AVX-NE-CONVERT instructions
+
+	.allow_index_reg
+	.text
+_start:
+	vbcstnebf162ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	254(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	-256(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnebf162ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vbcstnebf162ps	254(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	-256(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	254(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	-256(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vbcstnesh2ps	254(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	-256(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vcvtneebf162ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneebf162ps	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneebf162ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vcvtneebf162ps	4064(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneebf162ps	-4096(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneeph2ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneeph2ps	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneeph2ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vcvtneeph2ps	4064(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneeph2ps	-4096(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneobf162ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneobf162ps	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneobf162ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vcvtneobf162ps	4064(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneobf162ps	-4096(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneoph2ps	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneoph2ps	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneoph2ps	0x10000000(%rbp, %r14, 8), %ymm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	(%r9), %ymm6	 #AVX-NE-CONVERT
+	vcvtneoph2ps	4064(%rcx), %ymm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneoph2ps	-4096(%rdx), %ymm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	%xmm5, %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	%ymm5, %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16x	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16x	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16x	0x10000000(%rbp, %r14, 8), %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	(%r9), %xmm6	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16x	(%r9), %xmm6	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16x	(%r9), %xmm6	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16x	(%r9), %xmm6	 #AVX-NE-CONVERT
+	vcvtneps2bf16x	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{evex} vcvtneps2bf16x	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex} vcvtneps2bf16x	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex3} vcvtneps2bf16x	2032(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneps2bf16x	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{evex} vcvtneps2bf16x	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex} vcvtneps2bf16x	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex3} vcvtneps2bf16x	-2048(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneps2bf16y	4064(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{evex} vcvtneps2bf16y	4064(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex} vcvtneps2bf16y	4064(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex3} vcvtneps2bf16y	4064(%rcx), %xmm6	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneps2bf16y	-4096(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{evex} vcvtneps2bf16y	-4096(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex} vcvtneps2bf16y	-4096(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex3} vcvtneps2bf16y	-4096(%rdx), %xmm6	 #AVX-NE-CONVERT Disp32(00f0ffff)
+
+.intel_syntax noprefix
+	vbcstnebf162ps	xmm6, WORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	xmm6, WORD PTR [r9]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	xmm6, WORD PTR [rcx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	xmm6, WORD PTR [rdx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnebf162ps	ymm6, WORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	ymm6, WORD PTR [r9]	 #AVX-NE-CONVERT
+	vbcstnebf162ps	ymm6, WORD PTR [rcx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnebf162ps	ymm6, WORD PTR [rdx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	xmm6, WORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	xmm6, WORD PTR [r9]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	xmm6, WORD PTR [rcx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	xmm6, WORD PTR [rdx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vbcstnesh2ps	ymm6, WORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	ymm6, WORD PTR [r9]	 #AVX-NE-CONVERT
+	vbcstnesh2ps	ymm6, WORD PTR [rcx+254]	 #AVX-NE-CONVERT Disp32(fe000000)
+	vbcstnesh2ps	ymm6, WORD PTR [rdx-256]	 #AVX-NE-CONVERT Disp32(00ffffff)
+	vcvtneebf162ps	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneebf162ps	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneebf162ps	ymm6, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	ymm6, YMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneebf162ps	ymm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneebf162ps	ymm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneeph2ps	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneeph2ps	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneeph2ps	ymm6, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	ymm6, YMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneeph2ps	ymm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneeph2ps	ymm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneobf162ps	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneobf162ps	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneobf162ps	ymm6, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	ymm6, YMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneobf162ps	ymm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneobf162ps	ymm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneoph2ps	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneoph2ps	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneoph2ps	ymm6, YMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	ymm6, YMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneoph2ps	ymm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneoph2ps	ymm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, xmm5	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, ymm5	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [rbp+r14*8+0x10000000]	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	{vex} vcvtneps2bf16	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [r9]	 #AVX-NE-CONVERT
+	vcvtneps2bf16	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex} vcvtneps2bf16	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [rcx+2032]	 #AVX-NE-CONVERT Disp32(f0070000)
+	vcvtneps2bf16	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{evex} vcvtneps2bf16	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex} vcvtneps2bf16	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	{vex3} vcvtneps2bf16	xmm6, XMMWORD PTR [rdx-2048]	 #AVX-NE-CONVERT Disp32(00f8ffff)
+	vcvtneps2bf16	xmm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{evex} vcvtneps2bf16	xmm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex} vcvtneps2bf16	xmm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	{vex3} vcvtneps2bf16	xmm6, YMMWORD PTR [rcx+4064]	 #AVX-NE-CONVERT Disp32(e00f0000)
+	vcvtneps2bf16	xmm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{evex} vcvtneps2bf16	xmm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex} vcvtneps2bf16	xmm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
+	{vex3} vcvtneps2bf16	xmm6, YMMWORD PTR [rdx-4096]	 #AVX-NE-CONVERT Disp32(00f0ffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index d04cc3779b..e0e99c83b9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -937,6 +937,8 @@  enum
   MOD_VEX_0F385E_X86_64_P_3_W_0,
   MOD_VEX_0F388C,
   MOD_VEX_0F388E,
+  MOD_VEX_0F38B0,
+  MOD_VEX_0F38B1,
   MOD_VEX_0F3A30_L_0,
   MOD_VEX_0F3A31_L_0,
   MOD_VEX_0F3A32_L_0,
@@ -1132,6 +1134,9 @@  enum
   PREFIX_VEX_0F3851_W_0,
   PREFIX_VEX_0F385C_X86_64,
   PREFIX_VEX_0F385E_X86_64,
+  PREFIX_VEX_0F3872,
+  PREFIX_VEX_0F38B0,
+  PREFIX_VEX_0F38B1,
   PREFIX_VEX_0F38F5_L_0,
   PREFIX_VEX_0F38F6_L_0,
   PREFIX_VEX_0F38F7_L_0,
@@ -1526,8 +1531,11 @@  enum
   VEX_W_0F385E_X86_64_P_1,
   VEX_W_0F385E_X86_64_P_2,
   VEX_W_0F385E_X86_64_P_3,
+  VEX_W_0F3872_P_1,
   VEX_W_0F3878,
   VEX_W_0F3879,
+  VEX_W_0F38B0,
+  VEX_W_0F38B1,
   VEX_W_0F38B4,
   VEX_W_0F38B5,
   VEX_W_0F38CF,
@@ -4035,7 +4043,31 @@  static const struct dis386 prefix_table[][4] = {
     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
     { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
   },
+  
+  /* PREFIX_VEX_0F3872 */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (VEX_W_0F3872_P_1) },
+    { Bad_Opcode },
+    { Bad_Opcode },
+  },
 
+  /* PREFIX_VEX_0F38B0 */
+  {
+    { "vcvtneoph2ps", {XM, Mx}, 0 },
+    { "vcvtneebf162ps", {XM, Mx}, 0 },
+    { "vcvtneeph2ps", {XM, Mx}, 0 },
+    { "vcvtneobf162ps", {XM, Mx}, 0 },
+  },
+
+  /* PREFIX_VEX_0F38B1 */
+  {
+    { Bad_Opcode },
+    { "vbcstnebf162ps", {XM, Ew}, 0 },
+    { "vbcstnesh2ps", {XM, Ew}, 0 },
+    { Bad_Opcode },
+  },
+  
   /* PREFIX_VEX_0F38F5_L_0 */
   {
     { "bzhiS",		{ Gdq, Edq, VexGdq }, 0 },
@@ -6238,7 +6270,7 @@  static const struct dis386 vex_table[][256] = {
     /* 70 */
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3872) },
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
@@ -6308,8 +6340,8 @@  static const struct dis386 vex_table[][256] = {
     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
     /* b0 */
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { MOD_TABLE (MOD_VEX_0F38B0) },
+    { MOD_TABLE (MOD_VEX_0F38B1) },
     { Bad_Opcode },
     { Bad_Opcode },
     { VEX_W_TABLE (VEX_W_0F38B4) },
@@ -7610,6 +7642,10 @@  static const struct dis386 vex_w_table[][2] = {
     /* VEX_W_0F385E_X86_64_P_3 */
     { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
   },
+  {
+    /* VEX_W_0F3872_P_1 */
+    { "%XV vcvtneps2bf16%XY", { XMM, EXx }, 0 },
+  },
   {
     /* VEX_W_0F3878 */
     { "vpbroadcastb",	{ XM, EXb }, PREFIX_DATA },
@@ -7618,6 +7654,14 @@  static const struct dis386 vex_w_table[][2] = {
     /* VEX_W_0F3879 */
     { "vpbroadcastw",	{ XM, EXw }, PREFIX_DATA },
   },
+  {
+  /* VEX_W_0F38B0 */
+    { PREFIX_TABLE (PREFIX_VEX_0F38B0) },
+  },
+  {
+    /* VEX_W_0F38B1 */
+    { PREFIX_TABLE (PREFIX_VEX_0F38B1) },
+  },
   {
     /* VEX_W_0F38B4 */
     { Bad_Opcode },
@@ -8428,6 +8472,14 @@  static const struct dis386 mod_table[][2] = {
     /* MOD_VEX_0F388E */
     { "vpmaskmov%DQ",	{ Mx, Vex, XM }, PREFIX_DATA },
   },
+  {
+    /* MOD_VEX_0F38B0*/
+    { VEX_W_TABLE (VEX_W_0F38B0) },
+  },
+  {
+    /* MOD_VEX_0F38B1*/
+    { VEX_W_TABLE (VEX_W_0F38B1) },
+  },
   {
     /* MOD_VEX_0F3A30_L_0 */
     { Bad_Opcode },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 8a80c4c64b..6c69ebf29b 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -249,6 +249,8 @@  static initializer cpu_flag_init[] =
     "CPU_AVX2_FLAGS|CpuAVX_IFMA" },
   { "CPU_AVX_VNNI_INT8_FLAGS",
     "CPU_AVX2_FLAGS|CpuAVX_VNNI_INT8" },
+  { "CPU_AVX_NE_CONVERT_FLAGS",
+    "CPU_AVX2_FLAGS|CpuAVX_NE_CONVERT" },
   { "CPU_IAMCU_FLAGS",
     "Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
   { "CPU_ADX_FLAGS",
@@ -447,6 +449,8 @@  static initializer cpu_flag_init[] =
     "CpuAVX_IFMA" },
   { "CPU_ANY_AVX_VNNI_INT8_FLAGS",
     "CpuAVX_VNNI_INT8" },
+  { "CPU_ANY_AVX_NE_CONVERT_FLAGS",
+    "CpuAVX_NE_CONVERT" },
 };
 
 static initializer operand_type_init[] =
@@ -650,6 +654,7 @@  static bitfield cpu_flags[] =
   BITFIELD (CpuAVX512_FP16),
   BITFIELD (CpuAVX_IFMA),
   BITFIELD (CpuAVX_VNNI_INT8),
+  BITFIELD (CpuAVX_NE_CONVERT),
   BITFIELD (CpuMWAITX),
   BITFIELD (CpuCLZERO),
   BITFIELD (CpuOSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index e9c6785898..c5212aaf12 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -213,6 +213,8 @@  enum
   CpuAVX_IFMA,
   /* Intel AVX VNNI-INT8 Instructions support required.  */
   CpuAVX_VNNI_INT8,
+  /* Intel AVX NE CONVERT Instructions support required.  */
+  CpuAVX_NE_CONVERT,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -394,6 +396,7 @@  typedef union i386_cpu_flags
       unsigned int cpuavx512_fp16:1;
       unsigned int cpuavx_ifma:1;
       unsigned int cpuavx_vnni_int8:1;
+      unsigned int cpuavx_ne_convert:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 458a9897da..daff6669de 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3027,6 +3027,21 @@  movdir64b, 0x660f38f8, None, CpuMOVDIR64B, Modrm|AddrPrefixOpReg, { Unspecified|
 
 // MOVEDIR instructions end.
 
+// AVX_NE_CONVERT instructions.
+
+vbcstnebf162ps, 0xf3b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
+vbcstnesh2ps,   0x66b1, None, CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Word|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneoph2ps,   0xb0,   None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneebf162ps, 0xf3b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneeph2ps,   0x66b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneobf162ps, 0xf2b0, None,   CpuAVX_NE_CONVERT, Modrm|Vex|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|Ymmword|Unspecified|BaseIndex, RegXMM|RegYMM}
+vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16x, 0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex128|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Xmmword|RegXMM|Unspecified|BaseIndex, RegXMM}
+vcvtneps2bf16y,  0xf372, None,   CpuAVX_NE_CONVERT, Modrm|PseudoVexPrefix|Vex256|Space0F38|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, {Ymmword|RegYMM|Unspecified|BaseIndex, RegXMM}
+
+// AVX_NE_CONVERT instructions end.
+
 // AVX512_BF16 instructions.
 
 vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }