[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard
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Commit Message
From: zengxiao <zengxiao@eswincomputing.com>
This patch makes R_RISCV_SUB6 conforms to riscv abi standard.
R_RISCV_SUB6 only the lower 6 bits of the code are valid.
The proposed specification which can be found in 8.5. Relocations of,
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_elf_add_sub_reloc): Take the lower
6 bits as the significant bit
reviewed-by: gaofei@eswincomputing.com
jinyanjiang@eswincomputing.com
Signed-off-by: zengxiao <zengxiao@eswincomputing.com>
---
bfd/elfxx-riscv.c | 7 +++++++
1 file changed, 7 insertions(+)
@@ -994,6 +994,13 @@ riscv_elf_add_sub_reloc (bfd *abfd,
relocation = old_value + relocation;
break;
case R_RISCV_SUB6:
+ {
+ bfd_vma six_bit_valid_value = old_value & howto->dst_mask;
+ six_bit_valid_value -= relocation;
+ relocation = (six_bit_valid_value & howto->dst_mask) |
+ (old_value & ~howto->dst_mask);
+ }
+ break;
case R_RISCV_SUB8:
case R_RISCV_SUB16:
case R_RISCV_SUB32: