diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 0bcf2fdcfa34..d4f580733ddd 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1104,6 +1104,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"smaia", "ssaia",		check_implicit_always},
   {"smstateen", "ssstateen",	check_implicit_always},
   {"smepmp", "zicsr",		check_implicit_always},
+  {"smrnmi", "zicsr",		check_implicit_always},
   {"ssaia", "zicsr",		check_implicit_always},
   {"sscofpmf", "zicsr",		check_implicit_always},
   {"ssstateen", "zicsr",	check_implicit_always},
@@ -1225,6 +1226,7 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
 {
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smepmp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"smrnmi",		ISA_SPEC_CLASS_DRAFT,		0, 4, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscofpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2415,6 +2417,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
 	      || riscv_subset_supports (rps, "zve64d")
 	      || riscv_subset_supports (rps, "zve64f")
 	      || riscv_subset_supports (rps, "zve32f"));
+    case INSN_CLASS_SMRNMI:
+      return riscv_subset_supports (rps, "smrnmi");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2573,6 +2577,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64x' or `zve32x");
     case INSN_CLASS_ZVEF:
       return _("v' or `zve64d' or `zve64f' or `zve32f");
+    case INSN_CLASS_SMRNMI:
+      return "smrnmi";
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 0682eb355241..85aa4d1d00d4 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -74,6 +74,7 @@ enum riscv_csr_class
   CSR_CLASS_H_32,	/* hypervisor, rv32 only */
   CSR_CLASS_SMAIA,		/* Smaia */
   CSR_CLASS_SMAIA_32,		/* Smaia, rv32 only */
+  CSR_CLASS_SMRNMI,		/* Smrnmi only */
   CSR_CLASS_SMSTATEEN,		/* Smstateen only */
   CSR_CLASS_SMSTATEEN_32,	/* Smstateen RV32 only */
   CSR_CLASS_SSAIA,		/* Ssaia */
@@ -1049,6 +1050,9 @@ riscv_csr_address (const char *csr_name,
     case CSR_CLASS_SMAIA:
       extension = "smaia";
       break;
+    case CSR_CLASS_SMRNMI:
+      extension = "smrnmi";
+      break;
     case CSR_CLASS_SMSTATEEN:
     case CSR_CLASS_SMSTATEEN_32:
       is_rv32_only = (csr_class == CSR_CLASS_SMSTATEEN_32);
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.d b/gas/testsuite/gas/riscv/csr-dw-regnums.d
index fd830666ab89..a87df625da9d 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.d
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.d
@@ -324,6 +324,10 @@ Contents of the .* section:
   DW_CFA_offset_extended_sf: r4888 \(mvienh\) at cfa\+3168
   DW_CFA_offset_extended_sf: r4889 \(mviph\) at cfa\+3172
   DW_CFA_offset_extended_sf: r4948 \(miph\) at cfa\+3408
+  DW_CFA_offset_extended_sf: r5952 \(mnscratch\) at cfa\+7424
+  DW_CFA_offset_extended_sf: r5953 \(mnepc\) at cfa\+7428
+  DW_CFA_offset_extended_sf: r5954 \(mncause\) at cfa\+7432
+  DW_CFA_offset_extended_sf: r5956 \(mnstatus\) at cfa\+7440
   DW_CFA_offset_extended_sf: r4876 \(mstateen0\) at cfa\+3120
   DW_CFA_offset_extended_sf: r4877 \(mstateen1\) at cfa\+3124
   DW_CFA_offset_extended_sf: r4878 \(mstateen2\) at cfa\+3128
diff --git a/gas/testsuite/gas/riscv/csr-dw-regnums.s b/gas/testsuite/gas/riscv/csr-dw-regnums.s
index b8b0f7902297..3ea3853a2cc5 100644
--- a/gas/testsuite/gas/riscv/csr-dw-regnums.s
+++ b/gas/testsuite/gas/riscv/csr-dw-regnums.s
@@ -321,6 +321,11 @@ _start:
 	.cfi_offset mvienh, 3168
 	.cfi_offset mviph, 3172
 	.cfi_offset miph, 3408
+	# Smrnmi extension
+	.cfi_offset mnscratch, 7424
+	.cfi_offset mnepc, 7428
+	.cfi_offset mncause, 7432
+	.cfi_offset mnstatus, 7440
 	# Smstateen extension
 	.cfi_offset mstateen0, 3120
 	.cfi_offset mstateen1, 3124
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index ee41e1025cce..9c2bf4bc9628 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+31959073[ 	]+csrw[ 	]+mviph,a1
 [ 	]+[0-9a-f]+:[ 	]+35402573[ 	]+csrr[ 	]+a0,miph
 [ 	]+[0-9a-f]+:[ 	]+35459073[ 	]+csrw[ 	]+miph,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index e677b78b8bb8..b00515d2cf13 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -444,6 +444,14 @@
 .*Warning: invalid CSR `miph', needs `smaia' extension
 .*Warning: invalid CSR `miph', needs rv32i extension
 .*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index a83b1bf68f98..9783cb795e2c 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+31959073[ 	]+csrw[ 	]+mviph,a1
 [ 	]+[0-9a-f]+:[ 	]+35402573[ 	]+csrr[ 	]+a0,miph
 [ 	]+[0-9a-f]+:[ 	]+35459073[ 	]+csrw[ 	]+miph,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index 81ca86ca7bcc..da5167dab7e3 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -442,6 +442,14 @@
 .*Warning: invalid CSR `miph', needs `smaia' extension
 .*Warning: invalid CSR `miph', needs rv32i extension
 .*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index 612aac280768..e39473062d5a 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+31959073[ 	]+csrw[ 	]+mviph,a1
 [ 	]+[0-9a-f]+:[ 	]+35402573[ 	]+csrr[ 	]+a0,miph
 [ 	]+[0-9a-f]+:[ 	]+35459073[ 	]+csrw[ 	]+miph,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 1c0bb4ef2d8f..011e5d578309 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -304,6 +304,14 @@
 .*Warning: invalid CSR `miph', needs `smaia' extension
 .*Warning: invalid CSR `miph', needs rv32i extension
 .*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
index 0fe849c269c2..819292888aaa 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d
@@ -623,6 +623,14 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+31959073[ 	]+csrw[ 	]+mviph,a1
 [ 	]+[0-9a-f]+:[ 	]+35402573[ 	]+csrr[ 	]+a0,miph
 [ 	]+[0-9a-f]+:[ 	]+35459073[ 	]+csrw[ 	]+miph,a1
+[ 	]+[0-9a-f]+:[ 	]+74002573[ 	]+csrr[ 	]+a0,mnscratch
+[ 	]+[0-9a-f]+:[ 	]+74059073[ 	]+csrw[ 	]+mnscratch,a1
+[ 	]+[0-9a-f]+:[ 	]+74102573[ 	]+csrr[ 	]+a0,mnepc
+[ 	]+[0-9a-f]+:[ 	]+74159073[ 	]+csrw[ 	]+mnepc,a1
+[ 	]+[0-9a-f]+:[ 	]+74202573[ 	]+csrr[ 	]+a0,mncause
+[ 	]+[0-9a-f]+:[ 	]+74259073[ 	]+csrw[ 	]+mncause,a1
+[ 	]+[0-9a-f]+:[ 	]+74402573[ 	]+csrr[ 	]+a0,mnstatus
+[ 	]+[0-9a-f]+:[ 	]+74459073[ 	]+csrw[ 	]+mnstatus,a1
 [ 	]+[0-9a-f]+:[ 	]+30c02573[ 	]+csrr[ 	]+a0,mstateen0
 [ 	]+[0-9a-f]+:[ 	]+30c59073[ 	]+csrw[ 	]+mstateen0,a1
 [ 	]+[0-9a-f]+:[ 	]+30d02573[ 	]+csrr[ 	]+a0,mstateen1
diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.l b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
index c65d0b48e414..daf7e94bbace 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p9p1.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.l
@@ -494,6 +494,14 @@
 .*Warning: invalid CSR `miph', needs `smaia' extension
 .*Warning: invalid CSR `miph', needs rv32i extension
 .*Warning: invalid CSR `miph', needs `smaia' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnscratch', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mncause', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
+.*Warning: invalid CSR `mnstatus', needs `smrnmi' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen0', needs `smstateen' extension
 .*Warning: invalid CSR `mstateen1', needs `smstateen' extension
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index c7406ce34c2e..3508c42f623c 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -350,6 +350,12 @@
 	csr mviph
 	csr miph
 
+	# Smrnmi extension
+	csr mnscratch
+	csr mnepc
+	csr mncause
+	csr mnstatus
+
 	# Smstateen/Ssstateen extensions
 	csr mstateen0
 	csr mstateen1
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.d b/gas/testsuite/gas/riscv/smrnmi-noarch.d
new file mode 100644
index 000000000000..d28da9736300
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i
+#source: smrnmi.s
+#error_output: smrnmi-noarch.l
diff --git a/gas/testsuite/gas/riscv/smrnmi-noarch.l b/gas/testsuite/gas/riscv/smrnmi-noarch.l
new file mode 100644
index 000000000000..1ad5141c1245
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi-noarch.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `mnret', extension `smrnmi' required
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d
new file mode 100644
index 000000000000..2b628e91a103
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.d
@@ -0,0 +1,10 @@
+#as: -march=rv32i_smrnmi
+#source: smrnmi.s
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+70200073[ 	]+mnret
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s
new file mode 100644
index 000000000000..f2008bd8704e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/smrnmi.s
@@ -0,0 +1,2 @@
+target:
+	mnret
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 06e3df0f5a63..d80c7fb5a876 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2055,6 +2055,9 @@
 #define MASK_VDOTUVV  0xfc00707f
 #define MATCH_VFDOTVV  0xe4001057
 #define MASK_VFDOTVV  0xfc00707f
+/* Smrnmi instruction.  */
+#define MATCH_MNRET 0x70200073
+#define MASK_MNRET 0xffffffff
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -2673,6 +2676,11 @@
 #define CSR_MVIENH   0x318
 #define CSR_MVIPH    0x319
 #define CSR_MIPH     0x354
+/* Smrnmi extension CSR addresses.  */
+#define CSR_MNSCRATCH 0x740
+#define CSR_MNEPC 0x741
+#define CSR_MNCAUSE 0x742
+#define CSR_MNSTATUS 0x744
 /* Smstateen extension */
 #define CSR_MSTATEEN0 0x30c
 #define CSR_MSTATEEN1 0x30d
@@ -3106,6 +3114,8 @@ DECLARE_INSN(hsv_b, MATCH_HSV_B, MASK_HSV_B)
 DECLARE_INSN(hsv_h, MATCH_HSV_H, MASK_HSV_H)
 DECLARE_INSN(hsv_w, MATCH_HSV_W, MASK_HSV_W)
 DECLARE_INSN(hsv_d, MATCH_HSV_D, MASK_HSV_D)
+/* Smrnmi instructions.  */
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
 /* Zicbop instructions.  */
 DECLARE_INSN(prefetch_r, MATCH_PREFETCH_R, MASK_PREFETCH_R);
 DECLARE_INSN(prefetch_w, MATCH_PREFETCH_W, MASK_PREFETCH_W);
@@ -3550,6 +3560,11 @@ DECLARE_CSR(mieh, CSR_MIEH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_
 DECLARE_CSR(mvienh, CSR_MVIENH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mviph, CSR_MVIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(miph, CSR_MIPH, CSR_CLASS_SMAIA_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Smrnmi extension CSRs.  */
+DECLARE_CSR(mnscratch, CSR_MNSCRATCH, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnepc, CSR_MNEPC, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mncause, CSR_MNCAUSE, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(mnstatus, CSR_MNSTATUS, CSR_CLASS_SMRNMI, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 /* Smstateen/Ssstateen extensions.  */
 DECLARE_CSR(mstateen0, CSR_MSTATEEN0, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
 DECLARE_CSR(mstateen1, CSR_MSTATEEN1, CSR_CLASS_SMSTATEEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index c3cbde600cb0..d979ef4ac6db 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -405,6 +405,7 @@ enum riscv_insn_class
   INSN_CLASS_ZKND_OR_ZKNE,
   INSN_CLASS_V,
   INSN_CLASS_ZVEF,
+  INSN_CLASS_SMRNMI,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 0e691544f9bc..2194289469cd 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1847,6 +1847,9 @@ const struct riscv_opcode riscv_opcodes[] =
 {"sfence.vma", 0, INSN_CLASS_I, "s,t", MATCH_SFENCE_VMA, MASK_SFENCE_VMA, match_opcode, 0 },
 {"wfi",        0, INSN_CLASS_I, "",    MATCH_WFI, MASK_WFI, match_opcode, 0 },
 
+/* Smrnmi instructions.  */
+{"mnret",           0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },
+
 /* Svinval instructions.  */
 {"sinval.vma",      0, INSN_CLASS_SVINVAL, "s,t", MATCH_SINVAL_VMA, MASK_SINVAL_VMA, match_opcode, 0 },
 {"sfence.w.inval",  0, INSN_CLASS_SVINVAL, "",    MATCH_SFENCE_W_INVAL, MASK_SFENCE_W_INVAL, match_opcode, 0 },
