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[8.43.85.97]) by mx.google.com with ESMTPS id qa42-20020a17090786aa00b007ae26c753edsi12260236ejc.52.2022.11.28.17.25.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Nov 2022 17:25:58 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=TwpK2F0i; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8910F38362E8 for ; Tue, 29 Nov 2022 01:24:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8910F38362E8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669685063; bh=PJMMrEdiwCvmAy1Mw3xBsl7KP2KRMHO6z78+bApWW8E=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=TwpK2F0iBjNhZbuBBcjEss3vQqX6/56nV8YJgECnF3GJrFlTeCNcdXgncRGPtHY74 U9wR5oeUSOkx+ahj4R3Voj6bBNwY0c13Mtv5mdZaazNJqXgQ8yZ6FUA6xDS7USrwYk otygLxgjSVOv1sxtLCtg/zGorfiJ+8Ggd7UycZww= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 05FB53839D82 for ; Tue, 29 Nov 2022 01:24:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 05FB53839D82 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 66255300089; Tue, 29 Nov 2022 01:24:11 +0000 (UTC) To: Tsukasa OI Cc: binutils@sourceware.org Subject: [REVIEW ONLY 1/3] RISC-V: Add "XUN@S" operand type Date: Tue, 29 Nov 2022 01:23:57 +0000 Message-Id: <0187562c00ee6c8ba82439bd61e46a1899b9f916.1669684988.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1750791785066906888?= X-GMAIL-MSGID: =?utf-8?q?1750791785066906888?= From: Tsukasa OI This is a variant of operand type "XuN@S" but when disassembling, it's printed as a hexadecimal number. The author intends to use this operand type on: - Shift amount operands on 'P'-extension proposal's shift instructions (to make them consistent with regular shift instructions) - Landing pad label operand on the 'Zisslpcfi' extension proposal (because they allow three different precision of landing pad label [9, 17 and 25-bits] with up to three likely consecutive instructions with 9, 8 and 8-bit immediates respectively, printing them as binary- based will fit better to these instructions) gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn, riscv_ip): Add new operand type and its handling. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Print new operand type value as a hexadecimal number. --- gas/config/tc-riscv.c | 2 ++ opcodes/riscv-dis.c | 9 ++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 0682eb355241..b58b7bc0cb05 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1399,6 +1399,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 's': /* 'XsN@S' ... N-bit signed immediate at bit S. */ goto use_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ goto use_imm; use_imm: n = strtol (oparg + 1, (char **)&oparg, 10); @@ -3437,6 +3438,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, sign = true; goto parse_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ sign = false; goto parse_imm; parse_imm: diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 0e1f3b4610aa..b3127dccb3e0 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -587,8 +587,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info size_t n; size_t s; bool sign; + char opch = *++oparg; - switch (*++oparg) + switch (opch) { case 'l': /* Literal. */ oparg++; @@ -603,6 +604,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info sign = true; goto print_imm; case 'u': /* 'XuN@S' ... N-bit unsigned immediate at bit S. */ + case 'U': /* 'XUN@S' ... same but disassembled as hex. */ sign = false; goto print_imm; print_imm: @@ -613,8 +615,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info oparg--; if (!sign) - print (info->stream, dis_style_immediate, "%lu", - (unsigned long)EXTRACT_U_IMM (n, s, l)); + print (info->stream, dis_style_immediate, + opch == 'U' ? "0x%lx" : "%lu", + (unsigned long) EXTRACT_U_IMM (n, s, l)); else print (info->stream, dis_style_immediate, "%li", (signed long)EXTRACT_S_IMM (n, s, l));