Show patches with: Submitter = Tsukasa OI       |    Archived = No       |   199 patches
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Patch Series A/R/T S/W/F Date Submitter Delegate State
[v2,06/11] RISC-V: Use static xlen on ADDIW sequence RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
[v2,05/11] RISC-V: One time CSR hash table initialization RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
[v2,04/11] RISC-V: Split riscv_get_map_state into two steps RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
[v2,03/11] RISC-V: Make mapping symbol checking consistent RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
[v2,02/11] RISC-V: Add test for 'Zfinx' register switching RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
[v2,01/11] opcodes/riscv-dis.c: More tidying RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-28 Tsukasa OI Accepted
RISC-V: Allow merging 'H' extension RISC-V: Allow merging 'H' extension - - - 1-- 2022-11-26 Tsukasa OI Accepted
[v4,3/3] RISC-V: Better support for long instructions (tests) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v4,2/3] RISC-V: Better support for long instructions (assembler) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v4,1/3] RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v3,1/3] RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v3,2/2] RISC-V: Better support for long instructions (assembler) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v3,1/2] RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-25 Tsukasa OI Accepted
[v2,2/2] RISC-V: Better support for long instructions RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-23 Tsukasa OI Accepted
[v2,1/2] RISC-V: Make .insn tests stricter RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-23 Tsukasa OI Accepted
[v3,3/3] gdb/testsuite: RISC-V disassembler option tests RISC-V: Add overridable "priv-spec" and "arch" disassembler options - - - -1- 2022-11-20 Tsukasa OI Unresolved
[v3,2/3] RISC-V: Add "arch" disassembler option RISC-V: Add overridable "priv-spec" and "arch" disassembler options - - - -1- 2022-11-20 Tsukasa OI Unresolved
[v3,1/3] RISC-V: Make "priv-spec" overridable RISC-V: Add overridable "priv-spec" and "arch" disassembler options - - - -1- 2022-11-20 Tsukasa OI Unresolved
[3/3] RISC-V: Optimized search on mapping symbols RISC-V: Disassembler Core Optimization 1-2 (Mapping symbols) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[2/3] RISC-V: Per-section private data initialization RISC-V: Disassembler Core Optimization 1-2 (Mapping symbols) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[1/3] RISC-V: Easy optimization on riscv_search_mapping_symbol RISC-V: Disassembler Core Optimization 1-2 (Mapping symbols) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[3/3] RISC-V: Cache instruction support RISC-V: Disassembler Core Optimization 1-1 (Hash table and Caching) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[2/3] RISC-V: Fallback on faster hash table RISC-V: Disassembler Core Optimization 1-1 (Hash table and Caching) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[1/3] RISC-V: Use faster hash table on disassembling RISC-V: Disassembler Core Optimization 1-1 (Hash table and Caching) - - - -1- 2022-11-20 Tsukasa OI Unresolved
[2/2] RISC-V: Better support for long instructions RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-19 Tsukasa OI Accepted
[1/2] RISC-V: Make .insn tests stricter RISC-V: Better support for long instructions (64 < x <= 176 [bits]) - - - 1-- 2022-11-19 Tsukasa OI Accepted
[v4,8/8] RISC-V: Use defined mask and match values RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,7/8] RISC-V: Make alias instructions aliases RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,5/8] RISC-V: Complete tidying up with SCALL and SBREAK RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,4/8] RISC-V: Remove unused instruction macros RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,3/8] RISC-V: Remove spaces in opcode entries RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
[v4,1/8] RISC-V: Add a space at the end of pinfo RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-18 Tsukasa OI Accepted
RISC-V: Add INSN_DREF to memory read/write instructions RISC-V: Add INSN_DREF to memory read/write instructions - - - 1-- 2022-11-18 Tsukasa OI Accepted
[11/11] RISC-V: Move disassembler private data initialization RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[10/11] RISC-V: Reorganize arch-related initialization and management RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[09/11] RISC-V: Reorganize disassembler state initialization RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[08/11] RISC-V: Split match/print steps on disassembler RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[07/11] opcodes/riscv-dis.c: Add form feed for separation RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[06/11] RISC-V: Use static xlen on ADDIW sequence RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[05/11] RISC-V: One time CSR hash table initialization RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[04/11] RISC-V: Split riscv_get_map_state into two steps RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[03/11] RISC-V: Make mapping symbol checking consistent RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[02/11] RISC-V: Add test for 'Zfinx' register switching RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[01/11] opcodes/riscv-dis.c: More tidying RISC-V: Requirements for disassembler optimizations batch 1 - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,8/8] RISC-V: Use defined mask and match values RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,7/8] RISC-V: Make alias instructions aliases RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,5/8] RISC-V: Complete tidying up with SCALL and SBREAK RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,4/8] RISC-V: Remove unused instruction macros RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,3/8] RISC-V: Remove spaces in opcode entries RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[v3,1/8] RISC-V: Add a space at the end of pinfo RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-11-15 Tsukasa OI Accepted
[12/12] RISC-V: Combine/enhance 'Zk*'/'Zbk*' extension tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[11/12] RISC-V: Reorganize/enhance 'Zb*' extension tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[10/12] RISC-V: Enhance 'Zicbop' testcases RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[09/12] RISC-V: Combine/enhance 'Zicbo[mz]' extension tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[08/12] RISC-V: Refine/enhance 'M'/'Zmmul' extension tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[07/12] RISC-V: Combine complex extension error handling tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[06/12] RISC-V: Reorganize/enhance {sign, zero}-extension instructions RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[05/12] RISC-V: Redefine "nop" test RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[04/12] RISC-V: GAS: Add basic shared test utilities RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[03/12] RISC-V: Tidying related to 'Zfinx' disassembler test RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[02/12] RISC-V: Tidy disassembler corner case tests RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[01/12] RISC-V: Remove unnecessary empty matching file RISC-V: Test refinements (Batch 1) - - - 1-- 2022-11-05 Tsukasa OI Accepted
[REVIEW,ONLY,2/2] NEAR-RATIFICATION RISC-V: Add platform property/capability extensions NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles - - - 1-- 2022-11-03 Tsukasa OI Accepted
[REVIEW,ONLY,1/2] NEAR-RATIFICATION RISC-V: Add 'Ssstateen' extension and its CSRs NEAR RATIFICATION RISC-V: Extensions from the RISC-V Profiles - - - 1-- 2022-11-03 Tsukasa OI Accepted
RISC-V: Emit mapping symbol with ISA string if non-default arch is used RISC-V: Emit mapping symbol with ISA string if non-default arch is used - - - 1-- 2022-10-28 Tsukasa OI Accepted
RISC-V: Fix build failure for -Werror=maybe-uninitialized RISC-V: Fix build failure for -Werror=maybe-uninitialized - - - 1-- 2022-10-28 Tsukasa OI Accepted
include: Define macro to ignore -Wdeprecated-declarations on GCC include: Define macro to ignore -Wdeprecated-declarations on GCC - - - 1-- 2022-10-27 Tsukasa OI Accepted
[RFC] RISC-V: Allocate "various" operand type [RFC] RISC-V: Allocate "various" operand type - - - 1-- 2022-10-25 Tsukasa OI Accepted
[17/40] sim/lm32: Add explicit casts sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[16/40] sim/lm32: fix some missing function declaration warnings sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[14/40] sim/frv: Add explicit casts sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[13/40] sim/frv: Initialize some variables sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[12/40] sim/frv: Initialize nesr variable sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[11/40] cpu/frv: Initialize some variables sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[10/40] sim/erc32: Use int32_t as IRQ callback argument sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[09/40] sim/erc32: Use int32_t as event callback argument sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[08/40] sim/erc32: Insert void parameter sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[07/40] sim/cris: Regenerate with CGEN sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[06/40] sim/cris: Move declarations of f_specific_init sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[04/40] cpu/cris: Initialize some variables on CRIS CPU sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[03/40] sim/aarch64: Remove unused functions sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[02/40] sim: Check known getrusage declaration existence sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
[01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib sim+gdb: Suppress warnings if built with Clang (big batch 1) - - - 1-- 2022-10-20 Tsukasa OI Accepted
RISC-V: Remove RV32EF conflict RISC-V: Remove RV32EF conflict - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,8/8] RISC-V: Use defined mask and match values RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,7/8] RISC-V: Make alias instructions aliases RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,6/8] RISC-V: Tidying up with fmv.w.x and fmv.x.w RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,5/8] RISC-V: Complete tidying up with SCALL and SBREAK RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,4/8] RISC-V: Remove unused instruction macros RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,3/8] RISC-V: Remove spaces in opcode entries RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,2/8] RISC-V: Fix obvious misalignments ('Zbb'/'Zba') RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
[v2,1/8] RISC-V: Add a space at the end of pinfo RISC-V: Various opcode tidying (batch 1) - - - 1-- 2022-10-19 Tsukasa OI Accepted
binutils: Remove unused substitution PROGRAM binutils: Remove unused substitution PROGRAM - - - 1-- 2022-10-19 Tsukasa OI Accepted
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