Show patches with: Submitter = Xiao Zeng       |   9 patches
Patch Series A/R/T S/W/F Date Submitter Delegate State
[PING^2,v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' [PING^2,v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' - 1 - -1- 2023-12-15 Xiao Zeng Unresolved
[PING^1,v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' [PING^1,v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' - - - -1- 2023-12-07 Xiao Zeng Unresolved
[v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' [v2] RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr' - - - -1- 2023-11-27 Xiao Zeng Unresolved
RISC-V: Imply 'Zicsr' from 'Zicntr' and 'Zihpm' RISC-V: Imply 'Zicsr' from 'Zicntr' and 'Zihpm' - - - -1- 2023-11-27 Xiao Zeng Unresolved
RISC-V: Update 'Zfa' extension version RISC-V: Update 'Zfa' extension version - - - -1- 2023-11-21 Xiao Zeng Unresolved
RISC-V: Correction of machine registers mapping to dwarf registers RISC-V: Correction of machine registers mapping to dwarf registers - - - 1-- 2022-12-06 Xiao Zeng Accepted
[v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard [v2] RISC-V: Make R_RISCV_SUB6 conforms to riscv ABI standard - - - 1-- 2022-11-21 Xiao Zeng Accepted
[v1,1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard - 1 - 1-- 2022-11-15 Xiao Zeng Accepted
[1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard - 1 - 1-- 2022-10-14 Xiao Zeng Accepted