mbox series

[0/3] x86: correct checking of matching operand sizes

Message ID dd561fd8-329c-eabb-2ef2-4c1844cacb77@suse.com
Headers
Series x86: correct checking of matching operand sizes |

Message

Jan Beulich Nov. 23, 2022, 10:32 a.m. UTC 
  I've spotted a few cases where operand sizes matching wasn't really
checked, leading to malformed insn/operand combinations to be
accepted (in the first patch another anomaly is also taken care of).
This mainly, but not only affects Intel Syntax.

1: correct handling of LAR and LSL
2: add missing CheckRegSize
3: widen applicability and use of CheckRegSize

Jan

Comments

H.J. Lu Nov. 23, 2022, 9:39 p.m. UTC | #1 
On Wed, Nov 23, 2022 at 2:32 AM Jan Beulich <jbeulich@suse.com> wrote:
>
> I've spotted a few cases where operand sizes matching wasn't really
> checked, leading to malformed insn/operand combinations to be
> accepted (in the first patch another anomaly is also taken care of).
> This mainly, but not only affects Intel Syntax.
>
> 1: correct handling of LAR and LSL
> 2: add missing CheckRegSize
> 3: widen applicability and use of CheckRegSize
>
> Jan

OK to all.

Thanks.
Jan Beulich Nov. 24, 2022, 8:38 a.m. UTC | #2 
On 23.11.2022 22:39, H.J. Lu wrote:
> On Wed, Nov 23, 2022 at 2:32 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> I've spotted a few cases where operand sizes matching wasn't really
>> checked, leading to malformed insn/operand combinations to be
>> accepted (in the first patch another anomaly is also taken care of).
>> This mainly, but not only affects Intel Syntax.
>>
>> 1: correct handling of LAR and LSL
>> 2: add missing CheckRegSize
>> 3: widen applicability and use of CheckRegSize
>>
>> Jan
> 
> OK to all.

Thanks. I've committed these, but I wonder whether you may have overlooked
the remark in the last patch as to the name "CheckRegSize".

Jan