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[0/2] RISC-V: Preparation for more generic linker relaxation

Message ID cover.1697259797.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Preparation for more generic linker relaxation |

Message

Tsukasa OI Oct. 14, 2023, 5:03 a.m. UTC 
  Hi,

It *seems* a generic tidying patch set which does nothing useful.  However,
this is a part of my attempt to implement Qualcomm's proposal of Code Size
Reduction Instructions (tentatively called 'Zics') but without any 'Zics'-
specific code.

Qualcomm's proposal of Code Size Reduction Instructions:
<https://lists.riscv.org/g/tech-profiles/topic/101784675#332>
My test branch implementing most of them (except assembler/linker support of
PC-relative load instructions):
<https://github.com/a4lg/binutils-gdb/tree/qualcomm_zics>

This patch set intends to improve clarity and maintainability of the linker
relaxation so that 'Zics'-related linker relaxation can be implemented
easily.  I believe that it will be helpful even if 'Zics' is not approved.


'Zics' attempts to reduce the code size by providing PC-relative load
instructions (as well as other many additional addressing modes).  However,
Qualcomm's proposal of the PC-relative load instructions is exactly the same
as GNU Binutils' macro load instructions (except "lb" and "lbu", that
Qualcomm's proposal does not have a counterpart).

GNU Binutils' macro load instruction:

                        label:
                                lw      a0, symbol

will generate instruction sequence like this:

   0:   00000517                auipc   a0,0x0
                        0: R_RISCV_PCREL_HI20   symbol
                        0: R_RISCV_RELAX        *ABS*
   4:   00052503                lw      a0,0(a0) # 0 <_start>
                        4: R_RISCV_PCREL_LO12_I label
                        4: R_RISCV_RELAX        *ABS*

If "symbol" is near enough (relative to the second "lw"), the linker may
relax the instruction sequence like this (pseudo objdump output):

   0:   d0807503                lw      a0,400 <symbol>
        # This "lw" encoding is a proposed variant by Qualcomm.

It will require a few changes (riscv_pc_relax_hi_reloc must store additional
information such like reference count to keep track of whether HI20
instruction can be removed; this is because we may not be able to remove
instruction with HI20 relocation if (a) multiple LO12 relocations are
corresponding (b) there are multiple types of linker relaxations utilizing
this type and (c) at least one of them, relaxation possibility is determined
based on the instruction address with LO12 relocation, not HI20 one).


That got a quite long but even if Qualcomm's proposal didn't progress any
further, this patch alone set will be helpful to implement such like
**proper** Zero-page relaxation (current zero-page relaxation reusing the
code from PCREL->GPREL is too restrictive).

Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Group relaxation features
  RISC-V: Prepare for more generic PCREL relaxations

 bfd/elfnn-riscv.c | 176 ++++++++++++++++++++++++++--------------------
 1 file changed, 100 insertions(+), 76 deletions(-)


base-commit: 5e2c9ce9c0bf4763a6d17a3a5bee9011ec710f10