mbox series

[0/1] RISC-V: Make XVentanaCondOps RV64 only

Message ID cover.1693359513.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Make XVentanaCondOps RV64 only |

Message

Tsukasa OI Aug. 30, 2023, 1:38 a.m. UTC 
  Hello,

I noticed that two instructions in the XVentanaCondOps vendor extension --
"vt.maskc" and "vt.maskcn" -- are defined for all XLEN values.

This is against the manual and LLVM.


1. The instruction manual

<https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>

Currently defines the instructions only for RV64.

> All current cores by Ventana Micro implement RV64 and are designed as
> 64-bit only, the RV32-column is marked "n/a".

But it also says it's (in theory) XLEN-agonistic.

> The instructions in the XVentanaCondOps extension are defined to operate
> on XLEN and would thus be directly applicable to RV32.


2. LLVM (llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td)

> let Predicates = [IsRV64, HasVendorXVentanaCondOps]

It indicates that XVentanaCondOps instructions are only enabled on RV64.



Unless Ventana is working on some RV32 processors (and soon to be released
), I think disabling XVentanaCondOps instructions on RV32 would be safer
(to prevent possible misuses).  I would like to hear thoughts especially
from Ventana employees since I am just a volunteer.

I also chose not to reject XVentanaCondOps + RV32 because it is not stated
that is illegal (unlike Zcf + RV64).  This patch set makes XVentanaCondOps
+ RV32 empty (yet legal).


Sincerely,
Tsukasa




Tsukasa OI (1):
  RISC-V: Make XVentanaCondOps RV64 only

 gas/testsuite/gas/riscv/x-ventana-condops-32.d | 3 +++
 gas/testsuite/gas/riscv/x-ventana-condops-32.l | 3 +++
 opcodes/riscv-opc.c                            | 4 ++--
 3 files changed, 8 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.d
 create mode 100644 gas/testsuite/gas/riscv/x-ventana-condops-32.l


base-commit: 0637da3c7325b28a2c05f016d7f290513b1cd19b

Comments

Greg Favor Aug. 30, 2023, 3:21 a.m. UTC | #1 
On Tue, Aug 29, 2023 at 6:38 PM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> Unless Ventana is working on some RV32 processors (and soon to be released
> ), I think disabling XVentanaCondOps instructions on RV32 would be safer
> (to prevent possible misuses).  I would like to hear thoughts especially
> from Ventana employees since I am just a volunteer.
>

Representing Ventana, what you say is correct, i.e. we have no plans to do
RV32 processors.

Greg


> I also chose not to reject XVentanaCondOps + RV32 because it is not stated
> that is illegal (unlike Zcf + RV64).  This patch set makes XVentanaCondOps
> + RV32 empty (yet legal).
>
Tsukasa OI Aug. 30, 2023, 3:59 a.m. UTC | #2 
On 2023/08/30 12:21, Greg Favor wrote:
> On Tue, Aug 29, 2023 at 6:38 PM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
> 
>     Unless Ventana is working on some RV32 processors (and soon to be
>     released
>     ), I think disabling XVentanaCondOps instructions on RV32 would be safer
>     (to prevent possible misuses).  I would like to hear thoughts especially
>     from Ventana employees since I am just a volunteer.
> 
> 
> Representing Ventana, what you say is correct, i.e. we have no plans to
> do RV32 processors.
> 
> Greg

Thanks for the official information.  Committing.

(we could make XVentanaCondOps invalid on RV32 considering your answer
but that's for another time.)

Tsukasa

>  
> 
>     I also chose not to reject XVentanaCondOps + RV32 because it is not
>     stated
>     that is illegal (unlike Zcf + RV64).  This patch set makes
>     XVentanaCondOps
>     + RV32 empty (yet legal).
>