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[0/1] RISC-V: Imply 'Zicsr' from 'Zve32x'

Message ID cover.1691021025.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Imply 'Zicsr' from 'Zve32x' |

Message

Tsukasa OI Aug. 3, 2023, 12:03 a.m. UTC 
  Hi,

In September 2022, I raised this issue (along with a patch set):
<https://sourceware.org/pipermail/binutils/2022-September/122757.html>
<https://sourceware.org/pipermail/binutils/2022-September/122761.html>
that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.

At that time, we couldn't conclude that unprivileged extensions with CSRs
imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
withdrawn.

I recently raised issues at the repository of related specifications and at
the vector specification, it's concluded that 'Zve32x' (minimum vector
subset) implies 'Zicsr':
<https://github.com/riscv/riscv-v-spec/issues/908>
<https://github.com/riscv/riscv-v-spec/issues/909>

Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Imply 'Zicsr' from 'Zve32x'

 bfd/elfxx-riscv.c | 1 +
 1 file changed, 1 insertion(+)


base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647

Comments

Nelson Chu Aug. 3, 2023, 12:39 a.m. UTC | #1 
On Thu, Aug 3, 2023 at 8:04 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> Hi,
>
> In September 2022, I raised this issue (along with a patch set):
> <https://sourceware.org/pipermail/binutils/2022-September/122757.html>
> <https://sourceware.org/pipermail/binutils/2022-September/122761.html>
> that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.
>
> At that time, we couldn't conclude that unprivileged extensions with CSRs
> imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
> withdrawn.
>
> I recently raised issues at the repository of related specifications and at
> the vector specification, it's concluded that 'Zve32x' (minimum vector
> subset) implies 'Zicsr':
> <https://github.com/riscv/riscv-v-spec/issues/908>
> <https://github.com/riscv/riscv-v-spec/issues/909>
>
> Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
> should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.
>

Okay, sounds reasonable.

Thanks
Nelson


> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (1):
>   RISC-V: Imply 'Zicsr' from 'Zve32x'
>
>  bfd/elfxx-riscv.c | 1 +
>  1 file changed, 1 insertion(+)
>
>
> base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
> --
> 2.41.0
>
>
Tsukasa OI Aug. 3, 2023, 1:40 a.m. UTC | #2 
On 2023/08/03 9:39, Nelson Chu wrote:
> 
> 
> On Thu, Aug 3, 2023 at 8:04 AM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
> 
>     Hi,
> 
>     In September 2022, I raised this issue (along with a patch set):
>     <https://sourceware.org/pipermail/binutils/2022-September/122757.html <https://sourceware.org/pipermail/binutils/2022-September/122757.html>>
>     <https://sourceware.org/pipermail/binutils/2022-September/122761.html <https://sourceware.org/pipermail/binutils/2022-September/122761.html>>
>     that some extensions with CSR don't imply 'Zicsr' on the GNU toolchain.
> 
>     At that time, we couldn't conclude that unprivileged extensions with
>     CSRs
>     imply 'Zicsr' or not.  So part of my patch set ('Zkr' and 'Zve32x') is
>     withdrawn.
> 
>     I recently raised issues at the repository of related specifications
>     and at
>     the vector specification, it's concluded that 'Zve32x' (minimum vector
>     subset) implies 'Zicsr':
>     <https://github.com/riscv/riscv-v-spec/issues/908
>     <https://github.com/riscv/riscv-v-spec/issues/908>>
>     <https://github.com/riscv/riscv-v-spec/issues/909
>     <https://github.com/riscv/riscv-v-spec/issues/909>>
> 
>     Combining the fact that LLVM already implies 'Zicsr' from 'Zve32x', it
>     should be safe to imply 'Zicsr' from 'Zve32x' in the GNU toolchain.
> 
> 
> Okay, sounds reasonable.
> 
> Thanks
> Nelson

Committed!

Thanks,
Tsukasa

>  
> 
>     Thanks,
>     Tsukasa
> 
> 
> 
> 
>     Tsukasa OI (1):
>       RISC-V: Imply 'Zicsr' from 'Zve32x'
> 
>      bfd/elfxx-riscv.c | 1 +
>      1 file changed, 1 insertion(+)
> 
> 
>     base-commit: 4b177a76d5b759ba631568fb69e8750e99b43647
>     -- 
>     2.41.0
>