mbox series

[v4,0/1] RISC-V: Extensions from the RISC-V Profiles

Message ID cover.1690329932.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Extensions from the RISC-V Profiles |

Message

Tsukasa OI July 26, 2023, 12:05 a.m. UTC 
  This patch (set) adds 7 unprivileged extensions and 13 privileged
extensions, all of which denotes certain platform capability / constraint.

This is almost a resend of the previous PATCH v3 (in January 2023) but since
the RISC-V Profiles specification is now ratified, it's much safer to merge.

[Changes: v2 -> v3]

1.  After AIA is upstreamed, I haven't done tidying up with
    riscv_supported_std_s_ext with my rebased branch.  That made location of
    'Ssaia' a bit out of place. PATCH v3 fixes this.
2.  After version 0.8, the new extension 'Sscounterenw' is added but I
    missed that.  PATCH v3 adds support for this new extension correctly.
3.  I made minor changes to ChangeLog part of the commit message
    (I moved 'H' -> 'Zicsr' dependency for a reason but I didn't mentioned
    in the ChangeLog).

[Changes: v3 -> v4]

1.  Rebase against the latest master (with a bit of reordering).
2.  Reorder renamed 'Svade' to reflect canonical order.
3.  Referenced specification is now the ratified one (version 1.0),
    not frozen but draft one (version 0.9.2).

Thanks,
Tsukasa




Tsukasa OI (1):
  RISC-V: Add platform property/capability extensions

 bfd/elfxx-riscv.c | 35 ++++++++++++++++++++++++++++++++++-
 1 file changed, 34 insertions(+), 1 deletion(-)


base-commit: 6296109afcd8c8e89b771fbaf092d17a17d4ea99