mbox series

[REVIEW,ONLY,0/1] UNRATIFIED RISC-V: Add 'Svadu' extension

Message ID cover.1669684692.git.research_trasio@irq.a4lg.com
Headers
Series UNRATIFIED RISC-V: Add 'Svadu' extension |

Message

Tsukasa OI Nov. 29, 2022, 1:18 a.m. UTC 
  *** WAIT FOR SPECIFICATION FREEZE ***
This is an implementation for unratified and not frozen RISC-V extension
and not intended to be merged for now.
The only intent to submit this patchset is to test new instructions for
your (possibly virtual) environment and early review for fast adoption
after ratification.


This patchset adds following unratified extension to GNU Binutils:

-   'Svadu' (Hardware Updating of PTE A/D Bits)
    version 0.1 (may change on ratification)

which adds no instructions or no CSRs (but new CSR bits so 'Zicsr'
dependency is added along with extension name support).

This extension provides CSR-based control of hardware PTE updates.


This is based on the specification documentation, version 0.1:
<https://github.com/riscv/riscv-svadu/releases/tag/vv0.1>




Tsukasa OI (1):
  UNRATIFIED RISC-V: Add 'Svadu' extension

 bfd/elfxx-riscv.c | 2 ++
 1 file changed, 2 insertions(+)


base-commit: cb44f89ce977b1ab2d4063f2487950bddfb75bc7