mbox series

[v4,0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits])

Message ID cover.1669376539.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Better support for long instructions (64 < x <= 176 [bits]) |

Message

Tsukasa OI Nov. 25, 2022, 11:42 a.m. UTC 
  Hello,

c.f. PATCH v1 (with cover letter with some backgrounds):
<https://sourceware.org/pipermail/binutils/2022-November/124516.html>
c.f. PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-November/124596.html>
c.f. PATCH v3:
<https://sourceware.org/pipermail/binutils/2022-November/124643.html>


[Changes: v3 -> v4]

1.  Split to three separate patches
    (disassembler fix, assembler fix and testcases that require both fixes)
2.  PATCH 1/3: Further clarification of the intent of this commit
    (with examples) on the commit message.  No changes in the code.
3.  PATCH 2/3: Minor clarification on comments and the commit message.
    No code changes but some comment changes in tc-riscv.c.
4.  PATCH 3/3: Clarify that it tests both fixes.


[Changes: v2 -> v3]

1.  PATCH v2 1/2 is removed
2.  PATCH v2 2/2 is splitted to PATCH v3 {1,2}/2
    based on the feedback of Jan
    Strict ".byte" testcases are only preserved to test new behavior.
    They are not 4-byte aligned (10 and 22-bytes) and unlikely to change
    any time soon.


[Changes: v1 -> v2]

1.  Rebased (as usual)
2.  PATCH 2/2: Simplified the logic to extract low instruction bits
    (will describe later)
3.  PATCH 2/2: Changed the commit message slightly


Thanks,
Tsukasa




Tsukasa OI (3):
  RISC-V: Better support for long instructions (disassembler)
  RISC-V: Better support for long instructions (assembler)
  RISC-V: Better support for long instructions (tests)

 gas/config/tc-riscv.c                | 41 ++++++++++++++++++++++------
 gas/testsuite/gas/riscv/insn-dwarf.d | 10 ++++++-
 gas/testsuite/gas/riscv/insn-na.d    |  8 ++++++
 gas/testsuite/gas/riscv/insn.d       | 22 +++++++++++++++
 gas/testsuite/gas/riscv/insn.s       |  9 ++++++
 opcodes/riscv-dis.c                  | 14 ++++++----
 6 files changed, 89 insertions(+), 15 deletions(-)


base-commit: ac8df5a1921904b3928429e696ad8b40c612f829

Comments

Jan Beulich Nov. 25, 2022, 1:08 p.m. UTC | #1 
On 25.11.2022 12:42, Tsukasa OI wrote:
> Tsukasa OI (3):
>   RISC-V: Better support for long instructions (disassembler)
>   RISC-V: Better support for long instructions (assembler)
>   RISC-V: Better support for long instructions (tests)

LGTM, but again please wait a day or two with committing in case Nelson
wants to take another look. And thanks for being patient with me.

Jan
Nelson Chu Nov. 28, 2022, 1:53 a.m. UTC | #2 
On Fri, Nov 25, 2022 at 9:08 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 25.11.2022 12:42, Tsukasa OI wrote:
> > Tsukasa OI (3):
> >   RISC-V: Better support for long instructions (disassembler)
> >   RISC-V: Better support for long instructions (assembler)
> >   RISC-V: Better support for long instructions (tests)
>
> LGTM, but again please wait a day or two with committing in case Nelson
> wants to take another look. And thanks for being patient with me.

Hey Jan, thanks for your reply to clarify the roles of us.  FYI, the
.insn test cases were not so stricter because we haven't had any
dis-assembler improvements at that time, so not sure which the
dis-assembler results are better for those cases where the
instructions are not supported.  Anyway, I have seen the details,
which look good to me, too, so please commit these three patches.

Thanks for both of your support, Jan and Tsukasa
Nelson