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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id w13-20020a05640234cd00b0046189831142si4070554edc.7.2022.11.25.03.41.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Nov 2022 03:41:59 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wfBFn3bB; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1E52384F8B4 for ; Fri, 25 Nov 2022 11:41:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1E52384F8B4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1669376518; bh=Gk18/4tqh7C+BzwRTpolzLO7pjHw/Hd+C/X+lWMAzjI=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=wfBFn3bBjRdeF4HD/w9F3No7J+Hg590mVhGVyFeCTeOwZFPwragDnWpZe4O9FShpo OrlnkKNzfa0dhgO5FpU5cAzJLX/26ekNsC6XnoU3EyGd6F8ZjGBtjn9Ai4fhexqntr sUGHJO3Zj1QupFmSTmfMab/ju17RoQxQAMD8ySeI= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 0A50E384F89B for ; Fri, 25 Nov 2022 11:41:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0A50E384F89B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id E8032300089; Fri, 25 Nov 2022 11:41:47 +0000 (UTC) To: Tsukasa OI , Jan Beulich , Nelson Chu Cc: binutils@sourceware.org Subject: [PATCH v3 0/3] RISC-V: Better support for long instructions (64 < x <= 176 [bits]) Date: Fri, 25 Nov 2022 11:41:39 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749907561374700638?= X-GMAIL-MSGID: =?utf-8?q?1750468153701887071?= Hello, c.f. PATCH v1 (with cover letter with some backgrounds): c.f. PATCH v2: c.f. PATCH v3: [Changes: v3 -> v4] 1. Split to three separate patches (disassembler fix, assembler fix and testcases that require both fixes) 2. PATCH 1/3: Further clarification of the intent of this commit (with examples) on the commit message. No changes in the code. 3. PATCH 2/3: Minor clarification on comments and the commit message. No code changes but some comment changes in tc-riscv.c. 4. PATCH 3/3: Clarify that it tests both fixes. [Changes: v2 -> v3] 1. PATCH v2 1/2 is removed 2. PATCH v2 2/2 is splitted to PATCH v3 {1,2}/2 based on the feedback of Jan Strict ".byte" testcases are only preserved to test new behavior. They are not 4-byte aligned (10 and 22-bytes) and unlikely to change any time soon. [Changes: v1 -> v2] 1. Rebased (as usual) 2. PATCH 2/2: Simplified the logic to extract low instruction bits (will describe later) 3. PATCH 2/2: Changed the commit message slightly Thanks, Tsukasa Tsukasa OI (3): RISC-V: Better support for long instructions (disassembler) RISC-V: Better support for long instructions (assembler) RISC-V: Better support for long instructions (tests) gas/config/tc-riscv.c | 41 ++++++++++++++++++++++------ gas/testsuite/gas/riscv/insn-dwarf.d | 10 ++++++- gas/testsuite/gas/riscv/insn-na.d | 8 ++++++ gas/testsuite/gas/riscv/insn.d | 22 +++++++++++++++ gas/testsuite/gas/riscv/insn.s | 9 ++++++ opcodes/riscv-dis.c | 14 ++++++---- 6 files changed, 89 insertions(+), 15 deletions(-) base-commit: ac8df5a1921904b3928429e696ad8b40c612f829