mbox series

[v3,0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits])

Message ID cover.1669342633.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Better support for long instructions (64 < x <= 176 [bits]) |

Message

Tsukasa OI Nov. 25, 2022, 2:17 a.m. UTC 
  Hello,

c.f. PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-November/124516.html>
c.f. PATCH v2:
<https://sourceware.org/pipermail/binutils/2022-November/124596.html>


[Changes: v2 -> v3]

1.  PATCH v2 1/2 is removed
2.  PATCH v2 2/2 is splitted to PATCH v3 {1,2}/2
    based on the feedback of Jan
    Strict ".byte" testcases are only preserved to test new behavior.
    They are not 4-byte aligned (10 and 22-bytes) and unlikely to change
    any time soon.

I hope this can be a good compromise.


[Changes: v1 -> v2]

1.  Rebased (as usual)
2.  PATCH 2/2: Simplified the logic to extract low instruction bits
    (will describe later)
3.  PATCH 2/2: Changed the commit message slightly


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Better support for long instructions (disassembler)
  RISC-V: Better support for long instructions (assembler)

 gas/config/tc-riscv.c                | 38 ++++++++++++++++++++++------
 gas/testsuite/gas/riscv/insn-dwarf.d | 10 +++++++-
 gas/testsuite/gas/riscv/insn-na.d    |  8 ++++++
 gas/testsuite/gas/riscv/insn.d       | 22 ++++++++++++++++
 gas/testsuite/gas/riscv/insn.s       |  9 +++++++
 opcodes/riscv-dis.c                  | 13 ++++++----
 6 files changed, 86 insertions(+), 14 deletions(-)


base-commit: 18a119b83d1f0f661532e5167af1c5549496759c