mbox series

[v2,0/2] RISC-V: Better support for long instructions (64 < x <= 176 [bits])

Message ID cover.1669192210.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Better support for long instructions (64 < x <= 176 [bits]) |

Message

Tsukasa OI Nov. 23, 2022, 8:30 a.m. UTC 
  Hello,

c.f. PATCH v1:
<https://sourceware.org/pipermail/binutils/2022-November/124516.html>


[Changes: v1 -> v2]

1.  Rebased (as usual)
2.  PATCH 2/2: Simplified the logic to extract low instruction bits
    (will describe later)
3.  PATCH 2/2: Changed the commit message slightly

As a part of the process making the logic more flexible to bignum internal
changes, PATCH v1 used a complex logic.  After some investigation, I found
the function: generic_bignum_to_int32.  I decided to use this on PATCH v2.

Despite that it DOES NOT guarantee that it will extract lower 32-bits of a
big number even if the number overflows but it does (on the current design)
and flexible enough to bignum internal changes (I don't want to make
dependencies to something which can be easily changed as long as it is
reasonable enough).  Just for sure, I added a comment for the assumption of
this part.


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Make .insn tests stricter
  RISC-V: Better support for long instructions

 gas/config/tc-riscv.c                | 38 ++++++++++++++++++++++------
 gas/testsuite/gas/riscv/insn-dwarf.d | 10 +++++++-
 gas/testsuite/gas/riscv/insn-na.d    | 28 ++++++++++++--------
 gas/testsuite/gas/riscv/insn.d       | 32 +++++++++++++++++++----
 gas/testsuite/gas/riscv/insn.s       |  9 +++++++
 opcodes/riscv-dis.c                  | 13 ++++++----
 6 files changed, 101 insertions(+), 29 deletions(-)


base-commit: 829b6b3736d972f5fbacda09c82b31802d3b594c