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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sg40-20020a170907a42800b0078081036bdasi10083113ejc.501.2022.11.14.20.31.50 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 20:31:50 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b="x/WaQ9fc"; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 16BC53835794 for <ouuuleilei@gmail.com>; Tue, 15 Nov 2022 04:31:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 16BC53835794 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668486709; bh=SBzFG0knKLjgS/0Uec9GjY/LJJsB02XT0jHD1yVCfBE=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=x/WaQ9fct0C2B1/e0oMozJ0mV0x5Sx+iXIsGAS2eWVU8uYbdWU/Gnvf+ZJJn1ueqR tr9d1stz1qEy9GQuJ1UiWzWkwSLH69Ra0IRD/lIIIbF7O971sDuQBt25SHZsmeWXIr JOMBIFnoy9UmBIdgn6f+qBc/4elFvZvw4k5c7c2c= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 889363836004 for <binutils@sourceware.org>; Tue, 15 Nov 2022 04:31:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 889363836004 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 9B504300089; Tue, 15 Nov 2022 04:31:34 +0000 (UTC) To: Tsukasa OI <research_trasio@irq.a4lg.com>, Nelson Chu <nelson@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Cc: binutils@sourceware.org Subject: [PATCH v3 0/8] RISC-V: Various opcode tidying (batch 1) Date: Tue, 15 Nov 2022 04:31:21 +0000 Message-Id: <cover.1668486687.git.research_trasio@irq.a4lg.com> In-Reply-To: <cover.1666185116.git.research_trasio@irq.a4lg.com> References: <cover.1666185116.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list <binutils.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/binutils>, <mailto:binutils-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/binutils/> List-Post: <mailto:binutils@sourceware.org> List-Help: <mailto:binutils-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/binutils>, <mailto:binutils-request@sourceware.org?subject=subscribe> From: Tsukasa OI via Binutils <binutils@sourceware.org> Reply-To: Tsukasa OI <research_trasio@irq.a4lg.com> Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" <binutils-bounces+ouuuleilei=gmail.com@sourceware.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747121750397381245?= X-GMAIL-MSGID: =?utf-8?q?1749535121192786414?= |
Series |
RISC-V: Various opcode tidying (batch 1)
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Message
Tsukasa OI
Nov. 15, 2022, 4:31 a.m. UTC
PATCH v1: <https://sourceware.org/pipermail/binutils/2022-July/121691.html> PATCH v2: <https://sourceware.org/pipermail/binutils/2022-October/123707.html> Only change between v2 and v3 is a rebase to resolve conflict with commit a8d181c0fdae ("RISC-V: xtheadfmemidx: Use fp register in mnemonics"). So, this is pretty much unchanged from v2. As a reminder, this e-mail is followed by the same cover letter as v2. ============= Hello, This patchset contains various tidying of RISC-V opcodes that would... (a) Make coding style more consistent and/or more readable (b) Remove unused constants (c) Make new instruction names primary (clean old names except aliases) (d) Make opcode entries functionally consistent. I call this "batch 1" and deals with the most obvious (yet small and various) issues. [Overview of this Patchset] PATCH 1/8: (a) Tidying (add space at the tail of pinfo) PATCH 2/8: (a) Tidying (fix obvious misalignments on 'Zbb'/'Zba') PATCH 3/8: (a) Tidying (remove spaces around "|" operator) PATCH 4/8: (b) Remove unused instruction macros PATCH 5/8: (c) SCALL -> ECALL, SBREAK -> EBREAK (RISC-V ISA v2.1) PATCH 6/8: (c) FMV.S.X -> FMV.W.X, FMV.X.S -> FMV.X.W (RISC-V ISA v2.2) PATCH 7/8: (c) Make old instruction names aliases PATCH 8/8: (d) Use defined (and named) constants for instruction defining Thanks, Tsukasa Tsukasa OI (8): RISC-V: Add a space at the end of pinfo RISC-V: Fix obvious misalignments ('Zbb'/'Zba') RISC-V: Remove spaces in opcode entries RISC-V: Remove unused instruction macros RISC-V: Complete tidying up with SCALL and SBREAK RISC-V: Tidying up with fmv.w.x and fmv.x.w RISC-V: Make alias instructions aliases RISC-V: Use defined mask and match values include/opcode/riscv-opc.h | 47 +-- opcodes/riscv-opc.c | 706 ++++++++++++++++++------------------- 2 files changed, 359 insertions(+), 394 deletions(-) base-commit: 8148339a741b37df6df3c4b3c4a7b9e812a79be7