mbox series

[v3,0/2] RISC-V: Improve "bits undefined" diagnostics

Message ID cover.1665050099.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Improve "bits undefined" diagnostics |

Message

Tsukasa OI Oct. 6, 2022, 9:56 a.m. UTC 
  Hello,

This small patch intends to improve one of the internal diagnostic messages
when an invalid RISC-V instruction is defined in riscv-opc.c.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_gas_diag_unused_bits>

It was a very low-priority patch but since commit bb996692bd9 "RISC-V/gas:
allow generating up to 176-bit instructions with .insn" can break
validate_riscv_insn function (by negative shift width), it'a good chance to
improve this function entirely.


[Changes: v2 -> v3]

-   PATCH 1/2: Revised the function description to reflect
    the specification.
-   PATCH 2/2: Started using "%#llx" instead of "0x%llx".
    In this occurrence, it will not change the behavior.

Both changes are based on the feedback from Jan Beulich.



This is mostly a quote from the cover letter of PATCH v1 but the words
"PATCH 1/2" are replaced with "PATCH 2/2" to reflect PATCH v2 and v3.


> First -- just to experiment -- we change mask value of "fcvt.d.s"
> instruction from MASK_FCVT_D_S|MASK_RM to MASK_FCVT_D_S while not touching
> operands "D,S" and we run compiled assembler, we get following message:
>
>     Assembler messages:
>     Error: internal: bad RISC-V opcode (bits 0xffffffff00007000 undefined): fcvt.d.s D,S
>     Fatal error: internal: broken assembler.  No assembly attempted
>
> Bits 0x7000 corresponds to rm (rounding mode) bits we just removed and no
> corresponding operands are found (making definition of fcvt.d.s instruction
> invalid).
>
> Then, what about 0xffffffff00000000 (upper 32-bits)?
> Yes, they are non-instruction bits.  Because of ~ (bitwise complement)
> operator while computing undefined bits, it also displays non-instruction
> bits.
>
>
> This patchset (PATCH 2/2) changes how undefined/invalid bits are computed.
>
> before:
>     ~(used & required)
> after:
>     (used ^ required)
>
> After PATCH 2/2, following error message is generated.
>
>     Assembler messages:
>     Error: internal: bad RISC-V opcode (bits 0x7000 undefined or invalid): fcvt.d.s D,S
>     Fatal error: internal: broken assembler.  No assembly attempted
>
>
> Note that we are testing for "undefined or invalid" bits here, not just
> undefined bits.  In fact, if we corrupt a variant of c.addi instruction with
> ADDITIONAL "j" operand (which is an immediate for I-type instruction, upper
> 12-bits of **32-bit** instruction encoding), we get following message:
>
>     Assembler messages:
>     Error: internal: bad RISC-V opcode (bits 0xfff00000 undefined or invalid): addi d,CU,Cj,j
>     Fatal error: internal: broken assembler.  No assembly attempted
>
> Okay, extra "j" operand generates "extra" bits (that should not have been
> defined considering its 16-bit encoding) and words "undefined or invalid"
> are working here.  We are correctly capturing invalid extra bits.  Before
> this patch, invalid bits are hidden by 0xffffffffffff0000 (48 non-
> instruction bits).


Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Fallback for instructions longer than 64b
  RISC-V: Improve "bits undefined" diagnostics

 gas/config/tc-riscv.c | 17 ++++++++++-------
 1 file changed, 10 insertions(+), 7 deletions(-)


base-commit: 80e0c6dc91f52fad32c3ff3cf20da889d77013ac