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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id m19-20020a50ef13000000b00459e2868155si581273eds.568.2022.10.05.21.40.42 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Oct 2022 21:40:42 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=Zjy0i5Xi; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 408BF384D15E for <ouuuleilei@gmail.com>; Thu, 6 Oct 2022 04:40:41 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 408BF384D15E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1665031241; bh=V23J/tjMTshsdUh5OUV6jN7QAXViiD/3yPdRLaTl0s4=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To:Cc: From; b=Zjy0i5Xi8C83m8efTATeE2/+vHyA9OWOLIj85fI2SWz+bWdKri9L9ytVxAYt9inhf LpxZWGznBe55r8wt1RqSpNxwxuPtvboiZYfCGVCSCPNHufi3fSA8czz8IGKUSvUl5o X5V8cFNu/aNvpAs6PSzfaX1L5BYd8HIs4Lt4siS4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id A9A873853835 for <binutils@sourceware.org>; Thu, 6 Oct 2022 04:40:26 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A9A873853835 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id C13EA300089; Thu, 6 Oct 2022 04:40:23 +0000 (UTC) To: Tsukasa OI <research_trasio@irq.a4lg.com>, Nelson Chu <nelson@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com> Subject: [PATCH v2 0/2] RISC-V: Improve "bits undefined" diagnostics Date: Thu, 6 Oct 2022 04:40:14 +0000 Message-Id: <cover.1665031170.git.research_trasio@irq.a4lg.com> In-Reply-To: <cover.1657338656.git.research_trasio@irq.a4lg.com> References: <cover.1657338656.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list <binutils.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/binutils>, <mailto:binutils-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/binutils/> List-Post: <mailto:binutils@sourceware.org> List-Help: <mailto:binutils-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/binutils>, <mailto:binutils-request@sourceware.org?subject=subscribe> From: Tsukasa OI via Binutils <binutils@sourceware.org> Reply-To: Tsukasa OI <research_trasio@irq.a4lg.com> Cc: binutils@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" <binutils-bounces+ouuuleilei=gmail.com@sourceware.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745911799964221706?= X-GMAIL-MSGID: =?utf-8?q?1745911799964221706?= |
Series |
RISC-V: Improve "bits undefined" diagnostics
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Message
Tsukasa OI
Oct. 6, 2022, 4:40 a.m. UTC
Hello, This small patch intends to improve one of the internal diagnostic messages when an invalid RISC-V instruction is defined in riscv-opc.c. Tracker on GitHub: <https://github.com/a4lg/binutils-gdb/wiki/riscv_gas_diag_unused_bits> It was a very low-priority patch but since commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit instructions with .insn" can break validate_riscv_insn function (by negative shift width), it'a good chance to improve this function entirely. This is mostly a quote from the cover letter of PATCH v1 but the words "PATCH 1/2" are replaced with "PATCH 2/2" to reflect PATCH v2. > First -- just to experiment -- we change mask value of "fcvt.d.s" > instruction from MASK_FCVT_D_S|MASK_RM to MASK_FCVT_D_S while not touching > operands "D,S" and we run compiled assembler, we get following message: > > Assembler messages: > Error: internal: bad RISC-V opcode (bits 0xffffffff00007000 undefined): fcvt.d.s D,S > Fatal error: internal: broken assembler. No assembly attempted > > Bits 0x7000 corresponds to rm (rounding mode) bits we just removed and no > corresponding operands are found (making definition of fcvt.d.s instruction > invalid). > > Then, what about 0xffffffff00000000 (upper 32-bits)? > Yes, they are non-instruction bits. Because of ~ (bitwise complement) > operator while computing undefined bits, it also displays non-instruction > bits. > > > This patchset (PATCH 2/2) changes how undefined/invalid bits are computed. > > before: > ~(used & required) > after: > (used ^ required) > > After PATCH 2/2, following error message is generated. > > Assembler messages: > Error: internal: bad RISC-V opcode (bits 0x7000 undefined or invalid): fcvt.d.s D,S > Fatal error: internal: broken assembler. No assembly attempted > > > Note that we are testing for "undefined or invalid" bits here, not just > undefined bits. In fact, if we corrupt a variant of c.addi instruction with > ADDITIONAL "j" operand (which is an immediate for I-type instruction, upper > 12-bits of **32-bit** instruction encoding), we get following message: > > Assembler messages: > Error: internal: bad RISC-V opcode (bits 0xfff00000 undefined or invalid): addi d,CU,Cj,j > Fatal error: internal: broken assembler. No assembly attempted > > Okay, extra "j" operand generates "extra" bits (that should not have been > defined considering its 16-bit encoding) and words "undefined or invalid" > are working here. We are correctly capturing invalid extra bits. Before > this patch, invalid bits are hidden by 0xffffffffffff0000 (48 non- > instruction bits). Thanks, Tsukasa Tsukasa OI (2): RISC-V: Fallback for instructions longer than 64b RISC-V: Improve "bits undefined" diagnostics gas/config/tc-riscv.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) base-commit: a13886e2198beb78b81c59839043b021ce6df78a