mbox series

[v2,0/2] RISC-V: Fix buffer overflow after 176-bit instruction support

Message ID cover.1664876744.git.research_trasio@irq.a4lg.com
Headers
Series RISC-V: Fix buffer overflow after 176-bit instruction support |

Message

Tsukasa OI Oct. 4, 2022, 9:45 a.m. UTC 
  Hello,

After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit
instructions with .insn", I started to see some crashes while running
"make check-gas".

The cause was simple.  Some functions depended on the fact that maximum
length returned by riscv_insn_length is 8.  But since the commit above
increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes),
we need to increase two buffer sizes to avoid crashes.

But note that this change doesn't really support over 64-bit instructions.
At least we can safely ignore those long instructions but we must remember
that we are still in a partial support for 176-bit instructions.

[Changes: v1 -> v2]
-   Fix assertion failure on riscv_insn::decode
-   Use new constant RISCV_MAX_INSN_LEN for buffer size

PATCH 1: Binutils
PATCH 2: GDB (v2: depends on PATCH 1)

Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Fix buffer overflow on print_insn_riscv
  gdb/riscv: Partial support for instructions up to 176-bits

 gdb/riscv-tdep.c       | 9 +++++----
 include/opcode/riscv.h | 2 ++
 opcodes/riscv-dis.c    | 2 +-
 3 files changed, 8 insertions(+), 5 deletions(-)


base-commit: 034235cebd790d4f9a1728043a175d7d7d9338b1