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[8.43.85.97]) by mx.google.com with ESMTPS id ev13-20020a056402540d00b00458ef3ccd2asi4815269edb.299.2022.10.04.01.59.33 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Oct 2022 01:59:33 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=PxV7GNz8; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 770863858427 for <ouuuleilei@gmail.com>; Tue, 4 Oct 2022 08:59:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 770863858427 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1664873972; bh=7a9khYzESloqUwrTs6DUVdrJxTfZxefCXY+CSaeY0Qs=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=PxV7GNz88OthFqICqmGbyIxXJCXJNv/olXYowufv4skIXCsDf7rLs+Xo9y6a/jXeF GH0op6EhzTYVEVflIz/KLTEg+YBZQnfRPs6ZTmvSKeK+CuTWXI6O5DIu18VpOmbb18 pSem4jTqPGfGP7L5mBlNTuFxqcJqP42tqGRiym90= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id A4AE33858D1E; Tue, 4 Oct 2022 08:59:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A4AE33858D1E Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 2614C300089; Tue, 4 Oct 2022 08:59:21 +0000 (UTC) To: Tsukasa OI <research_trasio@irq.a4lg.com>, Nelson Chu <nelson@rivosinc.com>, Kito Cheng <kito.cheng@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Andrew Burgess <aburgess@redhat.com>, Jan Beulich <jbeulich@suse.com> Subject: [PATCH 0/2] RISC-V: Fix buffer overflow after long instruction support Date: Tue, 4 Oct 2022 08:59:06 +0000 Message-Id: <cover.1664873933.git.research_trasio@irq.a4lg.com> Mime-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, KAM_MANYTO, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list <binutils.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/binutils>, <mailto:binutils-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/binutils/> List-Post: <mailto:binutils@sourceware.org> List-Help: <mailto:binutils-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/binutils>, <mailto:binutils-request@sourceware.org?subject=subscribe> From: Tsukasa OI via Binutils <binutils@sourceware.org> Reply-To: Tsukasa OI <research_trasio@irq.a4lg.com> Cc: binutils@sourceware.org, gdb-patches@sourceware.org Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" <binutils-bounces+ouuuleilei=gmail.com@sourceware.org> X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1745746892274562979?= X-GMAIL-MSGID: =?utf-8?q?1745746892274562979?= |
Series |
RISC-V: Fix buffer overflow after long instruction support
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Message
Tsukasa OI
Oct. 4, 2022, 8:59 a.m. UTC
Hello, After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit instructions with .insn", I started to see some crashes while running "make check-gas". The cause was simple. Some functions depended on the fact that maximum length returned by riscv_insn_length is 8. But since the commit above increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes), we need to increase two buffer sizes to avoid crashes. But note that this change doesn't really support over 64-bit instructions. It can be said on riscv_insn::fetch_instruction because it now may return only a part of instruction. Instead of merging this, reverting that commit (for now) might be an option. PATCH 1: Binutils PATCH 2: GDB Thanks, Tsukasa Tsukasa OI (2): RISC-V: Fix buffer overflow on print_insn_riscv gdb/riscv: Fix buffer overflow on riscv_insn::fetch_instruction gdb/riscv-tdep.c | 2 +- opcodes/riscv-dis.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) base-commit: 034235cebd790d4f9a1728043a175d7d7d9338b1
Comments
On 04.10.2022 10:59, Tsukasa OI wrote: > After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit > instructions with .insn", I started to see some crashes while running > "make check-gas". Hmm, I'm puzzled why things worked correctly for me. The extra size needed is quite significant, so chances should be rather slim for things to work correctly. > The cause was simple. Some functions depended on the fact that maximum > length returned by riscv_insn_length is 8. But since the commit above > increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes), > we need to increase two buffer sizes to avoid crashes. > > But note that this change doesn't really support over 64-bit instructions. > It can be said on riscv_insn::fetch_instruction because it now may return > only a part of instruction. > Instead of merging this, reverting that commit (for now) might be an option. Please let's try to avoid reverting - the ability to emit wide instructions via .insn helps testsuites beyond binutils' / gas'es. In any event - thanks for the quick fixing of the issue. I wonder though whether a connection (at least by way of comments) should be established so that the same oversight won't happen again (e.g. once the spec spells out how even wider insns would be encoded). Jan
Jan, On 2022/10/04 18:07, Jan Beulich wrote: > On 04.10.2022 10:59, Tsukasa OI wrote: >> After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit >> instructions with .insn", I started to see some crashes while running >> "make check-gas". > > Hmm, I'm puzzled why things worked correctly for me. The extra size needed > is quite significant, so chances should be rather slim for things to work > correctly. I don't see this extra stack size as a problem so far. > >> The cause was simple. Some functions depended on the fact that maximum >> length returned by riscv_insn_length is 8. But since the commit above >> increased that upper limit from 64-bits (8 bytes) to 176-bits (22 bytes), >> we need to increase two buffer sizes to avoid crashes. >> >> But note that this change doesn't really support over 64-bit instructions. >> It can be said on riscv_insn::fetch_instruction because it now may return >> only a part of instruction. >> Instead of merging this, reverting that commit (for now) might be an option. > > Please let's try to avoid reverting - the ability to emit wide instructions > via .insn helps testsuites beyond binutils' / gas'es. I normally agree with you but the real problem is, most of the RISC-V code is not yet ready for >64b instructions. At least it breaks GDB (even with my PATCH v1). I increased the buffer size in riscv_insn::fetch_instruction but riscv_insn::decode (the caller of fetch_instruction) causes an assertion failure. > else > { > /* This must be a 6 or 8 byte instruction, we don't currently decode > any of these, so just ignore it. */ > gdb_assert (m_length == 6 || m_length == 8); > m_opcode = OTHER; > } So, I'll at least submit PATCH v2 based on your and Andreas' feedback to patch minimally required portions but I will keep reverting as an option. With next PATCH v2, at least Binutils and GDB will be "functional" again (so that reverting will be not that urgent). Thanks, Tsukasa > > In any event - thanks for the quick fixing of the issue. I wonder though > whether a connection (at least by way of comments) should be established so > that the same oversight won't happen again (e.g. once the spec spells out > how even wider insns would be encoded). > > Jan >
On 04.10.2022 11:26, Tsukasa OI wrote: > On 2022/10/04 18:07, Jan Beulich wrote: >> On 04.10.2022 10:59, Tsukasa OI wrote: >>> After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit >>> instructions with .insn", I started to see some crashes while running >>> "make check-gas". >> >> Hmm, I'm puzzled why things worked correctly for me. The extra size needed >> is quite significant, so chances should be rather slim for things to work >> correctly. > > I don't see this extra stack size as a problem so far. I guess my wording was misleading: I would have expected things for me to be broken as well, simply because the amount of overrun would have clobbered multiple stack slots (the more that some of my testing was on a 32-bit host). Jan
On 2022/10/04 18:44, Jan Beulich wrote: > On 04.10.2022 11:26, Tsukasa OI wrote: >> On 2022/10/04 18:07, Jan Beulich wrote: >>> On 04.10.2022 10:59, Tsukasa OI wrote: >>>> After commit bb996692bd9 "RISC-V/gas: allow generating up to 176-bit >>>> instructions with .insn", I started to see some crashes while running >>>> "make check-gas". >>> >>> Hmm, I'm puzzled why things worked correctly for me. The extra size needed >>> is quite significant, so chances should be rather slim for things to work >>> correctly. >> >> I don't see this extra stack size as a problem so far. > > I guess my wording was misleading: I would have expected things for me to > be broken as well, simply because the amount of overrun would have > clobbered multiple stack slots (the more that some of my testing was on a > 32-bit host). Ah, that would make sense. Thanks, Tsukasa > > Jan >