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bh=JDUfVKv7soBctd/L6s6QHrkRuhh9Ra735LrCGwd4Tb8=; b=rm/jeCIgukU78QyyaFbifKOjH4hHU4oyq+XHuMHZkewGzR+WCjatt/nbitNdFHuisM wACZaJ50yQnWRL7BUaDY7SyLfofShl2US1yyNeTiZCrq6XhymPHu+5kSSp+Y1h7q1dj/ VTxvWxNLI0EK0KCea5LpAe8b9zbMbUDJehPYghDLH1dZuYILFHkfJEDofd24ZYkAPikX cBic6zem2MBxGfSQnGVVq6sk/MY2xbdtMRFESDq6Y3hAkjkz+bf6gS79HJAcx3OtIw1r 5Z0frv6UG4kaC7AJnU3lQLYeO8hzyfkpaXAjafzhZsYCj7VRD/T2FCmzmMkrmEgLm93g kIrw== X-Gm-Message-State: AOJu0YxgHPOa5QWc4KBDkMFdN3ZuGWsYww1kuw2B+5GEjUvUGJZ+aHIt Y+rn51eNBP9yv+eHx8qnlLAlF/h3FlUe4TOSeul3EsViyF8= X-Received: by 2002:a05:600c:548b:b0:40d:5cea:7186 with SMTP id iv11-20020a05600c548b00b0040d5cea7186mr1285427wmb.131.1704720287268; Mon, 08 Jan 2024 05:24:47 -0800 (PST) Received: from troughton.lym.embecosm-corp.com ([212.69.42.53]) by smtp.gmail.com with ESMTPSA id p7-20020a05600c358700b0040d3db8186fsm11175208wmq.5.2024.01.08.05.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 Jan 2024 05:24:46 -0800 (PST) From: Mary Bennett To: binutils@sourceware.org Cc: mary.bennett@embecosm.com Subject: [PATCH v3 0/3] RISC-V: Support CORE-V XCVELW, XCVBI, and XCVMEM extensions Date: Mon, 8 Jan 2024 13:24:29 +0000 Message-Id: <20240108132432.901738-1-mary.bennett@embecosm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231211114500.3695548-1-mary.bennett@embecosm.com> References: <20231211114500.3695548-1-mary.bennett@embecosm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-5.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784985814294202290 X-GMAIL-MSGID: 1787528846544062323 Thank you for reviewing this patch. I do not have merge permissions. If all looks good, please merge on my behalf. This patch series presents the comprehensive implementation of the ELW, BI, and MEM extension for CORE-V. Tested with riscv-gnu-toolchain on binutils, ld, gas and gcc testsuites to ensure its correctness and compatibility with the existing codebase. However, your input, reviews, and suggestions are invaluable in making this extension even more robust. The CORE-V instructions are described in the specification [1] and work can be found in the OpenHW group's Github repository [2]. [1] docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html [2] github.com/openhwgroup/corev-binutils-gdb Contributors: Mary Bennett Nandni Jamnadas Pietra Ferreira Charlie Keaney Jessica Mills Craig Blackmore Simon Cook Jeremy Bennett Helene Chelin Nazareno Bruschi Lin Sinan RISC-V: Add support for XCVmem extension in CV32E40P RISC-V: Add support for XCVelw extension in CV32E40P RISC-V: Add support for XCVbi extension in CV32E40P bfd/elfxx-riscv.c | 15 ++++++ gas/config/tc-riscv.c | 12 ++++- gas/doc/c-riscv.texi | 15 ++++++ gas/testsuite/gas/riscv/cv-bi-beqimm.d | 12 +++++ gas/testsuite/gas/riscv/cv-bi-beqimm.s | 4 ++ gas/testsuite/gas/riscv/cv-bi-bneimm.d | 12 +++++ gas/testsuite/gas/riscv/cv-bi-bneimm.s | 4 ++ gas/testsuite/gas/riscv/cv-bi-fail-march.d | 3 ++ gas/testsuite/gas/riscv/cv-bi-fail-march.l | 3 ++ gas/testsuite/gas/riscv/cv-bi-fail-march.s | 5 ++ .../gas/riscv/cv-bi-fail-operand-01.d | 3 ++ .../gas/riscv/cv-bi-fail-operand-01.l | 3 ++ .../gas/riscv/cv-bi-fail-operand-01.s | 4 ++ .../gas/riscv/cv-bi-fail-operand-02.d | 3 ++ .../gas/riscv/cv-bi-fail-operand-02.l | 3 ++ .../gas/riscv/cv-bi-fail-operand-02.s | 4 ++ .../gas/riscv/cv-bi-fail-operand-03.d | 3 ++ .../gas/riscv/cv-bi-fail-operand-03.l | 9 ++++ .../gas/riscv/cv-bi-fail-operand-03.s | 10 ++++ gas/testsuite/gas/riscv/cv-elw-fail-march.d | 3 ++ gas/testsuite/gas/riscv/cv-elw-fail-march.l | 38 +++++++++++++++ gas/testsuite/gas/riscv/cv-elw-fail-march.s | 42 +++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-fail.d | 3 ++ gas/testsuite/gas/riscv/cv-elw-fail.l | 5 ++ gas/testsuite/gas/riscv/cv-elw-fail.s | 8 ++++ gas/testsuite/gas/riscv/cv-elw-pass.d | 46 +++++++++++++++++++ gas/testsuite/gas/riscv/cv-elw-pass.s | 42 +++++++++++++++++ gas/testsuite/gas/riscv/cv-mem-fail-march.d | 3 ++ gas/testsuite/gas/riscv/cv-mem-fail-march.l | 25 ++++++++++ gas/testsuite/gas/riscv/cv-mem-fail-march.s | 26 +++++++++++ .../gas/riscv/cv-mem-fail-operand-01.d | 3 ++ .../gas/riscv/cv-mem-fail-operand-01.l | 21 +++++++++ .../gas/riscv/cv-mem-fail-operand-01.s | 22 +++++++++ .../gas/riscv/cv-mem-fail-operand-02.d | 3 ++ .../gas/riscv/cv-mem-fail-operand-02.l | 13 ++++++ .../gas/riscv/cv-mem-fail-operand-02.s | 14 ++++++ .../gas/riscv/cv-mem-fail-operand-03.d | 3 ++ .../gas/riscv/cv-mem-fail-operand-03.l | 33 +++++++++++++ .../gas/riscv/cv-mem-fail-operand-03.s | 34 ++++++++++++++ .../gas/riscv/cv-mem-fail-operand-04.d | 3 ++ .../gas/riscv/cv-mem-fail-operand-04.l | 41 +++++++++++++++++ .../gas/riscv/cv-mem-fail-operand-04.s | 42 +++++++++++++++++ .../gas/riscv/cv-mem-fail-operand-05.d | 3 ++ .../gas/riscv/cv-mem-fail-operand-05.l | 25 ++++++++++ .../gas/riscv/cv-mem-fail-operand-05.s | 26 +++++++++++ gas/testsuite/gas/riscv/cv-mem-lbpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lbpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lbrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lbrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lbrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lbrrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lbupost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lbupost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lburr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lburr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lburrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lburrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhrrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhupost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhupost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhurr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhurr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lhurrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lhurrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lwpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lwpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lwrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lwrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-lwrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-lwrrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-sbpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-sbpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-sbrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-sbrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-sbrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-sbrrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-shpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-shpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-shrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-shrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-shrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-shrrpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-swpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-swpost.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-swrr.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-swrr.s | 4 ++ gas/testsuite/gas/riscv/cv-mem-swrrpost.d | 12 +++++ gas/testsuite/gas/riscv/cv-mem-swrrpost.s | 4 ++ include/opcode/riscv-opc.h | 39 ++++++++++++++++ include/opcode/riscv.h | 6 +++ ld/testsuite/ld-riscv-elf/cv-bi-beqimm.d | 21 +++++++++ ld/testsuite/ld-riscv-elf/cv-bi-beqimm.s | 11 +++++ ld/testsuite/ld-riscv-elf/cv-bi-bneimm.d | 21 +++++++++ ld/testsuite/ld-riscv-elf/cv-bi-bneimm.s | 11 +++++ ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp | 2 + opcodes/riscv-dis.c | 4 ++ opcodes/riscv-opc.c | 33 +++++++++++++ 102 files changed, 1185 insertions(+), 1 deletion(-) create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-beqimm.s create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-bneimm.s create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.l create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-march.s create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l create mode 100644 gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.l create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail-march.s create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.d create mode 100644 gas/testsuite/gas/riscv/cv-elw-fail.l create mode 100644 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