Message ID | 20230919125633.491660-1-lili.cui@intel.com |
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Headers |
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[8.43.85.97]) by mx.google.com with ESMTPS id u17-20020a17090657d100b00997ba1c6f3dsi10816891ejr.403.2023.09.19.05.56.56 for <ouuuleilei@gmail.com> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Sep 2023 05:56:56 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=M2qMaFN+; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A82D93856DC7 for <ouuuleilei@gmail.com>; Tue, 19 Sep 2023 12:56:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A82D93856DC7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1695128207; bh=hjFvTe+njVbbE5nXOAHHv1MzSs0YGdpgi3i55WjaOfQ=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=M2qMaFN+D6hrNmrhoiJNvVQ1MyLpN9TjBjZlMOu40jX3FJE2XLFrKOF3tSzU6OOIH v0MfYCUV+6Vh0g8ArzyThzkGi6+y4mG592S4Iw/3TXb6azpG2u3gBZA/MK8wNsUHud Zr4tx2sTSqCKqgqiBQzPV9IgJaQIZNEPAE1PVhiA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id 5DC4A3856DFE for <binutils@sourceware.org>; Tue, 19 Sep 2023 12:56:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5DC4A3856DFE X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="444017709" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="444017709" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2023 05:56:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10838"; a="869960956" X-IronPort-AV: E=Sophos;i="6.02,159,1688454000"; d="scan'208";a="869960956" Received: from scymds04.sc.intel.com ([10.82.73.238]) by orsmga004.jf.intel.com with ESMTP; 19 Sep 2023 05:56:36 -0700 Received: from shgcc101.sh.intel.com (shgcc101.sh.intel.com [10.239.85.97]) by scymds04.sc.intel.com (Postfix) with ESMTP id EC01318007DF; Tue, 19 Sep 2023 05:56:34 -0700 (PDT) To: binutils@sourceware.org Cc: jbeulich@suse.com, hongjiu.lu@intel.com Subject: [PATCH 0/7] [RFC] Support Intel APX EGPR Date: Tue, 19 Sep 2023 12:56:26 +0000 Message-Id: <20230919125633.491660-1-lili.cui@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-5.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list <binutils.sourceware.org> List-Unsubscribe: <https://sourceware.org/mailman/options/binutils>, <mailto:binutils-request@sourceware.org?subject=unsubscribe> List-Archive: <https://sourceware.org/pipermail/binutils/> List-Post: <mailto:binutils@sourceware.org> List-Help: <mailto:binutils-request@sourceware.org?subject=help> List-Subscribe: <https://sourceware.org/mailman/listinfo/binutils>, <mailto:binutils-request@sourceware.org?subject=subscribe> From: "Cui, Lili via Binutils" <binutils@sourceware.org> Reply-To: "Cui, Lili" <lili.cui@intel.com> Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" <binutils-bounces+ouuuleilei=gmail.com@sourceware.org> X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777470765121737059 X-GMAIL-MSGID: 1777470765121737059 |
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Support Intel APX EGPR
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Message
Frager, Neal via Binutils
Sept. 19, 2023, 12:56 p.m. UTC
Intel Advanced performance extension (APX) has been released in https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html. It contains several extensions such as 1. Support APX GPR32 with rex2 prefix (For MAP0 an MAP1 legacy instructions). 2. Support APX GPR32 with extend evex prefix(legacy, VEX and EVEX extend to EVEX prefix to support GPR32). 3. Support APX NDD (non-destructive destination) and it's optimized encoding. 4. Support APX Push2/Pop2 5. Support APX NF 6. Support APX JMPABS 7. Linker support for APX encoded instructions. 8. Support APX ZU 9. Support APX CCMP and CTEST Here is an introduction to the implementation of the first two patches in Binutils 1. APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. Only adding the No_egpr flag to the instructions (legacy map0/map1) don't support EGPR (unsupported instructions are less). For map2/map3(legacy), VEX and EVEX, we use gi386-gen.c to add No_egpr. 2. we created new entries in i386-opc.tbl for instructions promoted from the legacy space and VEX. The extended EVEX prefix is based on the current 4-byte EVEX prefix with the semantics of several payload bits re-defined. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. To do list: 1. For REX2, All opcodes listed map0 0x4*/0x7*/0xa* and map0 0x3*/0x8* are reserved under REX2 and triggers #UD when prefixed with REX2. It should be belong to first rex2 patch, I will creat another patch to add it. 2. Support APX ZU -- In progress 3. Support APX CCMP and CTEST -- In progress 4. We haven’t disabled EGPR for 3DNOW instructions. We can disable them if AMD guys requires. This RFC focused on EGPR implementation in binutils. It may still have potential issues or bugs and requires futher optimization. Any comments are very appreciated. Cui, Lili (1): Support APX NF Hu, Lin1 (2): Support APX NDD optimized encoding. Support APX JMPABS Mo, Zewei (1): Support APX Push2/Pop2 konglin1 (3): Support APX GPR32 with rex2 prefix Support APX GPR32 with extend evex prefix Support APX NDD gas/NEWS | 3 + gas/config/tc-i386.c | 455 +- gas/doc/c-i386.texi | 3 +- gas/testsuite/gas/i386/apx-jmpabs-inval.l | 3 + gas/testsuite/gas/i386/apx-jmpabs-inval.s | 6 + gas/testsuite/gas/i386/apx-mov-inval.l | 2 + gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 + gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 + gas/testsuite/gas/i386/i386.exp | 2 + .../i386/ilp32/x86-64-opcode-inval-intel.d | 4 +- .../gas/i386/ilp32/x86-64-opcode-inval.d | 4 +- .../gas/i386/x86-64-apx-egpr-inval.l | 212 + .../gas/i386/x86-64-apx-egpr-inval.s | 210 + .../gas/i386/x86-64-apx-egpr-promote-inval.l | 17 + .../gas/i386/x86-64-apx-egpr-promote-inval.s | 18 + gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d | 22 + gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s | 25 + .../gas/i386/x86-64-apx-evex-promoted-intel.d | 740 + .../gas/i386/x86-64-apx-evex-promoted.d | 740 + .../gas/i386/x86-64-apx-evex-promoted.s | 1464 ++ .../gas/i386/x86-64-apx-jmpabs-intel.d | 14 + .../gas/i386/x86-64-apx-jmpabs-inval.d | 55 + .../gas/i386/x86-64-apx-jmpabs-inval.s | 18 + gas/testsuite/gas/i386/x86-64-apx-jmpabs.d | 14 + gas/testsuite/gas/i386/x86-64-apx-jmpabs.s | 10 + gas/testsuite/gas/i386/x86-64-apx-mov-inval.l | 2 + gas/testsuite/gas/i386/x86-64-apx-mov-inval.s | 5 + .../gas/i386/x86-64-apx-ndd-optimize.d | 120 + .../gas/i386/x86-64-apx-ndd-optimize.s | 115 + gas/testsuite/gas/i386/x86-64-apx-ndd.d | 165 + gas/testsuite/gas/i386/x86-64-apx-ndd.s | 156 + gas/testsuite/gas/i386/x86-64-apx-nf-intel.d | 633 + gas/testsuite/gas/i386/x86-64-apx-nf.d | 633 + gas/testsuite/gas/i386/x86-64-apx-nf.s | 1256 + .../i386/x86-64-apx-push2pop2-decode-inval.d | 29 + .../i386/x86-64-apx-push2pop2-decode-inval.s | 19 + .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 + .../gas/i386/x86-64-apx-push2pop2-inval.l | 9 + .../gas/i386/x86-64-apx-push2pop2-inval.s | 13 + gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 + gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 + .../gas/i386/x86-64-apx-rex2-inval.d | 29 + .../gas/i386/x86-64-apx-rex2-inval.s | 25 + gas/testsuite/gas/i386/x86-64-apx-rex2.d | 148 + gas/testsuite/gas/i386/x86-64-apx-rex2.s | 175 + gas/testsuite/gas/i386/x86-64-evex.d | 2 +- gas/testsuite/gas/i386/x86-64-inval-movbe.l | 31 +- gas/testsuite/gas/i386/x86-64-inval-movbe.s | 1 + gas/testsuite/gas/i386/x86-64-inval-pseudo.l | 12 + gas/testsuite/gas/i386/x86-64-inval-pseudo.s | 8 + .../gas/i386/x86-64-opcode-inval-intel.d | 4 +- gas/testsuite/gas/i386/x86-64-opcode-inval.d | 4 +- gas/testsuite/gas/i386/x86-64-pseudos.d | 62 + gas/testsuite/gas/i386/x86-64-pseudos.s | 64 + gas/testsuite/gas/i386/x86-64.exp | 19 + include/opcode/i386.h | 2 + opcodes/i386-dis-evex-len.h | 20 + opcodes/i386-dis-evex-mod.h | 60 + opcodes/i386-dis-evex-prefix.h | 91 + opcodes/i386-dis-evex-reg.h | 155 + opcodes/i386-dis-evex-w.h | 10 + opcodes/i386-dis-evex-x86.h | 150 + opcodes/i386-dis-evex.h | 638 +- opcodes/i386-dis.c | 437 +- opcodes/i386-gen.c | 14 + opcodes/i386-init.h | 514 +- opcodes/i386-mnem.h | 3921 +-- opcodes/i386-opc.h | 26 +- opcodes/i386-opc.tbl | 271 +- opcodes/i386-reg.tbl | 64 + opcodes/i386-tbl.h | 20205 +++++++++------- 71 files changed, 23477 insertions(+), 11018 deletions(-) create mode 100644 gas/testsuite/gas/i386/apx-jmpabs-inval.l create mode 100644 gas/testsuite/gas/i386/apx-jmpabs-inval.s create mode 100644 gas/testsuite/gas/i386/apx-mov-inval.l create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-egpr-promote-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-evex-promoted.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-jmpabs.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-mov-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-mov-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd-optimize.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-ndd.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-nf.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-decode-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-intel.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.l create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-push2pop2.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2-inval.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2-inval.s create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2.d create mode 100644 gas/testsuite/gas/i386/x86-64-apx-rex2.s create mode 100644 opcodes/i386-dis-evex-x86.h
Comments
On 19.09.2023 14:56, Cui, Lili wrote: > Intel Advanced performance extension (APX) has been released in > https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html. > It contains several extensions such as > 1. Support APX GPR32 with rex2 prefix (For MAP0 an MAP1 legacy instructions). > 2. Support APX GPR32 with extend evex prefix(legacy, VEX and EVEX extend to EVEX prefix to support GPR32). > 3. Support APX NDD (non-destructive destination) and it's optimized encoding. > 4. Support APX Push2/Pop2 > 5. Support APX NF > 6. Support APX JMPABS > 7. Linker support for APX encoded instructions. > 8. Support APX ZU > 9. Support APX CCMP and CTEST > > Here is an introduction to the implementation of the first two patches in Binutils > > 1. APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. Only adding the No_egpr flag to the instructions (legacy map0/map1) don't support EGPR (unsupported instructions are less). For map2/map3(legacy), VEX and EVEX, we use gi386-gen.c to add No_egpr. > > 2. we created new entries in i386-opc.tbl for instructions promoted from the legacy space and VEX. > The extended EVEX prefix is based on the current 4-byte EVEX prefix with the semantics of several payload bits re-defined. > EVEX extension of legacy instructions: > All promoted legacy instructions are placed in EVEX map 4, which is > currently reserved. > EVEX extension of EVEX instructions: > All existing EVEX instructions are extended by APX using the extended > EVEX prefix, so that they can access all 32 GPRs. > EVEX extension of VEX instructions: > Promoting a VEX instruction into the EVEX space does not change the map > id, the opcode, or the operand encoding of the VEX instruction. All such information belongs in the respective patches, as descriptions. ChangeLogs alone don't really help understanding _why_ certain things are done the way they are done, yet that information can be crucial when later some kind of issue needs sorting out (i.e. it needs to be in git, not just on a mailing list thread). > To do list: > 1. For REX2, All opcodes listed map0 0x4*/0x7*/0xa* and map0 0x3*/0x8* are reserved under REX2 and triggers #UD when prefixed with REX2. It should be belong to first rex2 patch, I will creat another patch to add it. > 2. Support APX ZU -- In progress > 3. Support APX CCMP and CTEST -- In progress > 4. We haven’t disabled EGPR for 3DNOW instructions. We can disable them if AMD guys requires. Nothing should allow use of the extended registers that isn't positively known to support them. > This RFC focused on EGPR implementation in binutils. It may still have potential issues or bugs and requires futher optimization. Any comments are very appreciated. > > > Cui, Lili (1): > Support APX NF > > Hu, Lin1 (2): > Support APX NDD optimized encoding. > Support APX JMPABS > > Mo, Zewei (1): > Support APX Push2/Pop2 > > konglin1 (3): > Support APX GPR32 with rex2 prefix > Support APX GPR32 with extend evex prefix > Support APX NDD > > gas/NEWS | 3 + With work not finished, this file shouldn't be updated just yet. > gas/config/tc-i386.c | 455 +- > gas/doc/c-i386.texi | 3 +- > gas/testsuite/gas/i386/apx-jmpabs-inval.l | 3 + > gas/testsuite/gas/i386/apx-jmpabs-inval.s | 6 + > gas/testsuite/gas/i386/apx-mov-inval.l | 2 + > gas/testsuite/gas/i386/apx-push2pop2-inval.l | 5 + > gas/testsuite/gas/i386/apx-push2pop2-inval.s | 9 + > gas/testsuite/gas/i386/i386.exp | 2 + > .../i386/ilp32/x86-64-opcode-inval-intel.d | 4 +- > .../gas/i386/ilp32/x86-64-opcode-inval.d | 4 +- > .../gas/i386/x86-64-apx-egpr-inval.l | 212 + > .../gas/i386/x86-64-apx-egpr-inval.s | 210 + > .../gas/i386/x86-64-apx-egpr-promote-inval.l | 17 + > .../gas/i386/x86-64-apx-egpr-promote-inval.s | 18 + > gas/testsuite/gas/i386/x86-64-apx-evex-egpr.d | 22 + > gas/testsuite/gas/i386/x86-64-apx-evex-egpr.s | 25 + > .../gas/i386/x86-64-apx-evex-promoted-intel.d | 740 + > .../gas/i386/x86-64-apx-evex-promoted.d | 740 + > .../gas/i386/x86-64-apx-evex-promoted.s | 1464 ++ > .../gas/i386/x86-64-apx-jmpabs-intel.d | 14 + > .../gas/i386/x86-64-apx-jmpabs-inval.d | 55 + > .../gas/i386/x86-64-apx-jmpabs-inval.s | 18 + > gas/testsuite/gas/i386/x86-64-apx-jmpabs.d | 14 + > gas/testsuite/gas/i386/x86-64-apx-jmpabs.s | 10 + > gas/testsuite/gas/i386/x86-64-apx-mov-inval.l | 2 + > gas/testsuite/gas/i386/x86-64-apx-mov-inval.s | 5 + > .../gas/i386/x86-64-apx-ndd-optimize.d | 120 + > .../gas/i386/x86-64-apx-ndd-optimize.s | 115 + > gas/testsuite/gas/i386/x86-64-apx-ndd.d | 165 + > gas/testsuite/gas/i386/x86-64-apx-ndd.s | 156 + > gas/testsuite/gas/i386/x86-64-apx-nf-intel.d | 633 + > gas/testsuite/gas/i386/x86-64-apx-nf.d | 633 + > gas/testsuite/gas/i386/x86-64-apx-nf.s | 1256 + > .../i386/x86-64-apx-push2pop2-decode-inval.d | 29 + > .../i386/x86-64-apx-push2pop2-decode-inval.s | 19 + > .../gas/i386/x86-64-apx-push2pop2-intel.d | 42 + > .../gas/i386/x86-64-apx-push2pop2-inval.l | 9 + > .../gas/i386/x86-64-apx-push2pop2-inval.s | 13 + > gas/testsuite/gas/i386/x86-64-apx-push2pop2.d | 42 + > gas/testsuite/gas/i386/x86-64-apx-push2pop2.s | 39 + > .../gas/i386/x86-64-apx-rex2-inval.d | 29 + > .../gas/i386/x86-64-apx-rex2-inval.s | 25 + > gas/testsuite/gas/i386/x86-64-apx-rex2.d | 148 + > gas/testsuite/gas/i386/x86-64-apx-rex2.s | 175 + > gas/testsuite/gas/i386/x86-64-evex.d | 2 +- > gas/testsuite/gas/i386/x86-64-inval-movbe.l | 31 +- > gas/testsuite/gas/i386/x86-64-inval-movbe.s | 1 + > gas/testsuite/gas/i386/x86-64-inval-pseudo.l | 12 + > gas/testsuite/gas/i386/x86-64-inval-pseudo.s | 8 + > .../gas/i386/x86-64-opcode-inval-intel.d | 4 +- > gas/testsuite/gas/i386/x86-64-opcode-inval.d | 4 +- > gas/testsuite/gas/i386/x86-64-pseudos.d | 62 + > gas/testsuite/gas/i386/x86-64-pseudos.s | 64 + > gas/testsuite/gas/i386/x86-64.exp | 19 + > include/opcode/i386.h | 2 + > opcodes/i386-dis-evex-len.h | 20 + > opcodes/i386-dis-evex-mod.h | 60 + > opcodes/i386-dis-evex-prefix.h | 91 + > opcodes/i386-dis-evex-reg.h | 155 + > opcodes/i386-dis-evex-w.h | 10 + > opcodes/i386-dis-evex-x86.h | 150 + > opcodes/i386-dis-evex.h | 638 +- > opcodes/i386-dis.c | 437 +- > opcodes/i386-gen.c | 14 + > opcodes/i386-init.h | 514 +- > opcodes/i386-mnem.h | 3921 +-- > opcodes/i386-opc.h | 26 +- > opcodes/i386-opc.tbl | 271 +- > opcodes/i386-reg.tbl | 64 + > opcodes/i386-tbl.h | 20205 +++++++++------- > 71 files changed, 23477 insertions(+), 11018 deletions(-) Please can you avoid sending out diff-s of generated files. Without that the patches are going to be quite a bit smaller and easier to handle. Jan