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To: binutils@sourceware.org
Cc: Richard Sandiford <richard.sandiford@arm.com>
Subject: [PATCH 00/31] aarch64: Add SME2 support
Date: Thu, 30 Mar 2023 11:26:15 +0100
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|
| Series |
aarch64: Add SME2 support
|
|
Message
Richard Sandiford
March 30, 2023, 10:26 a.m. UTC
This series of patches adds SME2 support to the AArch64 backend. Details on SME2 are available here: https://developer.arm.com/documentation/ddi0602/2022-12/SME-Instructions Tested on aarch64-linux-gnu, and via automatic cross-checking against the architecture description and the LLVM implementation. I've pushed the series under GWP, but I'm more than happy to update/adjust/fix based on post-commit review, so please let me know if you spot anything you think should be changed. Thanks, Richard Richard Sandiford (31): aarch64: Add +sme2 aarch64: Add a _10 suffix to FLD_imm3 aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array aarch64: Add support for vgx2 and vgx4 aarch64; Add support for vector offset ranges aarch64: Add support for predicate-as-counter registers aarch64: Add the SME2 MOVA instructions aarch64: Add the SME2 multivector LD1 and ST1 instructions aarch64: Add the SME2 predicate-related instructions aarch64: Add the SME2 ZT0 instructions aarch64: Add the SME2 ADD and SUB instructions aarch64: Add the SME2 maximum/minimum instructions aarch64: Add the SME2 FMLA and FMLS instructions aarch64: Add the SME2 MLAL and MLSL instructions aarch64: Add the SME2 MLALL and MLSLL instructions aarch64: Add the SME2 dot-product instructions aarch64: Add the SME2 vertical dot-product instructions aarch64: Add the SME2 MOPA and MOPS instructions aarch64: Add the SME2 CLAMP instructions aarch64: Add the SME2 FP<->int conversion instructions aarch64: Add the SME2 FP<->FP conversion instructions aarch64: Add the SME2 saturating conversion instructions aarch64: Add the SME2 shift instructions aarch64: Add the SME2 UNPK instructions aarch64: Add the SME2 UZP and ZIP instructions aarch64: Add the SVE BFMLSL instructions aarch64: Add new SVE dot-product instructions aarch64: Add new SVE saturating conversion instructions aarch64: Add new SVE shift instructions aarch64: Add the SVE FCLAMP instruction aarch64: Add the RPRFM instruction gas/NEWS | 2 + gas/config/tc-aarch64.c | 307 +- gas/doc/c-aarch64.texi | 2 + gas/testsuite/gas/aarch64/illegal-sve2.l | 28 +- gas/testsuite/gas/aarch64/legacy_reg_names.l | 2 +- gas/testsuite/gas/aarch64/rprfm-1-invalid.d | 3 + gas/testsuite/gas/aarch64/rprfm-1-invalid.l | 11 + gas/testsuite/gas/aarch64/rprfm-1-invalid.s | 9 + gas/testsuite/gas/aarch64/rprfm-1.d | 83 + gas/testsuite/gas/aarch64/rprfm-1.s | 74 + gas/testsuite/gas/aarch64/sme-2-illegal.l | 16 + gas/testsuite/gas/aarch64/sme-2-illegal.s | 11 + gas/testsuite/gas/aarch64/sme-3-illegal.l | 13 +- gas/testsuite/gas/aarch64/sme-3-illegal.s | 6 + gas/testsuite/gas/aarch64/sme-4-illegal.l | 6 +- gas/testsuite/gas/aarch64/sme-5-illegal.l | 10 + gas/testsuite/gas/aarch64/sme-5-illegal.s | 9 + gas/testsuite/gas/aarch64/sme-6-illegal.l | 10 + gas/testsuite/gas/aarch64/sme-6-illegal.s | 9 + gas/testsuite/gas/aarch64/sme-7-illegal.l | 20 + gas/testsuite/gas/aarch64/sme-7-illegal.s | 17 + gas/testsuite/gas/aarch64/sme-9-illegal.l | 19 + gas/testsuite/gas/aarch64/sme-9-illegal.s | 10 + gas/testsuite/gas/aarch64/sme-9.d | 4 +- gas/testsuite/gas/aarch64/sme2-1-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-1-invalid.l | 327 + gas/testsuite/gas/aarch64/sme2-1-invalid.s | 323 + gas/testsuite/gas/aarch64/sme2-1-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-1-noarch.l | 289 + gas/testsuite/gas/aarch64/sme2-1.d | 305 + gas/testsuite/gas/aarch64/sme2-1.s | 338 + gas/testsuite/gas/aarch64/sme2-10-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-10-invalid.l | 67 + gas/testsuite/gas/aarch64/sme2-10-invalid.s | 50 + gas/testsuite/gas/aarch64/sme2-10-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-10-noarch.l | 641 ++ gas/testsuite/gas/aarch64/sme2-10.d | 649 ++ gas/testsuite/gas/aarch64/sme2-10.s | 799 ++ gas/testsuite/gas/aarch64/sme2-11-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-11-invalid.l | 101 + gas/testsuite/gas/aarch64/sme2-11-invalid.s | 91 + gas/testsuite/gas/aarch64/sme2-11-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-11-noarch.l | 117 + gas/testsuite/gas/aarch64/sme2-11.d | 125 + gas/testsuite/gas/aarch64/sme2-11.s | 127 + gas/testsuite/gas/aarch64/sme2-12-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-12-invalid.l | 155 + gas/testsuite/gas/aarch64/sme2-12-invalid.s | 136 + gas/testsuite/gas/aarch64/sme2-12-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-12-noarch.l | 571 + gas/testsuite/gas/aarch64/sme2-12.d | 579 + gas/testsuite/gas/aarch64/sme2-12.s | 633 ++ gas/testsuite/gas/aarch64/sme2-13-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-13-invalid.l | 80 + gas/testsuite/gas/aarch64/sme2-13-invalid.s | 83 + gas/testsuite/gas/aarch64/sme2-13-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-13-noarch.l | 253 + gas/testsuite/gas/aarch64/sme2-13.d | 261 + gas/testsuite/gas/aarch64/sme2-13.s | 283 + gas/testsuite/gas/aarch64/sme2-14-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-14-invalid.l | 7 + gas/testsuite/gas/aarch64/sme2-14-invalid.s | 7 + gas/testsuite/gas/aarch64/sme2-14-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-14-noarch.l | 107 + gas/testsuite/gas/aarch64/sme2-14.d | 115 + gas/testsuite/gas/aarch64/sme2-14.s | 118 + gas/testsuite/gas/aarch64/sme2-15-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-15-invalid.l | 97 + gas/testsuite/gas/aarch64/sme2-15-invalid.s | 87 + gas/testsuite/gas/aarch64/sme2-15-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-15-noarch.l | 187 + gas/testsuite/gas/aarch64/sme2-15.d | 195 + gas/testsuite/gas/aarch64/sme2-15.s | 203 + gas/testsuite/gas/aarch64/sme2-16-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-16-invalid.l | 97 + gas/testsuite/gas/aarch64/sme2-16-invalid.s | 87 + gas/testsuite/gas/aarch64/sme2-16-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-16-noarch.l | 249 + gas/testsuite/gas/aarch64/sme2-16.d | 257 + gas/testsuite/gas/aarch64/sme2-16.s | 271 + gas/testsuite/gas/aarch64/sme2-17-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-17-invalid.l | 20 + gas/testsuite/gas/aarch64/sme2-17-invalid.s | 12 + gas/testsuite/gas/aarch64/sme2-17-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-17-noarch.l | 45 + gas/testsuite/gas/aarch64/sme2-17.d | 53 + gas/testsuite/gas/aarch64/sme2-17.s | 47 + gas/testsuite/gas/aarch64/sme2-18-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-18-invalid.l | 21 + gas/testsuite/gas/aarch64/sme2-18-invalid.s | 20 + gas/testsuite/gas/aarch64/sme2-18-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-18-noarch.l | 21 + gas/testsuite/gas/aarch64/sme2-18.d | 29 + gas/testsuite/gas/aarch64/sme2-18.s | 21 + gas/testsuite/gas/aarch64/sme2-19-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-19-invalid.l | 36 + gas/testsuite/gas/aarch64/sme2-19-invalid.s | 36 + gas/testsuite/gas/aarch64/sme2-19-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-19-noarch.l | 41 + gas/testsuite/gas/aarch64/sme2-19.d | 49 + gas/testsuite/gas/aarch64/sme2-19.s | 43 + gas/testsuite/gas/aarch64/sme2-2-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-2-invalid.l | 229 + gas/testsuite/gas/aarch64/sme2-2-invalid.s | 205 + gas/testsuite/gas/aarch64/sme2-2-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-2-noarch.l | 481 + gas/testsuite/gas/aarch64/sme2-2.d | 489 + gas/testsuite/gas/aarch64/sme2-2.s | 511 + gas/testsuite/gas/aarch64/sme2-20-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-20-invalid.l | 27 + gas/testsuite/gas/aarch64/sme2-20-invalid.s | 23 + gas/testsuite/gas/aarch64/sme2-20-noarch.d | 3 + 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gas/testsuite/gas/aarch64/sme2-23-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-23-noarch.l | 65 + gas/testsuite/gas/aarch64/sme2-23.d | 73 + gas/testsuite/gas/aarch64/sme2-23.s | 79 + gas/testsuite/gas/aarch64/sme2-24-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-24-invalid.l | 22 + gas/testsuite/gas/aarch64/sme2-24-invalid.s | 13 + gas/testsuite/gas/aarch64/sme2-24-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-24-noarch.l | 17 + gas/testsuite/gas/aarch64/sme2-24.d | 25 + gas/testsuite/gas/aarch64/sme2-24.s | 19 + gas/testsuite/gas/aarch64/sme2-25-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-25-invalid.l | 48 + gas/testsuite/gas/aarch64/sme2-25-invalid.s | 28 + gas/testsuite/gas/aarch64/sme2-25-noarch.d | 3 + gas/testsuite/gas/aarch64/sme2-25-noarch.l | 37 + gas/testsuite/gas/aarch64/sme2-25.d | 45 + gas/testsuite/gas/aarch64/sme2-25.s | 44 + gas/testsuite/gas/aarch64/sme2-26-invalid.d | 3 + gas/testsuite/gas/aarch64/sme2-26-invalid.l | 13 + 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Comments
On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: > Richard Sandiford (31): > aarch64: Add +sme2 > aarch64: Add a _10 suffix to FLD_imm3 > aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array > aarch64: Add support for vgx2 and vgx4 > aarch64; Add support for vector offset ranges > aarch64: Add support for predicate-as-counter registers > aarch64: Add the SME2 MOVA instructions > aarch64: Add the SME2 multivector LD1 and ST1 instructions Less than a 3rd of the patches in this series have made it to my mailbox (and the list archives), so commenting on e.g. the one above is difficult. Nevertheless - according to the documentation LD1x (scalar plus immediate, consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks as if the use of SME2_INSN() there is wrong, unless the documentation is categorizing these incorrectly). Jan
On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: > This series of patches adds SME2 support to the AArch64 backend. > Details on SME2 are available here: > > https://developer.arm.com/documentation/ddi0602/2022-12/SME-Instructions > > Tested on aarch64-linux-gnu, and via automatic cross-checking > against the architecture description and the LLVM implementation. > > I've pushed the series under GWP, but I'm more than happy > to update/adjust/fix based on post-commit review, so please > let me know if you spot anything you think should be changed. > > Thanks, > Richard > > > Richard Sandiford (31): > aarch64: Add +sme2 > aarch64: Add a _10 suffix to FLD_imm3 > aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array > aarch64: Add support for vgx2 and vgx4 > aarch64; Add support for vector offset ranges > aarch64: Add support for predicate-as-counter registers Shouldn't the (alias) insn forms added here all use SME2_INSN()? It doesn't seem to make sense to permit them with ".arch_extension sme". Jan > aarch64: Add the SME2 MOVA instructions > aarch64: Add the SME2 multivector LD1 and ST1 instructions > aarch64: Add the SME2 predicate-related instructions > aarch64: Add the SME2 ZT0 instructions > aarch64: Add the SME2 ADD and SUB instructions > aarch64: Add the SME2 maximum/minimum instructions > aarch64: Add the SME2 FMLA and FMLS instructions > aarch64: Add the SME2 MLAL and MLSL instructions > aarch64: Add the SME2 MLALL and MLSLL instructions > aarch64: Add the SME2 dot-product instructions > aarch64: Add the SME2 vertical dot-product instructions > aarch64: Add the SME2 MOPA and MOPS instructions > aarch64: Add the SME2 CLAMP instructions > aarch64: Add the SME2 FP<->int conversion instructions > aarch64: Add the SME2 FP<->FP conversion instructions > aarch64: Add the SME2 saturating conversion instructions > aarch64: Add the SME2 shift instructions > aarch64: Add the SME2 UNPK instructions > aarch64: Add the SME2 UZP and ZIP instructions > aarch64: Add the SVE BFMLSL instructions > aarch64: Add new SVE dot-product instructions > aarch64: Add new SVE saturating conversion instructions > aarch64: Add new SVE shift instructions > aarch64: Add the SVE FCLAMP instruction > aarch64: Add the RPRFM instruction > > gas/NEWS | 2 + > gas/config/tc-aarch64.c | 307 +- > gas/doc/c-aarch64.texi | 2 + > gas/testsuite/gas/aarch64/illegal-sve2.l | 28 +- > gas/testsuite/gas/aarch64/legacy_reg_names.l | 2 +- > gas/testsuite/gas/aarch64/rprfm-1-invalid.d | 3 + > gas/testsuite/gas/aarch64/rprfm-1-invalid.l | 11 + > gas/testsuite/gas/aarch64/rprfm-1-invalid.s | 9 + > gas/testsuite/gas/aarch64/rprfm-1.d | 83 + > gas/testsuite/gas/aarch64/rprfm-1.s | 74 + > gas/testsuite/gas/aarch64/sme-2-illegal.l | 16 + > gas/testsuite/gas/aarch64/sme-2-illegal.s | 11 + > gas/testsuite/gas/aarch64/sme-3-illegal.l | 13 +- > gas/testsuite/gas/aarch64/sme-3-illegal.s | 6 + > gas/testsuite/gas/aarch64/sme-4-illegal.l | 6 +- > gas/testsuite/gas/aarch64/sme-5-illegal.l | 10 + > gas/testsuite/gas/aarch64/sme-5-illegal.s | 9 + > gas/testsuite/gas/aarch64/sme-6-illegal.l | 10 + > gas/testsuite/gas/aarch64/sme-6-illegal.s | 9 + > gas/testsuite/gas/aarch64/sme-7-illegal.l | 20 + > gas/testsuite/gas/aarch64/sme-7-illegal.s | 17 + > gas/testsuite/gas/aarch64/sme-9-illegal.l | 19 + > gas/testsuite/gas/aarch64/sme-9-illegal.s | 10 + > gas/testsuite/gas/aarch64/sme-9.d | 4 +- > gas/testsuite/gas/aarch64/sme2-1-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-1-invalid.l | 327 + > gas/testsuite/gas/aarch64/sme2-1-invalid.s | 323 + > gas/testsuite/gas/aarch64/sme2-1-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-1-noarch.l | 289 + > gas/testsuite/gas/aarch64/sme2-1.d | 305 + > gas/testsuite/gas/aarch64/sme2-1.s | 338 + > gas/testsuite/gas/aarch64/sme2-10-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-10-invalid.l | 67 + > gas/testsuite/gas/aarch64/sme2-10-invalid.s | 50 + > gas/testsuite/gas/aarch64/sme2-10-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-10-noarch.l | 641 ++ > gas/testsuite/gas/aarch64/sme2-10.d | 649 ++ > gas/testsuite/gas/aarch64/sme2-10.s | 799 ++ > gas/testsuite/gas/aarch64/sme2-11-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-11-invalid.l | 101 + > gas/testsuite/gas/aarch64/sme2-11-invalid.s | 91 + > gas/testsuite/gas/aarch64/sme2-11-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-11-noarch.l | 117 + > gas/testsuite/gas/aarch64/sme2-11.d | 125 + > gas/testsuite/gas/aarch64/sme2-11.s | 127 + > gas/testsuite/gas/aarch64/sme2-12-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-12-invalid.l | 155 + > gas/testsuite/gas/aarch64/sme2-12-invalid.s | 136 + > gas/testsuite/gas/aarch64/sme2-12-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-12-noarch.l | 571 + > gas/testsuite/gas/aarch64/sme2-12.d | 579 + > gas/testsuite/gas/aarch64/sme2-12.s | 633 ++ > gas/testsuite/gas/aarch64/sme2-13-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-13-invalid.l | 80 + > gas/testsuite/gas/aarch64/sme2-13-invalid.s | 83 + > gas/testsuite/gas/aarch64/sme2-13-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-13-noarch.l | 253 + > gas/testsuite/gas/aarch64/sme2-13.d | 261 + > gas/testsuite/gas/aarch64/sme2-13.s | 283 + > gas/testsuite/gas/aarch64/sme2-14-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-14-invalid.l | 7 + > gas/testsuite/gas/aarch64/sme2-14-invalid.s | 7 + > gas/testsuite/gas/aarch64/sme2-14-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-14-noarch.l | 107 + > gas/testsuite/gas/aarch64/sme2-14.d | 115 + > gas/testsuite/gas/aarch64/sme2-14.s | 118 + > gas/testsuite/gas/aarch64/sme2-15-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-15-invalid.l | 97 + > gas/testsuite/gas/aarch64/sme2-15-invalid.s | 87 + > gas/testsuite/gas/aarch64/sme2-15-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-15-noarch.l | 187 + > gas/testsuite/gas/aarch64/sme2-15.d | 195 + > gas/testsuite/gas/aarch64/sme2-15.s | 203 + > gas/testsuite/gas/aarch64/sme2-16-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-16-invalid.l | 97 + > gas/testsuite/gas/aarch64/sme2-16-invalid.s | 87 + > gas/testsuite/gas/aarch64/sme2-16-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-16-noarch.l | 249 + > gas/testsuite/gas/aarch64/sme2-16.d | 257 + > gas/testsuite/gas/aarch64/sme2-16.s | 271 + > gas/testsuite/gas/aarch64/sme2-17-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-17-invalid.l | 20 + > gas/testsuite/gas/aarch64/sme2-17-invalid.s | 12 + > gas/testsuite/gas/aarch64/sme2-17-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-17-noarch.l | 45 + > gas/testsuite/gas/aarch64/sme2-17.d | 53 + > gas/testsuite/gas/aarch64/sme2-17.s | 47 + > gas/testsuite/gas/aarch64/sme2-18-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-18-invalid.l | 21 + > gas/testsuite/gas/aarch64/sme2-18-invalid.s | 20 + > gas/testsuite/gas/aarch64/sme2-18-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-18-noarch.l | 21 + > gas/testsuite/gas/aarch64/sme2-18.d | 29 + > gas/testsuite/gas/aarch64/sme2-18.s | 21 + > gas/testsuite/gas/aarch64/sme2-19-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-19-invalid.l | 36 + > gas/testsuite/gas/aarch64/sme2-19-invalid.s | 36 + > gas/testsuite/gas/aarch64/sme2-19-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-19-noarch.l | 41 + > gas/testsuite/gas/aarch64/sme2-19.d | 49 + > gas/testsuite/gas/aarch64/sme2-19.s | 43 + > gas/testsuite/gas/aarch64/sme2-2-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-2-invalid.l | 229 + > gas/testsuite/gas/aarch64/sme2-2-invalid.s | 205 + > gas/testsuite/gas/aarch64/sme2-2-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-2-noarch.l | 481 + > gas/testsuite/gas/aarch64/sme2-2.d | 489 + > gas/testsuite/gas/aarch64/sme2-2.s | 511 + > gas/testsuite/gas/aarch64/sme2-20-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-20-invalid.l | 27 + > gas/testsuite/gas/aarch64/sme2-20-invalid.s | 23 + > gas/testsuite/gas/aarch64/sme2-20-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-20-noarch.l | 21 + > gas/testsuite/gas/aarch64/sme2-20.d | 29 + > gas/testsuite/gas/aarch64/sme2-20.s | 21 + > gas/testsuite/gas/aarch64/sme2-21-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-21-invalid.l | 18 + > gas/testsuite/gas/aarch64/sme2-21-invalid.s | 12 + > gas/testsuite/gas/aarch64/sme2-21-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-21-noarch.l | 43 + > gas/testsuite/gas/aarch64/sme2-21.d | 51 + > gas/testsuite/gas/aarch64/sme2-21.s | 47 + > gas/testsuite/gas/aarch64/sme2-22-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-22-invalid.l | 27 + > gas/testsuite/gas/aarch64/sme2-22-invalid.s | 13 + > gas/testsuite/gas/aarch64/sme2-22-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-22-noarch.l | 111 + > gas/testsuite/gas/aarch64/sme2-22.d | 119 + > gas/testsuite/gas/aarch64/sme2-22.s | 131 + > gas/testsuite/gas/aarch64/sme2-23-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-23-invalid.l | 14 + > gas/testsuite/gas/aarch64/sme2-23-invalid.s | 8 + > gas/testsuite/gas/aarch64/sme2-23-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-23-noarch.l | 65 + > gas/testsuite/gas/aarch64/sme2-23.d | 73 + > gas/testsuite/gas/aarch64/sme2-23.s | 79 + > gas/testsuite/gas/aarch64/sme2-24-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-24-invalid.l | 22 + > gas/testsuite/gas/aarch64/sme2-24-invalid.s | 13 + > gas/testsuite/gas/aarch64/sme2-24-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-24-noarch.l | 17 + > gas/testsuite/gas/aarch64/sme2-24.d | 25 + > gas/testsuite/gas/aarch64/sme2-24.s | 19 + > gas/testsuite/gas/aarch64/sme2-25-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-25-invalid.l | 48 + > gas/testsuite/gas/aarch64/sme2-25-invalid.s | 28 + > gas/testsuite/gas/aarch64/sme2-25-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-25-noarch.l | 37 + > gas/testsuite/gas/aarch64/sme2-25.d | 45 + > gas/testsuite/gas/aarch64/sme2-25.s | 44 + > gas/testsuite/gas/aarch64/sme2-26-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-26-invalid.l | 13 + > gas/testsuite/gas/aarch64/sme2-26-invalid.s | 14 + > gas/testsuite/gas/aarch64/sme2-26-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-26-noarch.l | 25 + > gas/testsuite/gas/aarch64/sme2-26.d | 33 + > gas/testsuite/gas/aarch64/sme2-26.s | 29 + > gas/testsuite/gas/aarch64/sme2-27-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-27-invalid.l | 31 + > gas/testsuite/gas/aarch64/sme2-27-invalid.s | 25 + > gas/testsuite/gas/aarch64/sme2-27-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-27-noarch.l | 50 + > gas/testsuite/gas/aarch64/sme2-27.d | 62 + > gas/testsuite/gas/aarch64/sme2-27.s | 71 + > gas/testsuite/gas/aarch64/sme2-28-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-28-invalid.l | 19 + > gas/testsuite/gas/aarch64/sme2-28-invalid.s | 11 + > gas/testsuite/gas/aarch64/sme2-28-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-28-noarch.l | 26 + > gas/testsuite/gas/aarch64/sme2-28.d | 34 + > gas/testsuite/gas/aarch64/sme2-28.s | 29 + > gas/testsuite/gas/aarch64/sme2-29-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-29-invalid.l | 39 + > gas/testsuite/gas/aarch64/sme2-29-invalid.s | 14 + > gas/testsuite/gas/aarch64/sme2-29-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-29-noarch.l | 37 + > gas/testsuite/gas/aarch64/sme2-29.d | 45 + > gas/testsuite/gas/aarch64/sme2-29.s | 47 + > gas/testsuite/gas/aarch64/sme2-3-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-3-invalid.l | 75 + > gas/testsuite/gas/aarch64/sme2-3-invalid.s | 62 + > gas/testsuite/gas/aarch64/sme2-3-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-3-noarch.l | 481 + > gas/testsuite/gas/aarch64/sme2-3.d | 489 + > gas/testsuite/gas/aarch64/sme2-3.s | 511 + > gas/testsuite/gas/aarch64/sme2-30-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-30-invalid.l | 29 + > gas/testsuite/gas/aarch64/sme2-30-invalid.s | 18 + > gas/testsuite/gas/aarch64/sme2-30-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-30-noarch.l | 91 + > gas/testsuite/gas/aarch64/sme2-30.d | 99 + > gas/testsuite/gas/aarch64/sme2-30.s | 109 + > gas/testsuite/gas/aarch64/sme2-4-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-4-invalid.l | 75 + > gas/testsuite/gas/aarch64/sme2-4-invalid.s | 62 + > gas/testsuite/gas/aarch64/sme2-4-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-4-noarch.l | 481 + > gas/testsuite/gas/aarch64/sme2-4.d | 489 + > gas/testsuite/gas/aarch64/sme2-4.s | 511 + > gas/testsuite/gas/aarch64/sme2-5-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-5-invalid.l | 75 + > gas/testsuite/gas/aarch64/sme2-5-invalid.s | 62 + > gas/testsuite/gas/aarch64/sme2-5-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-5-noarch.l | 481 + > gas/testsuite/gas/aarch64/sme2-5.d | 489 + > gas/testsuite/gas/aarch64/sme2-5.s | 511 + > gas/testsuite/gas/aarch64/sme2-6-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-6-invalid.l | 139 + > gas/testsuite/gas/aarch64/sme2-6-invalid.s | 92 + > gas/testsuite/gas/aarch64/sme2-6-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-6-noarch.l | 145 + > gas/testsuite/gas/aarch64/sme2-6.d | 153 + > gas/testsuite/gas/aarch64/sme2-6.s | 164 + > gas/testsuite/gas/aarch64/sme2-7-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-7-invalid.l | 20 + > gas/testsuite/gas/aarch64/sme2-7-invalid.s | 14 + > gas/testsuite/gas/aarch64/sme2-7-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-7-noarch.l | 321 + > gas/testsuite/gas/aarch64/sme2-7.d | 329 + > gas/testsuite/gas/aarch64/sme2-7.s | 351 + > gas/testsuite/gas/aarch64/sme2-8-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-8-invalid.l | 208 + > gas/testsuite/gas/aarch64/sme2-8-invalid.s | 116 + > gas/testsuite/gas/aarch64/sme2-8-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-8-noarch.l | 104 + > gas/testsuite/gas/aarch64/sme2-8.d | 112 + > gas/testsuite/gas/aarch64/sme2-8.s | 124 + > gas/testsuite/gas/aarch64/sme2-9-invalid.d | 3 + > gas/testsuite/gas/aarch64/sme2-9-invalid.l | 179 + > gas/testsuite/gas/aarch64/sme2-9-invalid.s | 128 + > gas/testsuite/gas/aarch64/sme2-9-noarch.d | 3 + > gas/testsuite/gas/aarch64/sme2-9-noarch.l | 177 + > gas/testsuite/gas/aarch64/sme2-9.d | 185 + > gas/testsuite/gas/aarch64/sme2-9.s | 199 + > .../gas/aarch64/sme2-f64f64-1-invalid.d | 3 + > .../gas/aarch64/sme2-f64f64-1-invalid.l | 27 + > .../gas/aarch64/sme2-f64f64-1-invalid.s | 20 + > .../gas/aarch64/sme2-f64f64-1-noarch.d | 3 + > .../gas/aarch64/sme2-f64f64-1-noarch.l | 33 + > gas/testsuite/gas/aarch64/sme2-f64f64-1.d | 41 + > gas/testsuite/gas/aarch64/sme2-f64f64-1.s | 35 + > .../gas/aarch64/sme2-f64f64-2-invalid.d | 3 + > .../gas/aarch64/sme2-f64f64-2-invalid.l | 98 + > .../gas/aarch64/sme2-f64f64-2-invalid.s | 87 + > .../gas/aarch64/sme2-f64f64-2-noarch.d | 3 + > .../gas/aarch64/sme2-f64f64-2-noarch.l | 117 + > gas/testsuite/gas/aarch64/sme2-f64f64-2.d | 125 + > gas/testsuite/gas/aarch64/sme2-f64f64-2.s | 127 + > .../gas/aarch64/sme2-i16i64-1-invalid.d | 3 + > .../gas/aarch64/sme2-i16i64-1-invalid.l | 111 + > .../gas/aarch64/sme2-i16i64-1-invalid.s | 86 + > .../gas/aarch64/sme2-i16i64-1-noarch.d | 3 + > .../gas/aarch64/sme2-i16i64-1-noarch.l | 57 + > gas/testsuite/gas/aarch64/sme2-i16i64-1.d | 65 + > gas/testsuite/gas/aarch64/sme2-i16i64-1.s | 61 + > .../gas/aarch64/sme2-i16i64-2-invalid.d | 3 + > .../gas/aarch64/sme2-i16i64-2-invalid.l | 95 + > .../gas/aarch64/sme2-i16i64-2-invalid.s | 88 + > .../gas/aarch64/sme2-i16i64-2-noarch.d | 3 + > .../gas/aarch64/sme2-i16i64-2-noarch.l | 253 + > gas/testsuite/gas/aarch64/sme2-i16i64-2.d | 261 + > gas/testsuite/gas/aarch64/sme2-i16i64-2.s | 283 + > .../gas/aarch64/sme2-i16i64-3-invalid.d | 3 + > .../gas/aarch64/sme2-i16i64-3-invalid.l | 19 + > .../gas/aarch64/sme2-i16i64-3-invalid.s | 12 + > .../gas/aarch64/sme2-i16i64-3-noarch.d | 3 + > .../gas/aarch64/sme2-i16i64-3-noarch.l | 125 + > gas/testsuite/gas/aarch64/sme2-i16i64-3.d | 133 + > gas/testsuite/gas/aarch64/sme2-i16i64-3.s | 135 + > .../gas/aarch64/sme2-i16i64-4-invalid.d | 3 + > .../gas/aarch64/sme2-i16i64-4-invalid.l | 11 + > .../gas/aarch64/sme2-i16i64-4-invalid.s | 12 + > .../gas/aarch64/sme2-i16i64-4-noarch.d | 3 + > .../gas/aarch64/sme2-i16i64-4-noarch.l | 21 + > gas/testsuite/gas/aarch64/sme2-i16i64-4.d | 29 + > gas/testsuite/gas/aarch64/sme2-i16i64-4.s | 21 + > gas/testsuite/gas/aarch64/sve-invalid.l | 24 +- > gas/testsuite/gas/aarch64/sve-invalid.s | 1 + > .../gas/aarch64/sve-sme2-1-invalid.d | 3 + > .../gas/aarch64/sve-sme2-1-invalid.l | 51 + > .../gas/aarch64/sve-sme2-1-invalid.s | 25 + > gas/testsuite/gas/aarch64/sve-sme2-1-noarch.d | 3 + > gas/testsuite/gas/aarch64/sve-sme2-1-noarch.l | 25 + > gas/testsuite/gas/aarch64/sve-sme2-1.d | 33 + > gas/testsuite/gas/aarch64/sve-sme2-1.s | 27 + > .../gas/aarch64/sve2-sme2-1-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-1-invalid.l | 12 + > .../gas/aarch64/sve2-sme2-1-invalid.s | 12 + > .../gas/aarch64/sve2-sme2-1-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-1-noarch.l | 33 + > gas/testsuite/gas/aarch64/sve2-sme2-1.d | 41 + > gas/testsuite/gas/aarch64/sve2-sme2-1.s | 35 + > .../gas/aarch64/sve2-sme2-2-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-2-invalid.l | 25 + > .../gas/aarch64/sve2-sme2-2-invalid.s | 12 + > .../gas/aarch64/sve2-sme2-2-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-2-noarch.l | 257 + > gas/testsuite/gas/aarch64/sve2-sme2-2.d | 265 + > gas/testsuite/gas/aarch64/sve2-sme2-2.s | 287 + > .../gas/aarch64/sve2-sme2-3-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-3-invalid.l | 17 + > .../gas/aarch64/sve2-sme2-3-invalid.s | 15 + > .../gas/aarch64/sve2-sme2-3-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-3-noarch.l | 29 + > gas/testsuite/gas/aarch64/sve2-sme2-3.d | 41 + > gas/testsuite/gas/aarch64/sve2-sme2-3.s | 35 + > .../gas/aarch64/sve2-sme2-4-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-4-invalid.l | 17 + > .../gas/aarch64/sve2-sme2-4-invalid.s | 15 + > .../gas/aarch64/sve2-sme2-4-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-4-noarch.l | 40 + > gas/testsuite/gas/aarch64/sve2-sme2-4.d | 54 + > gas/testsuite/gas/aarch64/sve2-sme2-4.s | 49 + > .../gas/aarch64/sve2-sme2-5-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-5-invalid.l | 27 + > .../gas/aarch64/sve2-sme2-5-invalid.s | 12 + > .../gas/aarch64/sve2-sme2-5-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-5-noarch.l | 13 + > gas/testsuite/gas/aarch64/sve2-sme2-5.d | 21 + > gas/testsuite/gas/aarch64/sve2-sme2-5.s | 14 + > .../gas/aarch64/sve2-sme2-6-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-6-invalid.l | 20 + > .../gas/aarch64/sve2-sme2-6-invalid.s | 14 + > .../gas/aarch64/sve2-sme2-6-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-6-noarch.l | 16 + > gas/testsuite/gas/aarch64/sve2-sme2-6.d | 24 + > gas/testsuite/gas/aarch64/sve2-sme2-6.s | 17 + > .../gas/aarch64/sve2-sme2-7-invalid.d | 3 + > .../gas/aarch64/sve2-sme2-7-invalid.l | 29 + > .../gas/aarch64/sve2-sme2-7-invalid.s | 9 + > .../gas/aarch64/sve2-sme2-7-noarch.d | 3 + > .../gas/aarch64/sve2-sme2-7-noarch.l | 16 + > gas/testsuite/gas/aarch64/sve2-sme2-7.d | 24 + > gas/testsuite/gas/aarch64/sve2-sme2-7.s | 17 + > gas/testsuite/gas/aarch64/system.d | 2 +- > include/opcode/aarch64.h | 107 +- > opcodes/aarch64-asm-2.c | 350 +- > opcodes/aarch64-asm.c | 153 +- > opcodes/aarch64-asm.h | 5 + > opcodes/aarch64-dis-2.c | 9561 +++++++++++++---- > opcodes/aarch64-dis.c | 171 +- > opcodes/aarch64-dis.h | 5 + > opcodes/aarch64-opc-2.c | 69 +- > opcodes/aarch64-opc.c | 526 +- > opcodes/aarch64-opc.h | 54 +- > opcodes/aarch64-tbl.h | 742 +- > 346 files changed, 36993 insertions(+), 2255 deletions(-) > create mode 100644 gas/testsuite/gas/aarch64/rprfm-1-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/rprfm-1-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/rprfm-1-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/rprfm-1.d > create mode 100644 gas/testsuite/gas/aarch64/rprfm-1.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sme2-1-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-1-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-1-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sme2-1.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-1.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-10-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-10-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sme2-10-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-10-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-10-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sme2-10.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-10.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sme2-11-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sme2-11-noarch.l > create mode 100644 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gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-2.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-3.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-4.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-5.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-6.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7-invalid.s > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7-noarch.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7-noarch.l > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7.d > create mode 100644 gas/testsuite/gas/aarch64/sve2-sme2-7.s >
Jan Beulich <jbeulich@suse.com> writes: > On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >> Richard Sandiford (31): >> aarch64: Add +sme2 >> aarch64: Add a _10 suffix to FLD_imm3 >> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >> aarch64: Add support for vgx2 and vgx4 >> aarch64; Add support for vector offset ranges >> aarch64: Add support for predicate-as-counter registers >> aarch64: Add the SME2 MOVA instructions >> aarch64: Add the SME2 multivector LD1 and ST1 instructions > > Less than a 3rd of the patches in this series have made it to my mailbox > (and the list archives), so commenting on e.g. the one above is difficult. Yeah, they got held up in moderation due to the size. > Nevertheless - according to the documentation LD1x (scalar plus immediate, > consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts > are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks > as if the use of SME2_INSN() there is wrong, unless the documentation is > categorizing these incorrectly). They're both (but we haven't added SVE2p1 to binutils yet). E.g. see the pseudocode in: https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en where the condition is: if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; Chronologically, SME2 predates SVE2p1. Thanks, Richard
Jan Beulich <jbeulich@suse.com> writes: > On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >> This series of patches adds SME2 support to the AArch64 backend. >> Details on SME2 are available here: >> >> https://developer.arm.com/documentation/ddi0602/2022-12/SME-Instructions >> >> Tested on aarch64-linux-gnu, and via automatic cross-checking >> against the architecture description and the LLVM implementation. >> >> I've pushed the series under GWP, but I'm more than happy >> to update/adjust/fix based on post-commit review, so please >> let me know if you spot anything you think should be changed. >> >> Thanks, >> Richard >> >> >> Richard Sandiford (31): >> aarch64: Add +sme2 >> aarch64: Add a _10 suffix to FLD_imm3 >> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >> aarch64: Add support for vgx2 and vgx4 >> aarch64; Add support for vector offset ranges >> aarch64: Add support for predicate-as-counter registers > > Shouldn't the (alias) insn forms added here all use SME2_INSN()? It > doesn't seem to make sense to permit them with ".arch_extension sme". That's deliberate (and it's deliberate for the SVE instructions like PFALSE too). The base requirements in the table come from the underlying architectural requirements. In this case, the instructions are unchanged, and so the FEAT_* requirements are the same. Accepting predicate-as-counter registers is just a syntactic convenience. It's true that, without SME2 (or SVE2p1) you might not be able to do much with the predicate-as-counter registers except move, load and store them. But that doesn't make those operations invalid (and so something that the assembler must reject). Thanks, Richard
On 03.04.2023 10:05, Richard Sandiford wrote: > Jan Beulich <jbeulich@suse.com> writes: >> On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >>> Richard Sandiford (31): >>> aarch64: Add +sme2 >>> aarch64: Add a _10 suffix to FLD_imm3 >>> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >>> aarch64: Add support for vgx2 and vgx4 >>> aarch64; Add support for vector offset ranges >>> aarch64: Add support for predicate-as-counter registers >>> aarch64: Add the SME2 MOVA instructions >>> aarch64: Add the SME2 multivector LD1 and ST1 instructions >> >> Less than a 3rd of the patches in this series have made it to my mailbox >> (and the list archives), so commenting on e.g. the one above is difficult. > > Yeah, they got held up in moderation due to the size. > >> Nevertheless - according to the documentation LD1x (scalar plus immediate, >> consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts >> are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks >> as if the use of SME2_INSN() there is wrong, unless the documentation is >> categorizing these incorrectly). > > They're both (but we haven't added SVE2p1 to binutils yet). > E.g. see the pseudocode in: > > https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en > > where the condition is: > > if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; > > Chronologically, SME2 predates SVE2p1. Yet aiui dependency-wise, like SVE2 is a prereq to SME, SVE2.1 is going to be viewed as a prereq to SVE2.1? In which case enabling SVE2.1 alone ought to be sufficient to use these insns? Which would mean all of these (there are quite a few more) would need touching again. Jan
Jan Beulich <jbeulich@suse.com> writes: > On 03.04.2023 10:05, Richard Sandiford wrote: >> Jan Beulich <jbeulich@suse.com> writes: >>> On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >>>> Richard Sandiford (31): >>>> aarch64: Add +sme2 >>>> aarch64: Add a _10 suffix to FLD_imm3 >>>> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >>>> aarch64: Add support for vgx2 and vgx4 >>>> aarch64; Add support for vector offset ranges >>>> aarch64: Add support for predicate-as-counter registers >>>> aarch64: Add the SME2 MOVA instructions >>>> aarch64: Add the SME2 multivector LD1 and ST1 instructions >>> >>> Less than a 3rd of the patches in this series have made it to my mailbox >>> (and the list archives), so commenting on e.g. the one above is difficult. >> >> Yeah, they got held up in moderation due to the size. >> >>> Nevertheless - according to the documentation LD1x (scalar plus immediate, >>> consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts >>> are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks >>> as if the use of SME2_INSN() there is wrong, unless the documentation is >>> categorizing these incorrectly). >> >> They're both (but we haven't added SVE2p1 to binutils yet). >> E.g. see the pseudocode in: >> >> https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en >> >> where the condition is: >> >> if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; >> >> Chronologically, SME2 predates SVE2p1. > > Yet aiui dependency-wise, like SVE2 is a prereq to SME, SVE2.1 is going > to be viewed as a prereq to SVE2.1? Do you mean SVE2p1 being a prereq to SME2? If so, no. FEAT_SME2 && !FEAT_SVE2p1 is a valid combination, and in that case, these instructions will only be available in streaming mode. The way the pseudo expresses this is: if HaveSVE2p1() then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); > In which case enabling SVE2.1 alone > ought to be sufficient to use these insns? Which would mean all of these > (there are quite a few more) would need touching again. When SVE2p1 is added, we'll need to make these instructions available whenever SVE2p1 or SME2 is enabled. It didn't seem worth preempting that by adding SVE2p1 stuff in this series, not least because it wouldn't be testable. But it should be a simple enough change. Thanks, Richard
On 03.04.2023 10:27, Richard Sandiford wrote: > Jan Beulich <jbeulich@suse.com> writes: >> On 03.04.2023 10:05, Richard Sandiford wrote: >>> Jan Beulich <jbeulich@suse.com> writes: >>>> On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >>>>> Richard Sandiford (31): >>>>> aarch64: Add +sme2 >>>>> aarch64: Add a _10 suffix to FLD_imm3 >>>>> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >>>>> aarch64: Add support for vgx2 and vgx4 >>>>> aarch64; Add support for vector offset ranges >>>>> aarch64: Add support for predicate-as-counter registers >>>>> aarch64: Add the SME2 MOVA instructions >>>>> aarch64: Add the SME2 multivector LD1 and ST1 instructions >>>> >>>> Less than a 3rd of the patches in this series have made it to my mailbox >>>> (and the list archives), so commenting on e.g. the one above is difficult. >>> >>> Yeah, they got held up in moderation due to the size. >>> >>>> Nevertheless - according to the documentation LD1x (scalar plus immediate, >>>> consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts >>>> are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks >>>> as if the use of SME2_INSN() there is wrong, unless the documentation is >>>> categorizing these incorrectly). >>> >>> They're both (but we haven't added SVE2p1 to binutils yet). >>> E.g. see the pseudocode in: >>> >>> https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en >>> >>> where the condition is: >>> >>> if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; >>> >>> Chronologically, SME2 predates SVE2p1. >> >> Yet aiui dependency-wise, like SVE2 is a prereq to SME, SVE2.1 is going >> to be viewed as a prereq to SVE2.1? > > Do you mean SVE2p1 being a prereq to SME2? If so, no. FEAT_SME2 > && !FEAT_SVE2p1 is a valid combination, and in that case, these > instructions will only be available in streaming mode. The way the > pseudo expresses this is: > > if HaveSVE2p1() then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); That's different from the SME <-> SVE2 relationship then? Or is that dependency wrong in tc-aarch64.c:aarch64_features[]? Jan
Jan Beulich <jbeulich@suse.com> writes: > On 03.04.2023 10:27, Richard Sandiford wrote: >> Jan Beulich <jbeulich@suse.com> writes: >>> On 03.04.2023 10:05, Richard Sandiford wrote: >>>> Jan Beulich <jbeulich@suse.com> writes: >>>>> On 30.03.2023 12:26, Richard Sandiford via Binutils wrote: >>>>>> Richard Sandiford (31): >>>>>> aarch64: Add +sme2 >>>>>> aarch64: Add a _10 suffix to FLD_imm3 >>>>>> aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_array >>>>>> aarch64: Add support for vgx2 and vgx4 >>>>>> aarch64; Add support for vector offset ranges >>>>>> aarch64: Add support for predicate-as-counter registers >>>>>> aarch64: Add the SME2 MOVA instructions >>>>>> aarch64: Add the SME2 multivector LD1 and ST1 instructions >>>>> >>>>> Less than a 3rd of the patches in this series have made it to my mailbox >>>>> (and the list archives), so commenting on e.g. the one above is difficult. >>>> >>>> Yeah, they got held up in moderation due to the size. >>>> >>>>> Nevertheless - according to the documentation LD1x (scalar plus immediate, >>>>> consecutive registers) and their LDNT1x, ST1x, and STNT1x counterparts >>>>> are (unlike the strided forms) SVE2.1 insns, not SME2 ones (IOW it looks >>>>> as if the use of SME2_INSN() there is wrong, unless the documentation is >>>>> categorizing these incorrectly). >>>> >>>> They're both (but we haven't added SVE2p1 to binutils yet). >>>> E.g. see the pseudocode in: >>>> >>>> https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/LD1B--scalar-plus-immediate--consecutive-registers---Contiguous-load-of-bytes-to-multiple-consecutive-vectors--immediate-index--?lang=en >>>> >>>> where the condition is: >>>> >>>> if !HaveSME2() && !HaveSVE2p1() then UNDEFINED; >>>> >>>> Chronologically, SME2 predates SVE2p1. >>> >>> Yet aiui dependency-wise, like SVE2 is a prereq to SME, SVE2.1 is going >>> to be viewed as a prereq to SVE2.1? >> >> Do you mean SVE2p1 being a prereq to SME2? If so, no. FEAT_SME2 >> && !FEAT_SVE2p1 is a valid combination, and in that case, these >> instructions will only be available in streaming mode. The way the >> pseudo expresses this is: >> >> if HaveSVE2p1() then CheckSVEEnabled(); else CheckStreamingSVEEnabled(); > > That's different from the SME <-> SVE2 relationship then? Or is that > dependency wrong in tc-aarch64.c:aarch64_features[]? Yeah, it's a different relationship from SME <-> SVE2. For one thing, SVE2p1 includes things that SME2 doesn't, such as: https://developer.arm.com/documentation/ddi0602/2022-12/SVE-Instructions/ADDQV--Unsigned-add-reduction-of-quadword-vector-segments-?lang=en FEAT_SME && !FEAT_SVE is architecturally valid, but we took the decision not to support it for tools. The rule that +sme implies +sve2 is therefore a software requirement rather than an ISA requirement. Thanks, Richard