From patchwork Wed Oct 19 15:15:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 360 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:4ac7:0:0:0:0:0 with SMTP id y7csp383155wrs; Wed, 19 Oct 2022 08:18:04 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4qnWSYG/XC3S4AgQx3srof7h16weB5cDZtjTLelZb3bUmBKnwfbbKWy3i+IP6KzaClYQP9 X-Received: by 2002:a17:907:628a:b0:781:bbff:1d42 with SMTP id nd10-20020a170907628a00b00781bbff1d42mr7008725ejc.375.1666192684249; Wed, 19 Oct 2022 08:18:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1666192684; cv=none; d=google.com; s=arc-20160816; b=WnyX9od4RW70oGyCQal4eTdhL7/RUjV+6BlgmDV8s8onmE7blGc4ZKngrM5BNsBkd2 y3zXsXDMoPV/ihpKWKQ8ZTtumHWJa9vDvMuz3Z3nwvpHE041IzXS8CUdk0wF8sd1g57O bDrcu1LCGqRJtK5i1vNDBQVfGhsZO4k0gdn7qr59kcBYpPWQemdC3PHYXC2iORh2r6uU 7hWXTLQlQ6WjjedXWEiLxbO2eBd3mucuxThIZtnr36Iz8pmaWcM4hlx7Yt831n73phlh ZWvhZw//nFEi2Qb+sJ+m3vdMawuPb/T+aCrxD6t4yje65c3UoYGazlC0RpVrwWQvJrvn GNKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence:message-id:date :subject:to:dmarc-filter:delivered-to:dkim-signature:dkim-filter; bh=lF3bF/QBtBDnQLm74SOHq/iaUr0lJiALDNrqqi8j+5U=; b=NkEoh/ns4e9eYS37mfNprPB7iYcYnKFQFr27N8dwQm6xG5udWPm6m3NSd/ZIkdaI3C nOTsyZAB65GT1KvKYpeOk1qI40SWroecSC9u5B3+6NqBzTp0+wTSmV//KmUiwuAWIii5 C3trqTFU0xCVhtGLXobZAMbLEeZnNx8I5Nh5wfUbvq36bIru4ByBVqJu6RsV1Tl5m3UL NoHCuh/EdcyYJ5kDmVKDMFaSsbUqqQO1QJQjiOrgLpNTz2yRmUkskwcEooOfreSqI78t rtyQ8tfZNiHlUFKCc7eA31CwPrbbl2jEzgmX6jYPPzj5Mqa+/d4tOKGZJEuJugZFH5rE LNdg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=lcSDq1KC; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id sb36-20020a1709076da400b0078dd22dd569si15639993ejc.121.2022.10.19.08.18.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 08:18:04 -0700 (PDT) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=lcSDq1KC; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EABD1385841D for ; Wed, 19 Oct 2022 15:17:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EABD1385841D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1666192678; bh=lF3bF/QBtBDnQLm74SOHq/iaUr0lJiALDNrqqi8j+5U=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=lcSDq1KCp8SJoGgoYfDrwipzrXgk59xPUEdtGc1yWa+F8SNNN/OOvDZQtX/rIZajb HMMY7ijhjBoj78P49YSwrK1N/z+IjSIsiGpu+bcEMWylv6WqPdYt6IRAuhpSKsl6s7 hSa872WCr7XzQbuCvfcYA/0DUd9n2QDuUr6grT6A= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id 0BC41385841A for ; Wed, 19 Oct 2022 15:17:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0BC41385841A X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="305175404" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="305175404" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2022 08:17:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10505"; a="631714096" X-IronPort-AV: E=Sophos;i="5.95,196,1661842800"; d="scan'208";a="631714096" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga007.fm.intel.com with ESMTP; 19 Oct 2022 08:17:37 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9A5181007800; Wed, 19 Oct 2022 23:17:36 +0800 (CST) To: binutils@sourceware.org Subject: [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions (Resend) Date: Wed, 19 Oct 2022 23:15:24 +0800 Message-Id: <20221019151534.45521-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-5.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Binutils From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1747129660374242828?= X-GMAIL-MSGID: =?utf-8?q?1747129660374242828?= Hi all, Please ignore the first cover letter of this v2 series. I forgot to reset the i386-init.h and i386-tbl.h changes in those patches and most of them won't be sent. I will resend the patches in this series. Sorry for the disturb. This is our v2 patches for newly released Intel Architecture Instruction Set Extensions and Future Features. The document comes following: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html The changes we HAVEN'T DONE: 1. All the reviews in AVX-NE-CONVERT, RAO-INT, PREFETCHI. The patch owner for AVX-NE-CONVERT and RAO-INT is currently busy with the GCC patches adjustment for these two ISAs and haven't finished the change yet. We will update that in next version. For PREFETCHI, since it is quite special, some more discussion is welcomed before further change. For these three patches, there might have some general changes and will be mentioned below. 2. The Suffix things in CMPccXADD. We have inconsistency for No_Suf usage for CMPccXADD and RAO-INT. We will align them in next version. The changes we HAVE DONE: 1. The AVX2 prereq for AVX-IFMA and AVX-VNNI-INT8. 2. The changes from ANY_xxx to xxx for CMPccXADD, WRMSRNS, MSRLIST. It is very unlikely for these three ISAs have future ISAs that depend on them. Therefore, I changed ANY_xxx to xxx. For other ISAs, we keep the ANY_xxx since we suppose there might be dependency on them. But it still need discussion. There is potential we will remove some of them in v3 (most likely AMX-FP16 and PREFETCHI). And we haven't removed those flags in i386-gen.c. It seems that we could also safely remove them right? 3. Removed lockbad testcases in WRMSRNS, MSRLIST, PREFETCHI. Since most of the insts are lockbad, the testcases in these three patches are not needed. 4. Combined CMPccXADD insts in i386-opc.tbl. Use to combine them, also include those alias not is documentation. Including them is better for developer to use them. 5. Changes in tables due to folding AVXVNNI entry patch. 6. Correct the wrong comment for CpuUnused in CMPccXADD patch and add missing comma for SUBARCH in that patch. 7. Fix in comments for singular, VexVVVV=1 to VexVVVV, Vex128 to Vex. 8. Removal for ALL noxxx things in texi file. The reviews need further discussion/investigation: 1. PseudoVexPrefix related ISAs. 2. Table combination and usage in CMPccXADD. Need further investigation how we could make it simpler. And I haven't investigated whether OP_M usage can save the modrm_table pass. 3. SwapSources in CMPccXADD. We may need a special identifier for CMPccXADD since we have VVVV at operand 3, where it is always at operand 2 for all other insts which have VVVV. That is the reason we reuse SwapSources. It might be not that same as the original meaning. But we want to avoid adding a bit for this very rare case. Do we need to change that? 4. The replacement from _ to - in i386-opc.tbl comments. It seems that recent ISA patches are mostly using _. So I am confused about that. 5. Testcase for WRMSRNS and MSRLIST. The 32bit and 64bit can be shared as mentioned. But we cannot just remove one of them right? All the above are the changes in V2 patch. If there is something missing, just remind us. Thx, Haochen