mbox series

[v2,0/10] Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions

Message ID 20221019145608.45213-1-haochen.jiang@intel.com
Headers
Series Add new Intel Sierra Forest, Grand Ridge, Granite Rapids Instructions |

Message

Jiang, Haochen Oct. 19, 2022, 2:55 p.m. UTC 
  Hi all,

This is our v2 patches for newly released
Intel Architecture Instruction Set Extensions and Future Features.

The document comes following:
https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

The changes we HAVEN'T DONE:

1. All the reviews in AVX-NE-CONVERT, RAO-INT, PREFETCHI.
The patch owner for AVX-NE-CONVERT and RAO-INT is currently busy with the
GCC patches adjustment for these two ISAs and haven't finished the change
yet. We will update that in next version.

For PREFETCHI, since it is quite special, some more discussion is welcomed
before further change.

For these three patches, there might have some general changes and will be
mentioned below.

2. The Suffix things in CMPccXADD.
We have inconsistency for No_Suf usage for CMPccXADD and RAO-INT. We will
align them in next version.

The changes we HAVE DONE:

1. The AVX2 prereq for AVX-IFMA and AVX-VNNI-INT8.

2. The changes from ANY_xxx to xxx for CMPccXADD, WRMSRNS, MSRLIST.
It is very unlikely for these three ISAs have future ISAs that depend on
them. Therefore, I changed ANY_xxx to xxx.

For other ISAs, we keep the ANY_xxx since we suppose there might be
dependency on them. But it still need discussion. There is potential we will
remove some of them in v3 (most likely AMX-FP16 and PREFETCHI).

And we haven't removed those flags in i386-gen.c. It seems that we could also
safely remove them right?

3. Removed lockbad testcases in WRMSRNS, MSRLIST, PREFETCHI.
Since most of the insts are lockbad, the testcases in these three patches are
not needed.

4. Combined CMPccXADD insts in i386-opc.tbl.
Use <cc> to combine them, also include those alias not is documentation.
Including them is better for developer to use them.

5. Changes in tables due to folding AVXVNNI entry patch.

6. Correct the wrong comment for CpuUnused in CMPccXADD patch and add missing
comma for SUBARCH in that patch.

7. Fix in comments for singular, VexVVVV=1 to VexVVVV, Vex128 to Vex.

8. Removal for ALL noxxx things in texi file.

The reviews need further discussion/investigation:

1. PseudoVexPrefix related ISAs.

2. Table combination and usage in CMPccXADD.
Need further investigation how we could make it simpler. And I haven't
investigated whether OP_M usage can save the modrm_table pass.

3. SwapSources in CMPccXADD.
We may need a special identifier for CMPccXADD since we have VVVV at
operand 3, where it is always at operand 2 for all other insts which
have VVVV. That is the reason we reuse SwapSources. It might be not
that same as the original meaning. But we want to avoid adding a bit
for this very rare case. Do we need to change that?

4. The replacement from _ to - in i386-opc.tbl comments.
It seems that recent ISA patches are mostly using _. So I am confused
about that.

5. Testcase for WRMSRNS and MSRLIST.
The 32bit and 64bit can be shared as mentioned. But we cannot just
remove one of them right?

All the above are the changes in V2 patch. If there is something
missing, just remind us.

Thx,
Haochen

Comments

Jan Beulich Oct. 19, 2022, 3:17 p.m. UTC | #1 
On 19.10.2022 16:55, Haochen Jiang wrote:
> Hi all,
> 
> This is our v2 patches for newly released
> Intel Architecture Instruction Set Extensions and Future Features.
> 
> The document comes following:
> https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
> 
> The changes we HAVEN'T DONE:

Just to avoid misunderstanding with the items here and ...

> The reviews need further discussion/investigation:

... the ones mentioned here it's quite hard to tell which, if any, parts
of this v2 make sense to re-review. Unless told more specifically, I
guess I'll wait for v3 until I take another thorough look.

Jan
Frager, Neal via Binutils Oct. 19, 2022, 3:22 p.m. UTC | #2 
> -----Original Message-----
> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, October 19, 2022 11:17 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: hjl.tools@gmail.com; binutils@sourceware.org
> Subject: Re: [PATCH v2 0/10] Add new Intel Sierra Forest, Grand Ridge, Granite
> Rapids Instructions
> 
> On 19.10.2022 16:55, Haochen Jiang wrote:
> > Hi all,
> >
> > This is our v2 patches for newly released
> > Intel Architecture Instruction Set Extensions and Future Features.
> >
> > The document comes following:
> > https://www.intel.com/content/www/us/en/develop/download/intel-
> architecture-instruction-set-extensions-programming-reference.html
> >
> > The changes we HAVEN'T DONE:
> 
> Just to avoid misunderstanding with the items here and ...
> 
> > The reviews need further discussion/investigation:
> 
> ... the ones mentioned here it's quite hard to tell which, if any, parts
> of this v2 make sense to re-review. Unless told more specifically, I
> guess I'll wait for v3 until I take another thorough look.

I split them into two parts since those HAVEN'T DONE part will be changes.
while those in discussion part might keep how they were like.

> 
> Jan