Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 Commit message: "RISC-V: Reorganize binary autovec testcases" > git rev-list --no-walk c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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[PR98536]","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/8283eb31e9bd32b704bd337a846ea980c1d4e182.camel@tugraz.at/mbox/"},{"id":131504,"url":"https://patchwork.plctlab.org/api/1.2/patches/131504/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/ffd3c7b1b0c71e13f40471aeef643b9c9e3c0353.camel@tugraz.at/","msgid":"","list_archive_url":null,"date":"2023-08-05T16:33:04","name":"[C] Support typename as selector in _Generic","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/ffd3c7b1b0c71e13f40471aeef643b9c9e3c0353.camel@tugraz.at/mbox/"},{"id":131546,"url":"https://patchwork.plctlab.org/api/1.2/patches/131546/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230805204324.2434846-1-apinski@marvell.com/","msgid":"<20230805204324.2434846-1-apinski@marvell.com>","list_archive_url":null,"date":"2023-08-05T20:43:24","name":"MATCH: Extend min_value/max_value to pointer types","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230805204324.2434846-1-apinski@marvell.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-08/mbox/"}]' + bundle_id=27 + git-pw bundle add 27 131559 +------------+------------------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+------------------------------------------------------------------------------------------------------------------| | ID | 27 | | Name | gcc-patch_2023-08 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-08/ | | Owner | patchwork-bot | | Project | gcc-patch | | Public | True | | Patches | 128781 [COMMITTED] PR tree-optimization/110582 - fur_list should not use the range vector for non-ssa, operands. | | | 128790 ipa-sra: Don't consider CLOBBERS as writes preventing splitting | | | 128800 [COMMITTEDv3] tree-optimization: [PR100864] `(a&!b) | b` is not opimized to `a | b` for comparisons | | | 128809 [1/2] Move `~X & X` and `~X | X` over to use bitwise_inverted_equal_p | | | 128810 [2/2] Slightly improve bitwise_inverted_equal_p comparisons | | | 128860 PHIOPT: Mark the conditional lhs and rhs as to look at to see if DCEable | | | 128879 c++: parser cleanup, remove dummy arguments | | | 128924 libbacktrace patch committed | | | 128925 [COMMITTEDv2] Fix PR 93044: extra cast is not removed | | | 128929 c++: improve debug_tree for templated types/decls | | | 128930 tree-pretty-print: handle COMPONENT_REF with non-decl RHS | | | 128958 preprocessor: c++: Support `#pragma GCC target' macros [PR87299] | | | 128992 Adjust testcase for more optimal codegen. | | | 128993 x86: fold two of vec_dupv2df's alternatives | | | 128994 [RESEND] libatomic: drop redundant all-multi command | | | 129013 [V3] VECT: Support CALL vectorization for COND_LEN_* | | | 129032 [v1] RISC-V: Support RVV VFSUB and VFRSUB rounding mode intrinsic API | | | 129062 [COMMITTED] ada: Emit SCOs for nested decisions in quantified expressions | | | 129059 [COMMITTED] ada: check Atree.Get/Set_Field_Value | | | 129060 [COMMITTED] ada: Fix generation of JSON output for data representation | | | 129061 [COMMITTED] ada: Default Put_Image for composite derived types is missing information | | | 129063 [COMMITTED] ada: Incorrect optimization for unconstrained limited record component type | | | 129065 [COMMITTED] ada: Bugbox compiling Constrained_Protected_Object'Image | | | 129066 [COMMITTED] ada: Disable inlining of subprograms with Skip(_Flow_And)_Proof in GNATprove | | | 129064 [COMMITTED] ada: Fix printing of numbers in JSON output for data representation | | | 129069 [PING^1,v8] tree-ssa-sink: Improve code sinking pass. | | | 129071 [PING^3] PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces. | | | 129072 PING^3] [PATCH 3/4] ree: Improve functionality of ree pass for rs6000 target. | | | 129085 [COMMITTED] doc: Fix spelling in arm_v8_1m_main_cde_mve_fp | | | 129108 MAINTAINERS: correct my email address | | | 129129 Fix profile upate after vectorizer peeling | | | 129294 [avr,committed] Fix PR target/110220: Set JUMP_LABEL as required. | | | 129315 analyzer: stash values for CPython plugin [PR107646] | | | 129317 [committed] MAINTAINERS: Add myself to write after approval | | | 129323 RISC-V: Implement vector "average" autovec pattern. | | | 129355 [OpenACC,2.7,v2] Implement default clause support for data constructs | | | 129381 arm: Remove unsigned variant of vcaddq_m | | | 129416 [v2] rs6000: Fix __builtin_altivec_vcmpne{b,h,w} implementation | | | 129425 [1/2] bpf: Implementation of BPF CO-RE builtins | | | 129424 [2/2] bpf: CO-RE builtins support tests. | | | 129439 [Committed] IBM Z: Handle unaligned symbols | | | 129445 match.pd: Canonicalize (signed x << c) >> c [PR101955] | | | 129447 match.pd: Canonicalize (signed x << c) >> c [PR101955] | | | 129456 [v4] i386: Allow -mlarge-data-threshold with -mcmodel=large | | | 129538 Support vec_fmaddsub/vec_fmsubadd for vector HFmode. | | | 129545 Optimize vlddqu + inserti128 to vbroadcasti128 | | | 129546 [v3,RISC-V] Generate Zicond instruction for select pattern with condition eq or neq to 0 | | | 129561 [v1] RISC-V: Support RVV VFWADD rounding mode intrinsic API | | | 129613 [committed,RISC-V] Avoid sub-word mode comparisons with Zicond | | | 129630 [v2] RISC-V: Support RVV VFWADD rounding mode intrinsic API | | | 129669 Fix profile update after cancelled loop distribution | | | 129689 [v1] RISC-V: Enhance the test case for RVV vfsub/vfrsub rounding | | | 129708 Enable tpause Exponential backoff and thread delay | | | 129717 [v3] mklog: handle Signed-off-by, minor cleanup | | | 129735 [1/3,v2] Support get_or_insert in ordered_hash_map | | | 129736 [2/3,v2] genmatch: Reduce variability of generated code | | | 129737 [3/3,v2] genmatch: Log line numbers indirectly | | | 129743 [v1] RISC-V: Support RVV VFWSUB rounding mode intrinsic API | | | 129746 AArch64 update costing for MLA by invariant | | | 129747 AArch64 update costing for combining vector conditionals | | | 129751 AArch64 Undo vec_widen_shiftl optabs [PR106346] | | | 129752 [gensupport] : Don't segfault on empty attrs list | | | 129788 Make add_phi_node_to_bb static | | | 129796 aarch64: SVE/NEON Bridging intrinsics | | | 129816 [1/2] Add virtual operand global liveness computation class | | | 129817 [2/2] Improve sinking with unrelated defs | | | 129850 PR combine/110867 Fix narrow comparison of memory and constant | | | 129925 arm/aarch64: Add bti for all functions [PR106671] | | | 129930 _BitInt bit-field support [PR102989] | | | 129933 [v2] analyzer: stash values for CPython plugin [PR107646] | | | 129934 match.pd: Canonicalize (signed x << c) >> c [PR101955] | | | 129991 [v2,1/3] libgomp, nvptx: low-latency memory allocator | | | 129989 [v2,2/3] openmp, nvptx: low-lat memory access traits | | | 129993 [v2,3/3] amdgcn, libgomp: low-latency allocator | | | 129998 [committed,RISC-V] Fix 20010221-1.c with zicond | | | 130057 [v3] analyzer: stash values for CPython plugin [PR107646] | | | 130167 [x86] PR target/110792: Early clobber issues with rot32di2_doubleword. | | | 130218 MATCH: first of the value replacement moving from phiopt | | | 130238 [v1] RISC-V: Support RVV VFMUL rounding mode intrinsic API | | | 130243 [V2] RISC-V: Support CALL conditional autovec patterns | | | 130245 [v1] RISC-V: Remove redudant extern declaration in function base | | | 130258 Fix `~X & X` and `~X | X` patterns | | | 130259 [v2] RISC-V: Support RVV VFMUL rounding mode intrinsic API | | | 130261 Fix PR 110874: infinite loop in gimple_bitwise_inverted_equal_p with fre | | | 130268 [V4] VECT: Support CALL vectorization for COND_LEN_* | | | 130290 [RFC] Combine zero_extract and sign_extend for TARGET_TRULY_NOOP_TRUNCATION | | | 130294 [v1] RISC-V: Support RVV VFDIV and VFRDIV rounding mode intrinsic API | | | 130317 [v1] RISC-V: Support RVV VFWMUL rounding mode intrinsic API | | | 130325 s390: Enable vect_bswap test cases | | | 130326 s390: Try to emit vlbr/vstbr instead of vperm et al. | | | 130341 [x86] Split SUBREGs of SSE vector registers into vec_select insns. | | | 130343 Introduce -msmp to select /lib_smp/ on ppc-vx6 | | | 130376 [01/10] x86: "prefix_extra" tidying | | | 130377 [02/10] x86: "sse4arg" adjustments | | | 130380 [03/10] x86: "ssemuladd" adjustments | | | 130379 [04/10] x86: "prefix_extra" can't really be "2" | | | 130386 [05/10] x86: replace/correct bogus "prefix_extra" | | | 130389 [06/10] x86: drop stray "prefix_extra" | | | 130381 [07/10] x86: add (adjust) XOP insn attributes | | | 130393 [08/10] x86: add missing "prefix" attribute to VF{,C}MULC | | | 130385 [09/10] x86: correct "length_immediate" in a few cases | | | 130398 [10/10] x86: drop redundant "prefix_data16" attributes | | | 130440 Swap loop splitting and final value replacement | | | 130444 [v3,RFC] c-family: Implement __has_feature and __has_extension [PR60512] | | | 130459 c-family: Add _BitInt support for __atomic_*fetch* [PR102989] | | | 130478 [RFC] c++: extend cold, hot attributes to classes | | | 130482 [v3,1/8] LoongArch: Add Loongson SX vector directive compilation framework. | | | 130488 [v3,2/8] LoongArch: Add Loongson SX base instruction support. | | | 130485 [v3,3/8] LoongArch: Add Loongson SX directive builtin function support. | | | 130483 [v3,4/8] LoongArch: Add Loongson ASX vector directive compilation framework. | | | 130486 [v3,5/8] LoongArch: Add Loongson ASX base instruction support. | | | 130484 [v3,6/8] LoongArch: Add Loongson ASX directive builtin function support. | | | 130534 [COMMITTED] ada: Adjust again address arithmetics in System.Dwarf_Lines | | | 130533 [COMMITTED] ada: Fix spurious error on 'Input of private type with Type_Invariant aspect | | | 130536 [COMMITTED] ada: Rewrite Set_Image_*_Unsigned routines to remove recursion. | | | 130535 [COMMITTED] ada: Add pragma Annotate for GNATcheck exemptions | | | 130542 tree-optimization/110702 - avoid zero-based memory references in IVOPTs | | | 130559 poly_int: Handle more can_div_trunc_p cases | | | 130584 [libbacktrace] fix up broken test | | | 130609 mid-end: Use integral time intervals in timevar.cc | | | 130625 [committed] analyzer: fix ICE on zero-sized arrays [PR110882] | | | 130661 [1/3,v3] Support get_or_insert in ordered_hash_map | | | 130659 [2/3,v3] genmatch: Reduce variability of generated code | | | 130660 [3/3,v3] genmatch: Log line numbers indirectly | | | 130663 [v1] RISC-V: Fix one comment for binop_frm insn | | | 130669 [v1] RISC-V: Support RVV VFMACC rounding mode intrinsic API | | | 130673 [committed] testsuite, analyzer: add test case [PR108171] | | | 130676 [committed,RISC-V] Remove errant hunk of code | | | 130729 Add documentation for -Wflex-array-member-not-at-end. | | | 130733 [PATCHv2] Fix PR 110874: infinite loop in gimple_bitwise_inverted_equal_p with fre | | | 130784 [COMMITTED] Automatically set type is certain Value_Range routines. | | | 130785 [COMMITTED] Provide a routine for NAME == NAME relation. | | | 130787 [COMMITTED] Add operand ranges to op1_op2_relation API. | | | 130814 Specify signed/unsigned/dontcare in calls to extract_bit_field_1. | | | 130846 Fix profiledbootstrap | | | 130849 Update estimated iteraitons counts after splitting | | | 130919 [v1] RISC-V: Support RVV VFNMACC rounding mode intrinsic API | | | 130933 [v1] RISC-V: Support RVV VFMSAC rounding mode intrinsic API | | | 130942 [v1] RISC-V: Support RVV VFNMSAC rounding mode intrinsic API | | | 130970 [C] _Generic should not warn in non-active branches [PR68193,PR97100] | | | 130973 [v1] RISC-V: Support RVV VFMADD rounding mode intrinsic API | | | 130984 Disable loop distribution for loops with estimated iterations 0 | | | 131023 [avr,committed] Fix some typos in avr-mcus.def | | | 131024 [avr,committed] Add some more devices to avr-mcus.def. | | | 131054 mid-end: Use integral time intervals in timevar.cc | | | 131068 tree-optimization/110838 - less aggressively fold out-of-bound shifts | | | 131072 tree-optimization/110838 - vectorization of widened right shifts | | | 131170 [pushed,LRA] Check input insn pattern hard regs against early clobber hard regs for live info | | | 131215 libatomic: Improve ifunc selection on AArch64 | | | 131284 Add -Wdisabled-optimization warning for not optimizing sibling calls | | | 131295 _Decimal* to _BitInt conversion support [PR102989] | | | 131320 [V2,1/3] Provide counted_by attribute to flexible array member field (PR108896) | | | 131321 [V2,2/3] Use the counted_by atribute info in builtin object size [PR108896] | | | 131322 [V2,3/3] Use the counted_by attribute information in bound sanitizer[PR108896] | | | 131340 [pushed] analyzer: fix some svalue::dump_to_pp implementations | | | 131341 [pushed] analyzer: handle function attribute "alloc_size" [PR110426] | | | 131372 match.pd: Implement missed optimization ((x ^ y) & z) | x -> (z & y) | x [PR109938] | | | 131497 | | | 131500 [committed] c: Less warnings for parameters declared as arrays [PR98536] | | | 131504 [C] Support typename as selector in _Generic | | | 131546 MATCH: Extend min_value/max_value to pointer types | | | 131559 [v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic | +------------+------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master fatal: refusing to merge unrelated histories + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series54067-patch131559 ++ git branch -a ++ grep 'series54067-patch131559$' + checkbranch= + checkbranchresult=null + '[' null = series54067-patch131559 ']' + git checkout -b series54067-patch131559 Switched to a new branch 'series54067-patch131559' ++ curl https://patchwork.plctlab.org/api/1.2/series/54067/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1418 100 1418 0 0 10907 0 --:--:-- --:--:-- --:--:-- 10907 + series_response='{"id":54067,"url":"https://patchwork.plctlab.org/api/1.2/series/54067/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=54067","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","date":"2023-08-06T03:36:12","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/54067/mbox/","cover_letter":null,"patches":[{"id":131559,"url":"https://patchwork.plctlab.org/api/1.2/patches/131559/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/","msgid":"<20230806033612.1078855-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-08-06T03:36:12","name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/"}]}' ++ echo '{"id":54067,"url":"https://patchwork.plctlab.org/api/1.2/series/54067/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=54067","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","date":"2023-08-06T03:36:12","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/54067/mbox/","cover_letter":null,"patches":[{"id":131559,"url":"https://patchwork.plctlab.org/api/1.2/patches/131559/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/","msgid":"<20230806033612.1078855-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-08-06T03:36:12","name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"131559,https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/"' + echo '"131559,https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"131559' ++ sed 's/"//g' + series_patch_id=131559 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='\''\'\'''\''Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='\''Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins10235422312618605108.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='\''Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins10235422312618605108.sh: line 178: ++: command not found ++ ++ declare -p berr /tmp/jenkins10235422312618605108.sh: line 179: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='\''Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 31319 100 31319 0 0 695k 0 --:--:-- --:--:-- --:--:-- 695k +++ bout='Applying: RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-protos.h M gcc/config/riscv/riscv-v.cc M gcc/config/riscv/riscv-vector-builtins.cc M gcc/config/riscv/vector.md Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/vector.md CONFLICT (content): Merge conflict in gcc/config/riscv/vector.md Auto-merging gcc/config/riscv/riscv-vector-builtins.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vector-builtins.cc Auto-merging gcc/config/riscv/riscv-v.cc Auto-merging gcc/config/riscv/riscv-protos.h CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-protos.h error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/9937/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/9937/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/9937/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/131559/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 968 100 428 100 540 2240 2827 --:--:-- --:--:-- --:--:-- 5068 {"id":11588,"url":"https://patchwork.plctlab.org/api/patches/131559/checks/11588/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-08-06T04:17:46.368757","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/9937/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/131559/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":131559,"url":"https://patchwork.plctlab.org/api/1.2/patches/131559/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230806033612.1078855-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-08-06T03:36:12","name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"c7e207741dd8afcf8c86d69bd0803007051531f8","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230806033612.1078855-1-pan2.li@intel.com/mbox/","series":[{"id":54067,"url":"https://patchwork.plctlab.org/api/1.2/series/54067/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=54067","date":"2023-08-06T03:36:12","name":"[v1] RISC-V: Refactor RVV frm_mode attr for rounding mode intrinsic","version":1,"mbox":"https://patchwork.plctlab.org/series/54067/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/131559/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/131559/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:c44e:0:b0:3f2:4152:657d with SMTP id w14csp741157vqr;\n Sat, 5 Aug 2023 20:37:10 -0700 (PDT)","from server2.sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n v4-20020aa7dbc4000000b0052310bfc381si3938095edt.288.2023.08.05.20.37.09\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sat, 05 Aug 2023 20:37:10 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id C685B385841F\n\tfor ; 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a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;\n\ts=default; t=1691293028;\n\tbh=O0ElomUid9VV/nF9dRR5aDXydaaZOdFfle2Bnb9/zkw=;\n\th=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive:\n\t List-Post:List-Help:List-Subscribe:From:Reply-To:From;\n\tb=Knj87lQwTNtlASECtc88xjR9yXA8iD4m0rdCC08m+uUUJqsT0WIohoYiV4l+v+D+2\n\t oGpk4iIKQyEiMuO55VaYoPPdyn5mfM71ADUz+p2+9OFycdf28qXEe8T8Q71RmohwFq\n\t 0XHNLgVGFEqaJArJ3xGrkL2AsL2+NOQbYSnuXx2k=","X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 2FFD13858D1E","X-IronPort-AV":["E=McAfee;i=\"6600,9927,10793\"; a=\"349946553\"","E=Sophos;i=\"6.01,259,1684825200\"; d=\"scan'208\";a=\"349946553\"","E=McAfee;i=\"6600,9927,10793\"; a=\"680407855\"","E=Sophos;i=\"6.01,259,1684825200\"; d=\"scan'208\";a=\"680407855\""],"X-ExtLoop1":"1","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com,\n kito.cheng@gmail.com","Subject":"[PATCH v1] RISC-V: Refactor RVV frm_mode attr for rounding mode\n intrinsic","Date":"Sun, 6 Aug 2023 11:36:12 +0800","Message-Id":"<20230806033612.1078855-1-pan2.li@intel.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Spam-Status":"No, score=-10.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH,\n DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0,\n KAM_ASCII_DIVIDERS, SPF_HELO_NONE, SPF_NONE,\n TXREP autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Pan Li via Gcc-patches ","Reply-To":"pan2.li@intel.com","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"INBOX","X-GMAIL-THRID":"1773449280374170517","X-GMAIL-MSGID":"1773449280374170517"},"content":"From: Pan Li \n\nThe frm_mode attr has some assumptions for each define insn as below.\n\n1. The define insn has at least 9 operands.\n2. The operands[9] must be frm reg.\n3. The operands[9] must be const int.\n\nActually, the frm operand can be operands[8], operands[9] or\noperands[10], and not all the define insn has frm operands.\n\nThis patch would like to refactor frm and eliminate the above\nassumptions, as well as unblock the underlying rounding mode intrinsic\nAPI support.\n\nAfter refactor, the default frm will be none, and the selected insn type\nwill be dyn. For the floating point which honors the frm, we will\nset the frm_mode attr explicitly in define_insn.\n\nPassed both the riscv.exp and rvv.exp for rv32/rv64 tests.\n\nSigned-off-by: Pan Li \n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-protos.h (get_frm_mode): Remove operand\n\tassumptions.\n\t* config/riscv/riscv-v.cc (get_frm_mode): New function.\n\t* config/riscv/riscv-vector-builtins.cc\n\t(function_expander::use_ternop_insn):\n\t* config/riscv/vector.md: Set frm_mode attr explicitly.\n---\n gcc/config/riscv/riscv-protos.h | 1 +\n gcc/config/riscv/riscv-v.cc | 28 ++++\n gcc/config/riscv/riscv-vector-builtins.cc | 22 ++-\n gcc/config/riscv/vector.md | 170 ++++++++++++++--------\n 4 files changed, 159 insertions(+), 62 deletions(-)","diff":"diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h\nindex 324991e2619..33f7cb1d670 100644\n--- a/gcc/config/riscv/riscv-protos.h\n+++ b/gcc/config/riscv/riscv-protos.h\n@@ -236,6 +236,7 @@ bool check_builtin_call (location_t, vec, unsigned int,\n \t\t\t tree, unsigned int, tree *);\n bool const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, HOST_WIDE_INT);\n bool legitimize_move (rtx, rtx);\n+int get_frm_mode (rtx);\n void emit_vlmax_vsetvl (machine_mode, rtx);\n void emit_hard_vlmax_vsetvl (machine_mode, rtx);\n void emit_vlmax_insn (unsigned, int, rtx *, rtx = 0);\ndiff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex 278452b9e05..d5fb8611d6e 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -1513,6 +1513,34 @@ expand_const_vector (rtx target, rtx src)\n gcc_unreachable ();\n }\n \n+/* Get the frm mode with given CONST_INT rtx, the default mode is\n+ FRM_MODE_DYN. */\n+int\n+get_frm_mode (rtx operand)\n+{\n+ gcc_assert (CONST_INT_P (operand));\n+\n+ switch (INTVAL (operand))\n+ {\n+ case FRM_RNE:\n+ return FRM_MODE_RNE;\n+ case FRM_RTZ:\n+ return FRM_MODE_RTZ;\n+ case FRM_RDN:\n+ return FRM_MODE_RDN;\n+ case FRM_RUP:\n+ return FRM_MODE_RUP;\n+ case FRM_RMM:\n+ return FRM_MODE_RMM;\n+ case FRM_DYN:\n+ return FRM_MODE_DYN;\n+ default:\n+ return FRM_MODE_DYN;\n+ }\n+\n+ gcc_unreachable ();\n+}\n+\n /* Expand a pre-RA RVV data move from SRC to DEST.\n It expands move for RVV fractional vector modes. */\n bool\ndiff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex 528dca7ae85..abab06c00ed 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -3730,17 +3730,29 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)\n }\n \n for (int argno = arg_offset; argno < call_expr_nargs (exp); argno++)\n- add_input_operand (argno);\n+ {\n+ if (base->has_rounding_mode_operand_p ()\n+\t && argno == call_expr_nargs (exp) - 2)\n+\t{\n+\t /* Since the rounding mode argument position is not consistent with\n+\t the instruction pattern, we need to skip rounding mode argument\n+\t here. */\n+\t continue;\n+\t}\n+ add_input_operand (argno);\n+ }\n \n add_input_operand (Pmode, get_tail_policy_for_pred (pred));\n add_input_operand (Pmode, get_mask_policy_for_pred (pred));\n add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));\n \n- /* TODO: Currently, we don't support intrinsic that is modeling rounding mode.\n- We add default rounding mode for the intrinsics that didn't model rounding\n- mode yet. */\n+ if (base->has_rounding_mode_operand_p ())\n+ add_input_operand (call_expr_nargs (exp) - 2);\n+\n+ /* The RVV floating-point only support dynamic rounding mode in the\n+ FRM register. */\n if (opno != insn_data[icode].n_generator_args)\n- add_input_operand (Pmode, const0_rtx);\n+ add_input_operand (Pmode, gen_int_mode (riscv_vector::FRM_DYN, Pmode));\n \n return generate_insn (icode);\n }\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex 750b2de8df9..db3ee105ef4 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -867,26 +867,8 @@ (define_attr \"vxrm_mode\" \"rnu,rne,rdn,rod,none\"\n ;; Defines rounding mode of an floating-point operation.\n (define_attr \"frm_mode\" \"rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none\"\n (cond [(eq_attr \"type\" \"vfalu,vfwalu,vfmul,vfdiv,vfwmul\")\n- (cond\n-\t [(match_test \"INTVAL (operands[9]) == riscv_vector::FRM_RNE\")\n-\t (const_string \"rne\")\n-\n-\t (match_test \"INTVAL (operands[9]) == riscv_vector::FRM_RTZ\")\n-\t (const_string \"rtz\")\n-\n-\t (match_test \"INTVAL (operands[9]) == riscv_vector::FRM_RDN\")\n-\t (const_string \"rdn\")\n-\n-\t (match_test \"INTVAL (operands[9]) == riscv_vector::FRM_RUP\")\n-\t (const_string \"rup\")\n-\n-\t (match_test \"INTVAL (operands[9]) == riscv_vector::FRM_RMM\")\n-\t (const_string \"rmm\")\n-\n-\t (match_test \"INTVAL (operands[9]) == riscv_vector::FRM_DYN\")\n-\t (const_string \"dyn\")]\n- (const_string \"none\"))]\n- (const_string \"none\")))\n+\t (const_string \"dyn\")]\n+\t(const_string \"none\")))\n \n ;; -----------------------------------------------------------------\n ;; ---- Miscellaneous Operations\n@@ -6147,7 +6129,9 @@ (define_insn \"@pred_\"\n \"TARGET_VECTOR\"\n \"vf.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -6190,7 +6174,9 @@ (define_insn \"@pred__scalar\"\n \"TARGET_VECTOR\"\n \"vf.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred__scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -6234,7 +6220,9 @@ (define_insn \"@pred__scalar\"\n \"TARGET_VECTOR\"\n \"vf.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred__reverse_scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -6257,7 +6245,9 @@ (define_insn \"@pred__reverse_scalar\"\n \"TARGET_VECTOR\"\n \"vfr.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -6408,7 +6398,9 @@ (define_insn \"*pred_\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"*pred_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, ?&vd, vr, ?&vr\")\n@@ -6441,7 +6433,9 @@ (define_insn \"*pred_\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn_and_rewrite \"*pred_mul_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=&vr, ?&vr\")\n@@ -6478,7 +6472,9 @@ (define_insn_and_rewrite \"*pred_mul_\"\n operands[5] = operands[4] = operands[0];\n }\n [(set_attr \"type\" \"vfmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])\"))])\n \n (define_expand \"@pred_mul__scalar\"\n [(set (match_operand:VF 0 \"register_operand\")\n@@ -6535,7 +6531,9 @@ (define_insn \"*pred__scalar\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"*pred__scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, ?&vd, vr, ?&vr\")\n@@ -6569,7 +6567,9 @@ (define_insn \"*pred__scalar\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn_and_rewrite \"*pred_mul__scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=&vr, ?&vr\")\n@@ -6606,7 +6606,9 @@ (define_insn_and_rewrite \"*pred_mul__scalar\"\n operands[5] = operands[4] = operands[0];\n }\n [(set_attr \"type\" \"vfmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])\"))])\n \n (define_expand \"@pred_mul_neg_\"\n [(set (match_operand:VF 0 \"register_operand\")\n@@ -6668,7 +6670,9 @@ (define_insn \"*pred_\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"*pred_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, ?&vd, vr, ?&vr\")\n@@ -6702,7 +6706,9 @@ (define_insn \"*pred_\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn_and_rewrite \"*pred_mul_neg_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=&vr, ?&vr\")\n@@ -6740,7 +6746,9 @@ (define_insn_and_rewrite \"*pred_mul_neg_\"\n operands[5] = operands[4] = operands[0];\n }\n [(set_attr \"type\" \"vfmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])\"))])\n \n (define_expand \"@pred_mul_neg__scalar\"\n [(set (match_operand:VF 0 \"register_operand\")\n@@ -6799,7 +6807,9 @@ (define_insn \"*pred__scalar\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"*pred__scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, ?&vd, vr, ?&vr\")\n@@ -6834,7 +6844,9 @@ (define_insn \"*pred__scalar\"\n (set_attr \"vl_op_idx\" \"5\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[6])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[7])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[8])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn_and_rewrite \"*pred_mul_neg__scalar\"\n [(set (match_operand:VF 0 \"register_operand\" \"=&vr, ?&vr\")\n@@ -6872,7 +6884,9 @@ (define_insn_and_rewrite \"*pred_mul_neg__scalar\"\n operands[5] = operands[4] = operands[0];\n }\n [(set_attr \"type\" \"vfmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[10])\"))])\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated floating-point unary operations\n@@ -6908,7 +6922,9 @@ (define_insn \"@pred_\"\n (set_attr \"vl_op_idx\" \"4\")\n (set (attr \"ta\") (symbol_ref \"riscv_vector::get_ta(operands[5])\"))\n (set (attr \"ma\") (symbol_ref \"riscv_vector::get_ma(operands[6])\"))\n- (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[7])\"))])\n+ (set (attr \"avl_type\") (symbol_ref \"INTVAL (operands[7])\"))\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_\"\n [(set (match_operand:VF 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -7002,7 +7018,9 @@ (define_insn \"@pred_dual_widen_\"\n \"TARGET_VECTOR\"\n \"vfw.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vf\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_dual_widen__scalar\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr, &vr\")\n@@ -7027,7 +7045,9 @@ (define_insn \"@pred_dual_widen__scalar\"\n \"TARGET_VECTOR\"\n \"vfw.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vf\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_single_widen_add\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr, &vr\")\n@@ -7050,7 +7070,9 @@ (define_insn \"@pred_single_widen_add\"\n \"TARGET_VECTOR\"\n \"vfwadd.wv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwalu\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_single_widen_sub\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr, &vr\")\n@@ -7073,7 +7095,9 @@ (define_insn \"@pred_single_widen_sub\"\n \"TARGET_VECTOR\"\n \"vfwsub.wv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwalu\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_single_widen__scalar\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr, &vr\")\n@@ -7097,7 +7121,9 @@ (define_insn \"@pred_single_widen__scalar\"\n \"TARGET_VECTOR\"\n \"vfw.wf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vf\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated widen floating-point ternary operations\n@@ -7130,7 +7156,9 @@ (define_insn \"@pred_widen_mul_\"\n \"TARGET_VECTOR\"\n \"vfw.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_widen_mul__scalar\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr\")\n@@ -7157,7 +7185,9 @@ (define_insn \"@pred_widen_mul__scalar\"\n \"TARGET_VECTOR\"\n \"vfw.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_widen_mul_neg_\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr\")\n@@ -7184,7 +7214,9 @@ (define_insn \"@pred_widen_mul_neg_\"\n \"TARGET_VECTOR\"\n \"vfw.vv\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_widen_mul_neg__scalar\"\n [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr\")\n@@ -7212,7 +7244,9 @@ (define_insn \"@pred_widen_mul_neg__scalar\"\n \"TARGET_VECTOR\"\n \"vfw.vf\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwmuladd\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[9])\"))])\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated floating-point comparison operations\n@@ -7522,7 +7556,9 @@ (define_insn \"@pred_fcvt_x_f\"\n \"TARGET_VECTOR\"\n \"vfcvt.x.f.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfcvtftoi\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_\"\n [(set (match_operand: 0 \"register_operand\" \"=vd, vd, vr, vr\")\n@@ -7562,7 +7598,9 @@ (define_insn \"@pred_\"\n \"TARGET_VECTOR\"\n \"vfcvt.f.x.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfcvtitof\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated floating-point widen conversions\n@@ -7590,7 +7628,9 @@ (define_insn \"@pred_widen_fcvt_x_f\"\n \"TARGET_VECTOR\"\n \"vfwcvt.x.f.v\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfwcvtftoi\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_widen_\"\n [(set (match_operand:VWCONVERTI 0 \"register_operand\" \"=&vr, &vr\")\n@@ -7675,7 +7715,9 @@ (define_insn \"@pred_narrow_fcvt_x_f\"\n \"TARGET_VECTOR\"\n \"vfncvt.x.f.w\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfncvtftoi\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_narrow_\"\n [(set (match_operand: 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n@@ -7715,7 +7757,9 @@ (define_insn \"@pred_narrow_\"\n \"TARGET_VECTOR\"\n \"vfncvt.f.x.w\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfncvtitof\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_trunc\"\n [(set (match_operand: 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n@@ -7736,7 +7780,9 @@ (define_insn \"@pred_trunc\"\n \"TARGET_VECTOR\"\n \"vfncvt.f.f.w\\t%0,%3%p1\"\n [(set_attr \"type\" \"vfncvtftof\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n (define_insn \"@pred_rod_trunc\"\n [(set (match_operand: 0 \"register_operand\" \"=vd, vd, vr, vr, &vr, &vr\")\n@@ -8016,7 +8062,9 @@ (define_insn \"@pred_reduc_plus\"\n \"TARGET_VECTOR\"\n \"vfredsum.vs\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfred\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; Float Ordered Reduction Sum for SF\n (define_insn \"@pred_reduc_plus\"\n@@ -8042,7 +8090,9 @@ (define_insn \"@pred_reduc_plus\"\n \"TARGET_VECTOR\"\n \"vfredsum.vs\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfred\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set ( 100 34745 100 34595 100 150 489k 2173 --:--:-- --:--:-- --:--:-- 491k attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; Float Ordered Reduction Sum for DF\n (define_insn \"@pred_reduc_plus\"\n@@ -8068,7 +8118,9 @@ (define_insn \"@pred_reduc_plus\"\n \"TARGET_VECTOR\"\n \"vfredsum.vs\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfred\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; Float Widen Reduction for HF, aka SF = HF op SF\n (define_insn \"@pred_widen_reduc_plus\"\n@@ -8090,7 +8142,9 @@ (define_insn \"@pred_widen_reduc_plus\"\n \"TARGET_VECTOR\"\n \"vfwredsum.vs\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwred\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; Float Widen Reduction for SF, aka DF = SF * DF\n (define_insn \"@pred_widen_reduc_plus\"\n@@ -8112,7 +8166,9 @@ (define_insn \"@pred_widen_reduc_plus\"\n \"TARGET_VECTOR\"\n \"vfwredsum.vs\\t%0,%3,%4%p1\"\n [(set_attr \"type\" \"vfwred\")\n- (set_attr \"mode\" \"\")])\n+ (set_attr \"mode\" \"\")\n+ (set (attr \"frm_mode\")\n+\t(symbol_ref \"(enum attr_frm_mode) riscv_vector::get_frm_mode (operands[8])\"))])\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated permutation operations\n","prefixes":["v1"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE