Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 Commit message: "RISC-V: Reorganize binary autovec testcases" > git rev-list --no-walk c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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issue with SUBREGs in SET_DEST.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/002001d9a1e7$aa0daac0$fe290040$@nextmovesoftware.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-06/mbox/"}]' + bundle_id=24 + git-pw bundle add 24 109629 +------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | ID | 24 | | Name | gcc-patch_2023-06 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-06/ | | Owner | patchwork-bot | | Project | gcc-patch | | Public | True | | Patches | 101534 [1/3] testsuite: Unbork multilib testing on RISC-V (and any target really) | | | 101535 [2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp | | | 101536 [3/3] testsuite: print any leaking torture options for debugging | | | 101552 Move std::search into algobase.h | | | 101560 [1/3] testsuite: move handle-multiline-outputs to before check for blank lines | | | 101562 [2/3] diagnostics: add support for "text art" diagrams | | | 101561 [3/3] analyzer: add text-art visualizations of out-of-bounds accesses [PR106626] | | | 101569 OpenMP/Fortran: Permit pure directives inside PURE | | | 101571 [committed] libstdc++: Fix configure test for 32-bit targets | | | 101575 [committed] libstdc++: Fix build for targets without _Float128 [PR109921] | | | 101582 [committed] libstdc++: Express std::vector's size() <= capacity() invariant in code | | | 101583 [committed] libstdc++: Stop using _GLIBCXX_USE_C99_MATH_TR1 in | | | 101584 [committed] libstdc++: Add separate autoconf macro for std::float_t and std::double_t [PR109818] | | | 101653 [V2] RISC-V: Support RVV permutation auto-vectorization | | | 101677 libstdc++: optimize EH phase 2 | | | 101686 [pushed] c++: make -fpermissive avoid -Werror=narrowing | | | 101690 doc: improve docs for -pedantic{,-errors} | | | 101693 RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization | | | 101701 [v5] MIPS: Add speculation_barrier support | | | 101702 [V3] VECT: Change flow of decrement IV | | | 101704 PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces. | | | 101743 [2/3,v3] xtensa: Add 'adddi3' and 'subdi3' insn patterns | | | 101786 RISC-V: Introduce vfloat16m{f}*_t and their machine mode. | | | 101787 [v5] tree-ssa-sink: Improve code sinking pass | | | 101791 RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations | | | 101796 Don't try bswap + rotate when TYPE_PRECISION(n->type) > n->range. | | | 101801 [V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations | | | 101805 [committed] libstdc++: Fix condition for supported SIMD types on ARMv8 | | | 101874 doc: Fix description of x86 -m32 option [PR109954] | | | 101902 RISC-V: Add test for vfloat16*_t (non tuple) types | | | 101964 [COMMITTED] cse: Change return type of predicate functions from int to bool | | | 101974 [1/2] c++: refine dependent_alias_template_spec_p [PR90679] | | | 101975 [2/2] c++: partial ordering and dep alias tmpl specs [PR90679] | | | 102002 [committed] libstdc++: Document removal of implicit allocator rebinding extensions | | | 102005 [committed] libstdc++: Fix code size regressions in std::vector [PR110060] | | | 102006 [committed] libstdc++: Do not use std::expected::value() in monadic ops (LWG 3938) | | | 102020 [fortran] PR87477 - [meta-bug] [F03] issues concerning the ASSOCIATE statement | | | 102062 [committed] libstdc++: Fix PSTL test that fails in C++20 | | | 102065 libstdc++: Use AS_IF in configure.ac | | | 102070 inline: improve internal function costs | | | 102073 gimple-range: implement widen plus range | | | 102141 Fortran: force error on bad KIND specifier [PR88552] | | | 102161 [Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) | | | 102162 [Committed] testsuite: print any leaking torture options for debugging | | | 102163 rs6000: Fix arguments for __builtin_altivec_tr_stxvrwx, __builtin_altivec_tr_stxvrhx | | | 102171 [RFC] range-op restructuring | | | 102205 c++: fix up caching of level lowered ttps | | | 102232 RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102233 rs6000: Fix expected counts powerpc/p9-vec-length-full | | | 102236 RISC-V: Add __RISCV_ prefix to VXRM and FRM enum | | | 102248 i386: Add missing vector truncate patterns [PR92658]. | | | 102249 [vect] Use intermiediate integer type for float_expr/fix_trunc_expr when direct optab is not existed. | | | 102262 [RFA] c++: make initializer_list array static again [PR110070] | | | 102277 RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102278 [V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102280 [COMMITTED] MAINTAINERS: Add myself as MIPS port maintainer | | | 102283 [RFA] varasm: check float size | | | 102287 RISC-V: Fix warning in predicated.md | | | 102300 RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV | | | 102317 RISC-V: Optimize reverse series index vector | | | 102334 RISCV: Add -m(no)-omit-leaf-frame-pointer support. | | | 102342 rtl-optimization: [PR102733] DSE removing address which only differ by address space. | | | 102376 Fix PR101188 wrong code from postreload | | | 102412 [V2] RISC-V: Fix warning in predicated.md | | | 102426 Consider '--with-build-sysroot=[...]' for target libraries' build-tree testing (instead of build-time 'CC' etc.) [PR109951] | | | 102427 [PR110086] avr: Fix ICE on optimize attribute | | | 102473 [1/2,RISC-V] fix cfi issue in save-restore. | | | 102474 [2/2,V3,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 102502 [avr,committed] Improve operations on non-LD_REGS when the operation follows a move from LD_REGS. | | | 102549 Add more ForEachMacros to clang-format file | | | 102559 [pushed] analyzer: regions in different memory spaces can't alias | | | 102561 [pushed] analyzer: implement various atomic builtins [PR109015] | | | 102575 New wi::bitreverse function. | | | 102578 c++: is_specialization_of_friend confusion [PR109923] | | | 102579 c++: simplify TEMPLATE_TEMPLATE_PARM hashing | | | 102582 [COMMITTED] reg-stack: Change return type of predicate functions from int to bool | | | 102592 c++: replace in_template_function | | | 102596 [01/12,contrib] validate_failures.py: Avoid testsuite aliasing | | | 102601 [02/12,contrib] validate_failures.py: Support expiry attributes in manifests | | | 102600 [03/12,contrib] validate_failures.py: Read in manifest when comparing build dirs | | | 102598 [04/12,contrib] validate_failures.py: Simplify GetManifestPath() | | | 102603 [05/12,contrib] validate_failures.py: Add more verbosity levels | | | 102602 [06/12,contrib] validate_failures.py: Be more stringent in parsing result lines | | | 102604 [07/12,contrib] validate_failures.py: Use exit code "2" to indicate regression | | | 102607 [08/12,contrib] validate_failures.py: Support "$tool:" prefix in exp names | | | 102605 [09/12,contrib] validate_failures.py: Improve error output | | | 102599 [10/12,contrib] validate_failures.py: Add new option --invert_match | | | 102606 [11/12,contrib] validate_failures.py: Add "--expiry_date YYYYMMDD" option | | | 102608 [12/12,contrib] validate_failures.py: Ignore stray filesystem paths in results | | | 102628 libstdc++: Do not assume existence of char8_t codecvt facet | | | 102629 [pushed] c++: fix explicit/copy problem [PR109247] | | | 102630 c++: bad 'this' conversion for nullary memfn [PR106760] | | | 102633 [committed] btf: Fix -Wformat errors | | | 102654 [committed] btf: fix bootstrap -Wformat errors [PR110073] | | | 102659 libatomic: Enable lock-free 128-bit atomics on AArch64 [PR110061] | | | 102660 [committed] Fortran: fix diagnostics for SELECT RANK [PR100607] | | | 102677 [pushed] Darwin, PPC: Fix struct layout with pragma pack [PR110044]. | | | 102807 xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode | | | 102837 libatomic: x86_64: Always try ifunc | | | 102840 RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill | | | 102863 [x86_64] PR target/110083: Fix-up REG_EQUAL notes on COMPARE in STV. | | | 102924 [x86] Add support for stc, clc and cmc instructions in i386.md | | | 102925 xtensa: Optimize boolean evaluation or branching when EQ/NE to INT_MIN | | | 102964 RISC-V: Support RVV FP16 ZVFHMIN intrinsic API | | | 102969 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 | | | 102970 [NFC] RISC-V: Reorganize riscv-v.cc | | | 102975 RISC-V: Split arguments of expand_vec_perm | | | 102976 [NFC] RISC-V: Move optimization patterns into autovec-opt.md | | | 103038 [committed] Convert H8 port to LRA | | | 103046 [RFA] Improve strcmp expansion when one input is a constant string. | | | 103053 [x86] Add missing vec_pack/unpacks patterns for _Float16 <-> int/float conversion. | | | 103057 MAINTAINERS: move Matthew Fortune to Write After Approval | | | 103061 [V2] VECT: Add SELECT_VL support | | | 103081 Fix PR 110085: `make clean` in GCC directory on sh target causes a failure | | | 103086 [1/2] Improve do_store_flag for single bit when there is no non-zero bits | | | 103087 [2/2] Handle const_int in expand_single_bit_test | | | 103092 [RISC-V] add TC for save-restore cfi directives. | | | 103097 rs6000: Remove duplicate expression [PR106907] | | | 103098 [v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API | | | 103194 [v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode | | | 103180 RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. | | | 103182 [v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API | | | 103199 [V3] VECT: Add SELECT_VL support | | | 103202 ??????: Re: [PATCH V3] VECT: Add SELECT_VL support | | | 103219 Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90' | | | 103222 driver: Forward '-lgfortran', '-lm' to offloading compilation | | | 103303 libiberty: writeargv: Simplify function error mode. | | | 103312 [v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API | | | 103318 [v1] RISC-V: Fix some typo in vector-iterators.md | | | 103334 Ping: Fwd: [V9][PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832] | | | 103364 [COMMITTED] reginfo: Change return type of predicate functions from int to bool | | | 103365 [COMMITTED] print-rtl: Change return type of two print functions from int to void | | | 103397 [committed] d: Warn when declared size of a special enum does not match its intrinsic type. | | | 103502 c++: extend lookup_template_class shortcut [PR110122] | | | 103528 [RISC-V] correct machine mode in save-restore cfi RTL. | | | 103536 [committed] bootstrap rtl-checking: Fix XVEC vs XVECEXP in postreload.cc | | | 103548 RISC-V: Support RVV VLA SLP auto-vectorization | | | 103555 Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. | | | 103554 Don't fold _mm{, 256}_blendv_epi8 into (mask < 0 ? src1 : src2) when -funsigned-char. | | | 103556 riscv: Fix insn cost calculation | | | 103557 riscv: Fix scope for memory model calculation | | | 103586 [v3] MIPS16: Implement `code_readable` function attribute. | | | 103595 middle-end/110055 - avoid CLOBBERing static variables | | | 103598 tree-optimization/109143 - improve PTA compile time | | | 103627 [v2] Explicitly view_convert_expr mask to signed type when folding pblendvb builtins. | | | 103637 [1/2] Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. | | | 103680 rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932] | | | 103681 rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011] | | | 103695 libgcc: Fix eh_frame fast path in find_fde_tail | | | 103696 [1/2] Missed opportunity to use [SU]ABD | | | 103698 RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103736 [committed] libstdc++: Use close-on-exec for file descriptors in filesystem::copy_file | | | 103741 [committed] libstdc++: Fix ambiguous expression in std::array::front() [PR110139] | | | 103738 [V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103740 RISC-V: Enable SELECT_VL for RVV | | | 103739 RISC-V: Support RVV VLA SLP auto-vectorization | | | 103742 [V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103744 analyzer: Standalone OOB-warning [PR109437, PR109439] | | | 103749 [V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103773 [committed] libstdc++: Protect against macros | | | 103775 libstdc++: Replace use of incorrect non-temporal store | | | 103778 libstdc++: Avoid vector casts while still avoiding PR90424 | | | 103781 [v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern | | | 103830 [GCC,12,committed] d: Merge upstream dmd 316b89f1e3, phobos 8e8aaae50. | | | 103832 [1/2] rs6000: genfusion: Rewrite load/compare code | | | 103833 [2/2] rs6000: genfusion: Delete dead code | | | 103848 libstdc++: Rewrite or avoid casts to 64-bit element types | | | 103862 [1/2] Missed opportunity to use [SU]ABD | | | 103896 [committed] Re: [PATCHv2] openmp: Add support for 'present' modifier | | | 103915 [OpenACC,2.7] Implement host_data must have use_device clause requirement | | | 103917 [OpenACC,2.7] Implement default clause support for data constructs | | | 103929 [2/2] AArch64: New RTL for ABD | | | 103934 [v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 103936 libgomp: plugin-gcn - support 'unified_address' | | | 103960 [committed] libstdc++: Make std::numeric_limits<__float128> more portable [PR104772] | | | 103961 [committed] libstdc++: Update list of known symbol versions for abi-check | | | 103997 [COMMITTED] reload1: Change return type of predicate function from int to bool | | | 104030 c++: unsynthesized defaulted constexpr fn [PR110122] | | | 104095 [ver,2] rs6000: Add builtins for IEEE 128-bit floating point values | | | 104108 [v6,1/4] libcpp: reject codepoints above 0x10FFFF | | | 104110 [v6,2/4] p1689r5: initial support | | | 104109 [v6,4/4] c++modules: report module mapper files as a dependency | | | 104112 For the `-A CMP -B -> B CMP A` pattern allow EQ/NE for all integer types | | | 104116 modula2: Fix bootstrap | | | 104117 [COMMITTED/13] Fix PR 110085: `make clean` in GCC directory on sh target causes a failure | | | 104118 middle-end, i386: Pattern recognize add/subtract with carry [PR79173] | | | 104122 [x86_64] PR target/110104: Missing peephole2 for addcarry. | | | 104135 [x86] PR target/31985: Improve memory operand use with doubleword add. | | | 104159 [1/2] Match: zero_one_valued_p should match 0 constants too | | | 104160 [2/2] Add match patterns for `a ? onezero : onezero` where one of the two operands are constant | | | 104171 [pushed] c++: add NRV testcase [PR58050] | | | 104172 [pushed] c++: fix contracts with NRV | | | 104173 [pushed] c++: fix throwing cleanup with label | | | 104176 [pushed] c++: NRV and goto [PR92407] | | | 104174 [pushed] c++: enable NRVO from inner block [PR51571] | | | 104175 [pushed] c++: Add -Wnrvo | | | 104192 RISC-V: Fix ICE when include riscv_vector.h with rv64gcv | | | 104198 LoongArch: Change jumptable's register constraint to 'q' [PR110136] | | | 104208 [v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104213 [V2] RISC-V: Support RVV VLA SLP auto-vectorization | | | 104223 [v1] LoongArch:Change the default value of LARCH_CALL_RATIO to 6 on the LoongArch architecture. | | | 104243 rs6000: Remove redundant initialization [PR106907] | | | 104248 [1/4,V4,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 104247 [2/4,RISC-V] support cm.popretz in zcmp | | | 104250 [3/4,RISC-V] resolve confilct between zcmp multi push/pop and shrink-wrap-separate | | | 104249 [4/4,RISC-V] support cm.mva01s cm.mvsa01 in zcmp | | | 104258 Add parentheses to clarify precedence between operators [PR106907] | | | 104277 RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104279 Support 'UNSUPPORTED: [...]: exception handling disabled' for libstdc++ testing (was: Support in the GCC(/C++) test suites for '-fno-exceptions') | | | 104317 [v2] LoongArch:Change the default value of LARCH_CALL_RATIO to 6 on the LoongArch architecture. | | | 104323 [v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104326 [testsuite] bump some tsvc timeouts | | | 104338 [V2] Optimize '(X - N * M) / N' to 'X / N - M' if valid | | | 104344 [avr] : Improve bit-extractions as of PR109907. | | | 104385 libiberty: pex-unix.c: Make pex_unix_cleanup signature always match body. | | | 104387 [3/4] ree: Improve functionality of ree pass for rs6000 target. | | | 104444 [committed] testsuite/libgomp.*/target-present-*.{c, f90}: Improve and fix (was: Re: [og12] Fix 'libgomp.{c-c++-common, fortran}/target-present-*' test cases) | | | 104485 [V4] VECT: Add SELECT_VL support | | | 104506 [v2,1/3] RISC-V: Minimal support for ZC* extensions. | | | 104507 [v2,2/3] RISC-V: Enable compressible features when use ZC* extensions. | | | 104508 [v2,3/3] RISC-V: Add ZC* test for failed march args being passed. | | | 104515 RISC-V: Add Veyron V1 pipeline description | | | 104524 [1/3] aarch64: Fix whitespace in ls64 builtin implementation [PR110100] | | | 104523 [2/3] aarch64: Fix wrong code with st64b builtin [PR110100] | | | 104525 [3/3] aarch64: Allow compiler to define ls64 builtins [PR110132] | | | 104534 vect: Don't pass subtype to vect_widened_op_tree where not needed [PR 110142] | | | 104548 [committed] Fix expected test output on hppa | | | 104552 Remove 'gcc/testsuite/g++.dg/warn/Wfree-nonheap-object.s' (was: [PATCH] add -Wmismatched-new-delete to middle end (PR 90629)) | | | 104560 Tighten 'dg-warning' alternatives in 'c-c++-common/Wfree-nonheap-object{,-2,-3}.c' (was: [PATCH] correct -Wmismatched-new-delete (PR 98160, 98166)) | | | 104593 [committed] libstdc++: Fix some tests that fail with -fexcess-precision=standard | | | 104597 [committed] libstdc++: Fix some tests that fail with -fno-exceptions | | | 104598 [committed] libstdc++: Restore accidentally removed version in abi-check | | | 104608 [fortran] PR87477 - (associate) - [meta-bug] [F03] issues concerning the ASSOCIATE statement | | | 104628 i386: Fix endless recursion in ix86_expand_vector_init_general with MMX [PR110152] | | | 104630 optabs: Implement double-word ctz and ffs expansion | | | 104634 libstdc++: Fix up 20_util/to_chars/double.cc test for excess precision [PR110145] | | | 104708 MATCH: Fix comment for `(zero_one ==/!= 0) ? y : z y` patterns | | | 104712 [1/3] MATCH: Allow unsigned types for `X & -Y -> X * Y` pattern | | | 104713 [2/3] Change the `zero_one ==/!= 0) ? y : z y` patterns to use multiply rather than `(-zero_one) & z` | | | 104714 [3/3] Add Plus to the op list of `(zero_one == 0) ? y : z y` pattern | | | 104741 [pushed] c++: allow NRV and non-NRV returns [PR58487] | | | 104772 [Committed] Bug fix to new wi::bitreverse_large function. | | | 104774 [nvptx] Update nvptx's bitrev2 pattern to use BITREVERSE rtx. | | | 104789 [1/4] rs6000: build constant via li;rotldi | | | 104792 [2/4] rs6000: build constant via lis;rotldi | | | 104791 [3/4] rs6000: build constant via li/lis;rldicl/rldicr | | | 104790 [4/4] rs6000: build constant via li/lis;rldic | | | 104794 [V5] VECT: Add SELECT_VL support | | | 104800 [v2] LoongArch: Modify the register constraints for template "jumptable" and "indirect_jump" from "r" to "e" [PR110136] | | | 104823 [v6] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104827 [v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104830 [v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104861 [v2] RISC-V: Add more test cases for RVV FP16 | | | 104891 [COMMITTED] analyzer: Standalone OOB-warning, formatting fixed [PR109437, PR109439] | | | 104902 [GCC,AArch64] convert some patterns to new MD syntax | | | 104916 [1/2] Missed opportunity to use [SU]ABD | | | 104920 [2/2] AArch64: New RTL for ABD | | | 104932 [RFC] c++: Accept elaborated-enum-base in system headers | | | 104935 testsuite: fix the condition bug in tsvc s176 | | | 104998 fix frange_nextafter odr violation | | | 105006 [ver,3] rs6000: Add builtins for IEEE 128-bit floating point values | | | 105077 doc: Clarification for -Wmissing-field-initializers | | | 105084 [COMMITTED,1/4] Fix floating point bug in fold_range. | | | 105085 [COMMITTED,2/4] - Remove tree_code from range-operator. | | | 105087 [COMMITTED,3/4] Unify range_operators to one class. | | | 105086 [COMMITTED,4/4] Provide a new dispatch mechanism for range-ops. | | | 105212 MATCH: Fix zero_one_valued_p not to match signed 1 bit integers | | | 105280 [v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 105284 [v4] RISC-V: Add vector psabi checking. | | | 105297 [v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 105316 middle-end/110182 - TYPE_PRECISION on VECTOR_TYPE causes wrong-code | | | 105317 Prevent TYPE_PRECISION on VECTOR_TYPEs | | | 105328 [v1] RISC-V: Fix one warning of frm enum. | | | 105355 [committed] fortran: Fix ICE on pr96024.f90 on big-endian hosts [PR96024] | | | 105424 [V6] VECT: Add SELECT_VL support | | | 105441 [committed] libstdc++: Improve tests for emplace member of sequence containers | | | 105520 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS | | | 105537 [V2] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS | | | 105582 [committed] libstdc++: Optimize std::to_array for trivial types [PR110167] | | | 105583 [committed] libstdc++: Fix P2510R3 "Formatting pointers" [PR110149] | | | 105585 [committed] libstdc++: Bump library version to libstdc++.so.6.0.33 | | | 105590 [committed] libstdc++: Add preprocessor checks to [PR100285] | | | 105594 [committed] libstdc++: Remove duplicate definition of _Float128 std::from_chars [PR110077] | | | 105676 RISC-V: Fix V_WHOLE && V_FRACT iterator requirement | | | 105700 c++: diagnostic ICE b/c of empty TPARMS_PRIMARY_TEMPLATE [PR109655] | | | 105708 [pushed] c++: init-list of uncopyable type [PR110102] | | | 105709 [pushed] c++: diagnose auto in template arg | | | 105711 [pushed] c++: fix 32-bit spaceship failures [PR110185] | | | 105723 [COMMITTED] Relocate range_cast to header, and add a generic version. | | | 105725 [COMMITTED] PR ipa/109886 - Also check type being cast to | | | 105742 MATCH: Fix zero_one_valued_p not to match signed 1 bit integers | | | 105752 [1/2] analyzer: Fix allocation size false positive on conjured svalue [PR109577] | | | 105753 [2/2] testsuite: Add more allocation size tests for conjured svalues [PR110014] | | | 105821 [pushed] analyzer: add caching to globals with initializers [PR110112] | | | 105834 [V3] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS | | | 105841 [v1] RISC-V: Add test cases for RVV FP16 vreinterpret | | | 105844 [COMMITTED,1/15] - Provide a unified range-op table. | | | 105847 [2/15] Unify EQ_EXPR range operator. | | | 105845 [COMMITTED,3/15] Unify NE_EXPR range operator | | | 105846 [COMMITTED,4/15] Unify LT_EXPR range operator | | | 105851 [COMMITTED,5/15] Unify LE_EXPR range operator | | | 105853 [COMMITTED,6/15] Unify GT_EXPR range operator | | | 105850 [COMMITTED,7/15] Unify GE_EXPR range operator | | | 105848 [COMMITTED,8/15] Unify Identity range operator | | | 105849 [COMMITTED,9/15] Unify operator_cst range operator | | | 105852 [COMMITTED,10/15] Unify operator_cast range operator | | | 105855 [COMMITTED,11/15] Unify PLUS_EXPR range operator | | | 105854 RISC-V: Enable select_vl for RVV auto-vectorization | | | 105890 (Re: Splitting up 27_io/basic_istream/ignore/wchar_t/94749.cc (takes too long)) | | | 105926 [RFC] Add stdckdint.h header for C23 | | | 106019 [c++] Implement DR 976 | | | 106020 libstdc++: Clarify manual demangle doc | | | 106023 [GCC,13] PR target/109973: CCZmode and CCCmode variants of [v]ptest. | | | 106025 [v1] RISC-V: Support RVV FP16 MISC vlmul ext intrinsic API | | | 106037 [v4,1/6] c++: implement __is_reference built-in trait | | | 106038 [v4,2/6] libstdc++: use new built-in trait __is_reference for std::is_reference | | | 106039 [v4,3/6] c++: implement __is_function built-in trait | | | 106041 [v4,4/6] libstdc++: use new built-in trait __is_function for std::is_function | | | 106040 [v4,5/6] c++, libstdc++: implement __is_void built-in trait | | | 106042 [v4,6/6] libstdc++: make std::is_object dispatch to new built-in traits | | | 106079 [avr,committed] Tidy code for inverted bit insertions | | | 106126 Avoid duplicate vector initializations during RTL expansion. | | | 106162 VECT: Add LEN_MASK_ LOAD/STORE to support flow control for length loop control | | | 106172 [AIX] Debugging does not require a stack frame. | | | 106176 [PATCHv2,rs6000] Add two peephole2 patterns for mr. insn | | | 106177 RISC-V: Add RVV narrow shift right lowering auto-vectorization | | | 106179 [v1] RISC-V: Add test cases for RVV FP16 undefined and vlmul trunc | | | 106211 [V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control | | | 106285 [v1] RISC-V: Support RVV FP16 MISC vget/vset intrinsic API | | | 106293 combine: Narrow comparison of memory and constant | | | 106296 [v5] RISC-V: Add vector psabi checking. | | | 106317 [v2,PR96339] Optimise svlast[ab] | | | 106335 [pushed] c++: build initializer_list in a loop [PR105838] | | | 106337 middle-end/110200 - genmatch force-leaf and convert interaction | | | 106376 RISC-V: Add ZVFHMIN autovec block testcase | | | 106383 [V2] RISC-V: Add ZVFHMIN block autovec testcase | | | 106472 [committed] Regenerate config.in | | | 106506 rs6000: Change bitwise xor to inequality operator [PR106907] | | | 106552 [v1] RISC-V: Fix one potential test failure for RVV vsetvl | | | 106571 Remove DEFAULT_MATCHPD_PARTITIONS macro | | | 106586 Fix disambiguation against .MASK_STORE | | | 106587 rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie | | | 106589 RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation | | | 106602 New finish_compare_by_pieces target hook (for x86). | | | 106662 RISC-V: Implement vec_set and vec_extract. | | | 106663 RISC-V: Add sign-extending variants for vmv.x.s. | | | 106664 [V2] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation | | | 106679 [COMMITTED,1/17] Move operator_addr_expr to the unified range-op table. | | | 106681 [COMMITTED,2/17] - Move operator_bitwise_not to the unified range-op table. | | | 106682 [COMMITTED,3/17] - Move operator_bitwise_xor to the unified range-op table. | | | 106683 [COMMITTED,4/17] - Move operator_bitwise_and to the unified range-op table. | | | 106686 [COMMITTED,5/17] - Move operator_bitwise_or to the unified range-op table. | | | 106689 [COMMITTED,6/17] - Move operator_min to the unified range-op table. | | | 106684 [COMMITTED,7/17] - Move operator_max to the unified range-op table. | | | 106687 [COMMITTED,8/17] - Split pointer based range operators to range-op-ptr.cc | | | 106693 [COMMITTED,9/17] - Add a hybrid BIT_AND_EXPR operator for integer and pointer. | | | 106696 [COMMITTED,10/17] - Add a hybrid BIT_IOR_EXPR operator for integer and pointer. | | | 106685 [COMMITTED,11/17] - Add a hybrid MIN_EXPR operator for integer and pointer. | | | 106697 [COMMITTED,12/17] - Add a hybrid MAX_EXPR operator for integer and pointer. | | | 106688 [COMMITTED,13/17] - Remove type from range_op_handler table selection | | | 106690 [COMMITTED,14/17] - Switch from unified table to range_op_table. There can be only one. | | | 106694 [COMMITTED,15/17] - Provide a default range_operator via range_op_handler. | | | 106692 [COMMITTED,16/17] - Provide interface for non-standard operators. | | | 106695 [COMMITTED,17/17] PR tree-optimization/110205 - Add some overrides. | | | 106712 [committed] OpenMP: Cleanups related to the 'present' modifier | | | 106764 [committed,PR,rtl-optimization/101188] Fix reload_cse_move2add ignoring clobbers | | | 106779 c: Add __typeof_unqual__ and __typeof_unqual support | | | 106784 c, c++: Accept __builtin_classify_type (typename) | | | 106787 c: Add stdckdint.h header for C23 | | | 106891 Fortran: fix passing of zero-sized array arguments to procedures [PR86277] | | | 106920 [v5,1/6] c++: implement __is_reference built-in trait | | | 106921 [v5,2/6] libstdc++: use new built-in trait __is_reference for std::is_reference | | | 106922 [v5,3/6] c++: implement __is_function built-in trait | | | 106923 [v5,4/6] libstdc++: use new built-in trait __is_function for std::is_function | | | 106925 [v5,5/6] c++, libstdc++: implement __is_void built-in trait | | | 106926 [v5,6/6] libstdc++: make std::is_object dispatch to new built-in traits | | | 106929 [v6,1/6] c++: implement __is_reference built-in trait | | | 106930 [v6,2/6] libstdc++: use new built-in trait __is_reference for std::is_reference | | | 106932 [v6,3/6] c++: implement __is_function built-in trait | | | 106931 [v6,4/6] libstdc++: use new built-in trait __is_function for std::is_function | | | 106935 [v6,5/6] c++, libstdc++: implement __is_void built-in trait | | | 106933 [v6,6/6] libstdc++: make std::is_object dispatch to new built-in traits | | | 106936 [v7,1/6] c++: implement __is_reference built-in trait | | | 106937 [v7,2/6] libstdc++: use new built-in trait __is_reference for std::is_reference | | | 106938 [v7,3/6] c++: implement __is_function built-in trait | | | 106939 [v7,4/6] libstdc++: use new built-in trait __is_function for std::is_function | | | 106940 [v7,5/6] c++, libstdc++: implement __is_void built-in trait | | | 106941 [v7,6/6] libstdc++: make std::is_object dispatch to new built-in traits | | | 106962 [wwwdocs] cxx-dr-status: Update from C++ Core Language Issue TOC, Revision 111 | | | 107005 [v4] Add condition coverage profiling | | | 107016 [1/9] vect: Move vect_model_load_cost next to the transform in vectorizable_load | | | 107019 [2/9] vect: Adjust vectorizable_load costing on VMAT_GATHER_SCATTER && gs_info.decl | | | 107017 [3/9] vect: Adjust vectorizable_load costing on VMAT_INVARIANT | | | 107022 [4/9] vect: Adjust vectorizable_load costing on VMAT_ELEMENTWISE and VMAT_STRIDED_SLP | | | 107023 [5/9] vect: Adjust vectorizable_load costing on VMAT_GATHER_SCATTER | | | 107018 [6/9] vect: Adjust vectorizable_load costing on VMAT_LOAD_STORE_LANES | | | 107024 [7/9] vect: Adjust vectorizable_load costing on VMAT_CONTIGUOUS_REVERSE | | | 107021 [8/9] vect: Adjust vectorizable_load costing on VMAT_CONTIGUOUS_PERMUTE | | | 107020 [9/9] vect: Adjust vectorizable_load costing on VMAT_CONTIGUOUS | | | 107026 RISC-V: Add comments of some functions | | | 107028 [v6] RISC-V: Add vector psabi checking. | | | 107054 Fix note_defect3 function | | | 107056 [v3] i386: Allow -mlarge-data-threshold with -mcmodel=large | | | 107105 RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. | | | 107116 [v1] RISC-V: Fix one typo in full-vec-movel test | | | 107131 [COMMITTED] ada: Remove explicit decoration of wrapper created in freezing | | | 107135 [COMMITTED] ada: Support new GNAT-specific aspect Ghost_Predicate | | | 107132 [COMMITTED] ada: Simplify appending to a newly created list | | | 107136 [COMMITTED] ada: Tune style in detection of writable function actuals | | | 107140 [COMMITTED] ada: Cleanup expansion of locally handled exception handlers | | | 107144 [COMMITTED] ada: Cleanup finding of locally handled exception handlers | | | 107147 [COMMITTED] ada: Remove wrong comment about expansion of exceptions for GNATprove | | | 107137 [COMMITTED] ada: Factor common processing in expansion of aggregates | | | 107133 [COMMITTED] ada: Fix expansion of aggregates with controlled components | | | 107153 [COMMITTED] ada: Use ghost predicate in standard library | | | 107134 [COMMITTED] ada: Factor out tag assignments from type in expander | | | 107138 [COMMITTED] ada: Add No_Elaboration_Code_All pragma to System.Storage_Elements | | | 107157 [COMMITTED] ada: Mark attribute Initialized as ghost code | | | 107142 [COMMITTED] ada: Fix wrong expansion of limited extension aggregate | | | 107141 [COMMITTED] ada: Small housekeeping work in expansion of extension aggregates | | | 107149 [COMMITTED] ada: Remove unreferenced routine Is_Inherited_Operation_For_Type | | | 107145 [COMMITTED] ada: Remove obsolete code in Analyze_Assignment | | | 107154 [COMMITTED] ada: Streamline expansion of controlled actions for aggregates | | | 107146 [COMMITTED] ada: Fix internal error on imported function with post-condition | | | 107159 [COMMITTED] ada: Fix spurious error on call to function returning private in generic | | | 107150 [COMMITTED] ada: Fix exception raised on invalid contract in generic package | | | 107162 [COMMITTED] ada: Fix iterated component initialization | | | 107167 [COMMITTED] ada: Fix another case of missing Has_Private_View flag | | | 107155 [COMMITTED] ada: Skip elaboration checks for abstract subprograms on derived types | | | 107158 [COMMITTED] ada: Implement new aspect Always_Terminates for SPARK | | | 107160 [COMMITTED] ada: Disable inlining in potentially unevaluated contexts | | | 107163 [COMMITTED] ada: Recognize iterated_component_association as potentially unevaluated | | | 107164 [COMMITTED] ada: Recognize iterated_component_association as repeatedly evaluated | | | 107151 [COMMITTED] ada: Add missing ss_mark/ss_release in quantified expressions | | | 107168 [COMMITTED] ada: Fix decoration of iterated component association for GNATprove | | | 107174 [committed] testsuite: Check int128 effective target for pr109932-{1,2}.c [PR110230] | | | 107184 [1/2] Missed opportunity to use [SU]ABD | | | 107185 [2/2] AArch64: New RTL for ABD | | | 107190 Fix disambiguation against .MASK_LOAD | | | 107191 middle-end/110232 - fix native interpret of vector | | | 107194 [PATCHv3,rs6000] Add two peephole2 patterns for mr. insn | | | 107210 RISC-V: Add more SLP tests | | | 107212 RISC-V: Fix bug of VLA SLP auto-vectorization | | | 107215 [committed] libgomp/testsuite: Add requires-unified-addr-1.{c,f90} [PR109837] | | | 107261 [V2] RISC-V: Add more SLP tests | | | 107263 [ping] Add 'libgomp.{, oacc-}fortran/fortran-torture_execute_math.f90' | | | 107264 [ping] driver: Forward '-lgfortran', '-lm' to offloading compilation | | | 107270 RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` | | | 107273 [V2] RISC-V: Remove duplicate `#include "riscv-vector-switch.def"` | | | 107318 [V3] RISC-V: Add more SLP tests | | | 107336 [pushed] c++: mutable temps in rodata | | | 107344 Fix memory leak in loop header copying | | | 107345 rs6000: replace '(const_int 0)' to 'unspec:BLK [(const_int 0)]' for stack_tie | | | 107369 Add -Wmissing-variable-declarations [PR65213]. | | | 107441 [OpenACC,2.7] Implement self clause for compute constructs | | | 107444 vect: Vectorize via libfuncs | | | 107448 [x86] Convert ptestz of pandn into ptestc. | | | 107458 libcpp: Diagnose #include after failed __has_include [PR80753] | | | 107462 [committed] i386: Fix up whitespace in assembly | | | 107470 [committed] Remove sh5media divtab code | | | 107496 [commited] Remove a couple mudflap remnants | | | 107509 OpenMP: Set default-device-var with OMP_TARGET_OFFLOAD=mandatory | | | 107510 [wwwdocs] gcc-14/changes.html + projects/gomp/: GCC 14 OpenMP update | | | 107547 Fix templated conversion operator demangling | | | 107558 [pushed] c/c++: use positive tone in missing header notes [PR84890] | | | 107635 LoongArch: Set default alignment for functions and labels with -mtune | | | 107637 [v1] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32 | | | 107653 [x86] Use x instead of v for alternative 2 (v, BH) in mov_internal. | | | 107657 [V6] Fix power10 fusion and -fstack-protector, PR target/105325 | | | 107659 [v1] RISC-V: Align the predictor style for define_insn_and_split | | | 107695 RISC-V: Use merge approach to optimize vector permutation | | | 107704 x86/AVX512: use VMOVDDUP for broadcast to V2DF | | | 107705 x86: add Bk and Br to comment list B's sub-chars | | | 107706 x86: make better use of VBROADCASTSS / VPBROADCASTD | | | 107708 x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F | | | 107751 RISC-V: Add (u)int8_t to binop tests. | | | 107760 [v2] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32 | | | 107783 [v2] RISC-V: Save and restore FCSR in interrupt functions to avoid program errors. | | | 107796 Fix typo in 'libgomp.c/target-51.c' (was: [patch] OpenMP: Set default-device-var with OMP_TARGET_OFFLOAD=mandatory) | | | 107819 [v3] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32 | | | 107824 Remove MFWRAP_SPEC remnant | | | 107832 [RFC] main loop masked vectorization with --param vect-partial-vector-usage=1 | | | 107845 Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90' | | | 107848 RTL: Merge rtx_equal_p and hash_rtx functions with their callback variants | | | 107879 libgomp.texi: Document allocator + affininity env vars | | | 107880 RISC-V: Fix PR 110119 | | | 107882 libgomp testsuite: Don't handle 'lang_link_flags' | | | 107888 Align a 'OMP_TARGET_OFFLOAD=mandatory' diagnostic with others (was: Fix typo in 'libgomp.c/target-51.c' (was: [patch] OpenMP: Set default-device-var with OMP_TARGET_OFFLOAD=mandatory)) | | | 107892 RISC-V: Ensure vector args and return use function stack to pass [PR110119] | | | 107900 ??????: Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119] | | | 107911 [1/3] Inline vect_get_max_nscalars_per_iter | | | 107912 [2/3] Add loop_vinfo argument to vect_get_loop_mask | | | 107916 [3/3] AVX512 fully masked vectorization | | | 107918 [V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119] | | | 107955 [v2] c++: Accept elaborated-enum-base in system headers | | | 107957 middle-end: Move constant args folding of .UBSAN_CHECK_* and .*_OVERFLOW into fold-const-call.cc | | | 107958 middle-end, i386, v3: Pattern recognize add/subtract with carry [PR79173] | | | 107959 c++: tweak c++17 ctor/conversion tiebreaker [DR2327] | | | 107960 RISC-V: testsuite: Add vector_hw and zvfh_hw checks. | | | 108003 [1/2] Missed opportunity to use [SU]ABD | | | 108005 RISC-V: Add autovec FP binary operations. | | | 108010 RISC-V: Add autovec FP unary operations. | | | 108018 libgomp: Extend OMP_ALLOCATOR, add affinity env var doc (was: [Patch] libgomp.texi: Document allocator + affininity env vars) | | | 108022 [v2] Add MinGW option -mcrtdll= for choosing C RunTime DLL library | | | 108078 [COMMITED] MAINTAINERS: Add myself to write after approval | | | 108143 [ver,4] rs6000: Add builtins for IEEE 128-bit floating point values | | | 108146 [wwwdocs] Broken URL to README in st/cli-be project | | | 108155 [OG13,1/6] OpenMP: Handle loop transformation clauses in nested functions | | | 108156 [OG13,2/6] OpenMP: C support for imperfectly-nested loops | | | 108159 [OG13,3/6] OpenMP: C++ support for imperfectly-nested loops | | | 108157 [OG13,4/6] OpenMP: New c/c++ testcases for imperfectly-nested loops | | | 108158 [OG13,5/6] OpenMP: Refactor and tidy Fortran front-end code for loop transformations | | | 108160 [OG13,6/6] OpenMP: Fortran support for imperfectly nested loops | | | 108169 libstdc++-v3: do not duplicate some math functions when using newlib | | | 108171 [libstdc++,testsuite] xfail dbl from_chars for aarch64 rtems ldbl | | | 108172 [libstdc++,testsuite] expect zero entropy matching implementation | | | 108217 c++: provide #include hint for missing includes [PR110164] | | | 108221 [committed] RISC-V: Ensure vector args and return use function stack to pass [PR110119] | | | 108223 [v3] LoongArch: Avoid non-returning indirect jumps through $ra [PR110136] | | | 108231 [v2] RISC-V: Use merge approach to optimize vector permutation | | | 108235 [v3] RISC-V: Use merge approach to optimize vector permutation | | | 108260 Reimplement __gnu_cxx::__ops operators | | | 108263 [V1] RISC-V:Add float16 tuple type support | | | 108268 x86: correct and improve "*vec_dupv2di" | | | 108269 [pushed,v3] LoongArch: Change the default value of LARCH_CALL_RATIO to 6. | | | 108270 Fix tree-opt/110252: wrong code due to phiopt using flow sensitive info during match | | | 108312 [COMMITTED] ada: Cleanup analysis of iterated component association | | | 108316 [COMMITTED] ada: Fix aspect Linker_Section ignored on subprogram body | | | 108313 [COMMITTED] ada: Remove obsolete references for Build_Transient_Object_Statements | | | 108314 [COMMITTED] ada: Crash on C++ constructor of private type | | | 108317 [COMMITTED] ada: Accept aspect Always_Terminates without expression | | | 108315 [COMMITTED] ada: Fix inverted implementation of RM 8.4(10) clause for operators | | | 108320 [COMMITTED] ada: Remove Ttypes.Max_Unaligned_Field | | | 108318 [COMMITTED] ada: Fix minor issues in comments | | | 108322 [COMMITTED] ada: Fix missing error on function call returning incomplete view | | | 108321 [COMMITTED] ada: Reject aspect Always_Terminates on functions and generic functions | | | 108329 [COMMITTED] ada: Accept aspect Always_Terminates on entries | | | 108319 [COMMITTED] ada: Accept aspect Always_Terminates on packages | | | 108333 [COMMITTED] ada: Adjust comments in targparm.ads | | | 108331 [COMMITTED] ada: Adjust QNX Ada priorities to match QNX system priorities | | | 108326 [COMMITTED] ada: Fix missing finalization for aggregates nested in conditional expressions | | | 108323 [COMMITTED] ada: Add escape hatch to configurable run-time | | | 108335 [COMMITTED] ada: Remove dead code in Expand_Iterator_Loop_Over_Container | | | 108330 [COMMITTED] ada: Fix too small secondary stack allocation for returned aggregate | | | 108332 [COMMITTED] ada: Revert latest change to Find_Hook_Context | | | 108338 [COMMITTED] ada: Fix internal error on loop iterator filter with -gnatVa | | | 108334 [COMMITTED] ada: Fix too small secondary stack allocation for returned conversion | | | 108340 [COMMITTED] ada: Reject Loop_Entry inside prefix of Loop_Entry | | | 108342 [COMMITTED] ada: Make minor improvements to user's guide | | | 108343 [COMMITTED] ada: Fix wrong finalization for double subtype of bounded vector | | | 108341 [COMMITTED] ada: Fix wrong code for ACATS cd1c03i on Morello target | | | 108339 [COMMITTED] ada: Remove unused files | | | 108387 value-prof.cc: Correct edge prob calculation. | | | 108402 [V3] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs | | | 108451 [1/2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns | | | 108452 [2/2] arm: Add support for MVE Tail-Predicated Low Overhead Loops | | | 108458 gcc-ar: Remove code duplication. | | | 108482 [1/2] c++: implement __remove_pointer built-in trait | | | 108483 [2/2] libstdc++: use new built-in trait __remove_pointer | | | 108512 [V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs | | | 108580 [v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks. | | | 108581 [v2] RISC-V: Add autovec FP binary operations. | | | 108582 [v2] RISC-V: Add autovec FP unary operations. | | | 108583 Skip a number of C++ test cases for '-fno-exceptions' testing (was: Support in the GCC(/C++) test suites for '-fno-exceptions') | | | 108604 Skip a number of C++ "split files" test cases for '-fno-exceptions' testing (was: Skip a number of C++ test cases for '-fno-exceptions' testing (was: Support in the GCC(/C++) test suites for '-fno-exceptions')) | | | 108607 [ver,2] rs6000, fix vec_replace_unaligned builtin arguments | | | 108611 Skip a number of C++ 'g++.dg/tree-prof/' test cases for '-fno-exceptions' testing (was: Skip a number of C++ test cases for '-fno-exceptions' testing (was: Support in the GCC(/C++) test suites for '-fno-exceptions')) | | | 108624 PR tree-optimization/110266 - Check for integer only complex | | | 108664 [v2] Implement new RTL optimizations pass: fold-mem-offsets. | | | 108669 Add another testcase for PR 110266 | | | 108774 [pushed] c: add name hints to c_parser_declspecs [PR107583] | | | 108781 [1/2] Reimplement packuswb/packusdw with UNSPEC_US_TRUNCATE instead of original us_truncate. | | | 108782 [2/2] Refined 256/512-bit vpacksswb/vpackssdw patterns. | | | 108819 Add bfloat16_t support for riscv | | | 108830 [v2] x86: correct and improve "*vec_dupv2di" | | | 108831 [v2] x86: make VPTERNLOG* usable on less than 512-bit operands with just AVX512F | | | 108893 [v1] RISC-V: Bugfix for RVV integer reduction in ZVE32/64. | | | 108918 RISC-V: Fix PR 110264 | | | 108919 RISC-V: Fix VL operand bug in VSETVL PASS[PR110264] | | | 108922 [v2] RISC-V: Bugfix for RVV integer reduction in ZVE32/64. | | | 108923 Check SCALAR_INT_MODE_P in try_const_anchors | | | 108926 tree-optimization/110269 - restore missed condition folding | | | 108928 [V3,1/4] rs6000: build constant via li;rotldi | | | 108934 [2/2,v2] AVX512 fully masked vectorization | | | 108985 [V5] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs | | | 109031 [V6] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs | | | 109050 [v1] RISC-V: Fix one warning of maybe-uninitialized in riscv-vsetvl.cc | | | 109064 tree-optimization/110278 - uns < (typeof uns)(uns != 0) is always false | | | 109075 [v3] c++: Accept elaborated-enum-base with pedwarn | | | 109081 [contrib] validate_failures.py: Don't consider summary line in wrong place | | | 109089 tree-optimization/110243 - kill off IVOPTs split_offset | | | 109125 [v3] RISC-V: Add autovec FP binary operations. | | | 109126 [v3] RISC-V: Add autovec FP unary operations. | | | 109134 [v2] RISC-V: Implement vec_set and vec_extract. | | | 109135 [wwwdocs] gcc-14/changes.htm - Offloading: -lm/-lgfortran is autolinked | | | 109171 tree-ssa-math-opts: Fix up uaddc/usubc pattern matching [PR110271] | | | 109172 builtins: Add support for clang compatible __builtin_{add,sub}c{,l,ll} [PR79173] | | | 109192 [pushed,RA,PR110215] Ignore conflicts for some pseudos from insns throwing a final exception | | | 109218 [committed] libgomp: Fix OMP_TARGET_OFFLOAD=mandatory | | | 109223 [1/2] go: update usage of TARGET_AIX to TARGET_AIX_OS | | | 109224 [2/2] rust: update usage of TARGET_AIX to TARGET_AIX_OS | | | 109236 Regenerate some autotools generated files (Was: Re: [PATCH v3] configure: Implement --enable-host-pie) | | | 109244 OpenMP (C/C++): Keep pointer value of unmapped ptr with default mapping [PR110270] | | | 109245 ipa-sra: Disable candidates with no known callers (PR 110276) | | | 109250 [x86_64] Two minor tweaks to ix86_expand_move. | | | 109293 [ver,5] rs6000: Add builtins for IEEE 128-bit floating point values | | | 109333 libgo patch committed: Add benchmarks and examples to test list | | | 109439 [fortran] PR107900 Select type with intrinsic type inside associate causes ICE / Segmenation fault | | | 109504 [v1] RISC-V: Bugfix for RVV float reduction in ZVE32/64 | | | 109557 [V7] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs | | | 109566 [v2] RISC-V: Bugfix for RVV float reduction in ZVE32/64 | | | 109578 [1/2] xtensa: Remove TARGET_MEMORY_MOVE_COST hook | | | 109577 [2/2] xtensa: constantsynth: Add new 2-insns synthesis pattern | | | 109593 [x86] Standardize shift amount constants as QImode. | | | 109594 [x86] Add alternate representation for {and,or,xor}b %ah,%dh. | | | 109597 Improved SUBREG simplifications in simplify-rtx.cc's simplify_subreg. | | | 109599 [x86] Refactor new ix86_expand_carry to set the carry flag. | | | 109600 RISC-V: Add tuple vector mode psABI checking and simplify code | | | 109615 [RFC] Workaround LRA reload issue with SUBREGs in SET_DEST. | | | 109629 [v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 | +------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master fatal: refusing to merge unrelated histories + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series44845-patch109629 ++ git branch -a ++ grep 'series44845-patch109629$' + checkbranch= + checkbranchresult=null + '[' null = series44845-patch109629 ']' + git checkout -b series44845-patch109629 Switched to a new branch 'series44845-patch109629' ++ curl https://patchwork.plctlab.org/api/1.2/series/44845/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1402 100 1402 0 0 35050 0 --:--:-- --:--:-- --:--:-- 35050 + series_response='{"id":44845,"url":"https://patchwork.plctlab.org/api/1.2/series/44845/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=44845","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","date":"2023-06-18T15:13:29","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/44845/mbox/","cover_letter":null,"patches":[{"id":109629,"url":"https://patchwork.plctlab.org/api/1.2/patches/109629/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/","msgid":"<20230618151329.1814812-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-06-18T15:13:29","name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/"}]}' ++ echo '{"id":44845,"url":"https://patchwork.plctlab.org/api/1.2/series/44845/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=44845","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","date":"2023-06-18T15:13:29","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/44845/mbox/","cover_letter":null,"patches":[{"id":109629,"url":"https://patchwork.plctlab.org/api/1.2/patches/109629/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/","msgid":"<20230618151329.1814812-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-06-18T15:13:29","name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"109629,https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/"' + echo '"109629,https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"109629' ++ sed 's/"//g' + series_patch_id=109629 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++ git rev-parse HEAD + commitid_before=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 32584 100 32584 0 0 636k 0 --:--:-- --:--:-- --:--:-- 636k +++ bout='\''\'\'''\''Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 32584 100 32584 0 0 636k 0 --:--:-- --:--:-- --:--:-- 636k +++ bout='\''Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins18188284365570366251.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 32584 100 32584 0 0 636k 0 --:--:-- --:--:-- --:--:-- 636k +++ bout='\''Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins18188284365570366251.sh: line 154: ++: command not found ++ ++ declare -p berr /tmp/jenkins18188284365570366251.sh: line 155: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 32584 100 32584 0 0 636k 0 --:--:-- --:--:-- --:--:-- 636k +++ bout='\''Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 32584 100 32584 0 0 636k 0 --:--:-- --:--:-- --:--:-- 636k +++ bout='Applying: RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 error: sha1 information is lacking or useless (gcc/config/riscv/riscv-vector-builtins-bases.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Bugfix for RVV widenning reduction in ZVE32/64 When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/8425/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/8425/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/8425/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/109629/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 966 100 426 100 540 8693 11020 --:--:-- --:--:-- --:--:-- 19714 {"id":9771,"url":"https://patchwork.plctlab.org/api/patches/109629/checks/9771/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-06-18T15:16:58.240375","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/8425/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/109629/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":109629,"url":"https://patchwork.plctlab.org/api/1.2/patches/109629/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230618151329.1814812-1-pan2.li@intel.com>","list_archive_url":null,"date":"2023-06-18T15:13:29","name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"eee880dcd8b1c3c0f21d8caf5a9476744e07a867","submitter":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/people/1/","name":"Pan Li via Gcc-patches","email":"gcc-patches@gcc.gnu.org"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230618151329.1814812-1-pan2.li@intel.com/mbox/","series":[{"id":44845,"url":"https://patchwork.plctlab.org/api/1.2/series/44845/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=44845","date":"2023-06-18T15:13:29","name":"[v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","version":1,"mbox":"https://patchwork.plctlab.org/series/44845/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/109629/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/109629/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp2512860vqr;\n Sun, 18 Jun 2023 08:14:27 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n i5-20020a1709061cc500b00987a410ed03si1659556ejh.82.2023.06.18.08.14.26\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Sun, 18 Jun 2023 08:14:26 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id 54FD93858409\n\tfor ; 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a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;\n\ts=default; t=1687101265;\n\tbh=vXIxHmBhM/FkbfiIuExF4XyywT48+QlxFfZVVH0AoGo=;\n\th=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive:\n\t List-Post:List-Help:List-Subscribe:From:Reply-To:From;\n\tb=CbqTNKeyeugtvKTWA3DesxEdDIv8EPN5IWDT/c7ma0gjy1DyTWWh4VM/22uRu903D\n\t lAF4JeTBYwqy8e55oyaLl65rBeijNvs/mp9dNXspPnPt4CEoZmdAwFn2XWEtoS2/uJ\n\t gQODnvqP+a6kZGO5FdNvB+iDDvaSurjOYt4k6okM=","X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 54EC63858D28","X-IronPort-AV":["E=McAfee;i=\"6600,9927,10745\"; a=\"388434509\"","E=Sophos;i=\"6.00,252,1681196400\"; d=\"scan'208\";a=\"388434509\"","E=McAfee;i=\"6600,9927,10745\"; a=\"713422157\"","E=Sophos;i=\"6.00,252,1681196400\"; d=\"scan'208\";a=\"713422157\""],"X-ExtLoop1":"1","To":"gcc-patches@gcc.gnu.org","Cc":"juzhe.zhong@rivai.ai, rdapp.gcc@gmail.com, jeffreyalaw@gmail.com,\n pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com","Subject":"[PATCH v1] RISC-V: Bugfix for RVV widenning reduction in ZVE32/64","Date":"Sun, 18 Jun 2023 23:13:29 +0800","Message-Id":"<20230618151329.1814812-1-pan2.li@intel.com>","X-Mailer":"git-send-email 2.34.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-Spam-Status":"No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH,\n DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0,\n KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL,\n SPF_HELO_NONE,\n SPF_NONE, TXREP,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Pan Li via Gcc-patches ","Reply-To":"pan2.li@intel.com","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1769053897834503277?=","X-GMAIL-MSGID":"=?utf-8?q?1769053897834503277?="},"content":"From: Pan Li \n\nThe rvv widdening reduction has 3 different patterns for zve128+, zve64\nand zve32. They take the same iterator with different attributions.\nHowever, we need the generated function code_for_reduc (code, mode1, mode2).\nThe implementation of code_for_reduc may look like below.\n\ncode_for_reduc (code, mode1, mode2)\n{\n if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)\n return CODE_FOR_pred_reduc_maxvnx1hfvnx16hf; // ZVE128+\n\n if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)\n return CODE_FOR_pred_reduc_maxvnx1hfvnx8hf; // ZVE64\n\n if (code == max && mode1 == VNx1HF && mode2 == VNx1HF)\n return CODE_FOR_pred_reduc_maxvnx1hfvnx4hf; // ZVE32\n}\n\nThus there will be a problem here. For example zve32, we will have\ncode_for_reduc (max, VNx1HF, VNx1HF) which will return the code of\nthe ZVE128+ instead of the ZVE32 logically.\n\nThis patch will merge the 3 patterns into pattern, and pass both the\ninput_vector and the ret_vector of code_for_reduc. For example, ZVE32\nwill be code_for_reduc (max, VNx1HF, VNx2HF), then the correct code of ZVE32\nwill be returned as expectation.\n\nPlease note both GCC 13 and 14 are impacted by this issue.\n\nSigned-off-by: Pan Li \nCo-Authored by: Juzhe-Zhong \n\n\tPR 110299\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vector-builtins-bases.cc: Adjust expand for\n\tmodes.\n\t* config/riscv/vector-iterators.md: Remove VWLMUL1, VWLMUL1_ZVE64,\n\tVWLMUL1_ZVE32.\n\t* config/riscv/vector.md\n\t(@pred_widen_reduc_plus): Removed.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): New pattern.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\t(@pred_widen_reduc_plus): Ditto.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/pr110299-1.c: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-1.h: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-2.c: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-2.h: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-3.c: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-3.h: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-4.c: New test.\n\t* gcc.target/riscv/rvv/base/pr110299-4.h: New test.\n---\n .../riscv/riscv-vector-builtins-bases.cc | 16 +-\n gcc/config/riscv/vector-iterators.md | 62 -----\n gcc/config/riscv/vector.md | 243 ++++++++++++------\n .../gcc.target/riscv/rvv/base/pr110299-1.c | 7 +\n .../gcc.target/riscv/rvv/base/pr110299-1.h | 9 +\n .../gcc.target/riscv/rvv/base/pr110299-2.c | 8 +\n .../gcc.target/riscv/rvv/base/pr110299-2.h | 17 ++\n .../gcc.target/riscv/rvv/base/pr110299-3.c | 7 +\n .../gcc.target/riscv/rvv/base/pr110299-3.h | 17 ++\n .../gcc.target/riscv/rvv/base/pr110299-4.c | 8 +\n .../gcc.target/riscv/rvv/base/pr110299-4.h | 17 ++\n 11 files changed, 253 insertions(+), 158 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h","diff":"diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc\nindex 27545113996..c6c53dc13a5 100644\n--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc\n@@ -1396,16 +1396,8 @@ public:\n \n rtx expand (function_expander &e) const override\n {\n- machine_mode mode = e.vector_mode ();\n- machine_mode ret_mode = e.ret_mode ();\n-\n- /* TODO: we will use ret_mode after all types of PR110265 are addressed. */\n- if (GET_MODE_INNER (mode) != GET_MODE_INNER (ret_mode))\n- return e.use_exact_insn (\n-\tcode_for_pred_reduc (CODE, e.vector_mode (), e.vector_mode ()));\n- else\n- return e.use_exact_insn (\n-\tcode_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));\n+ return e.use_exact_insn (\n+ code_for_pred_reduc (CODE, e.vector_mode (), e.ret_mode ()));\n }\n };\n \n@@ -1420,7 +1412,7 @@ public:\n {\n return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,\n \t\t\t\t\t\t\t e.vector_mode (),\n-\t\t\t\t\t\t\t e.vector_mode ()));\n+\t\t\t\t\t\t\t e.ret_mode ()));\n }\n };\n \n@@ -1449,7 +1441,7 @@ public:\n {\n return e.use_exact_insn (code_for_pred_widen_reduc_plus (UNSPEC,\n \t\t\t\t\t\t\t e.vector_mode (),\n-\t\t\t\t\t\t\t e.vector_mode ()));\n+\t\t\t\t\t\t\t e.ret_mode ()));\n }\n };\n \ndiff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md\nindex 6169116482a..e4c6c1bb135 100644\n--- a/gcc/config/riscv/vector-iterators.md\n+++ b/gcc/config/riscv/vector-iterators.md\n@@ -1392,68 +1392,6 @@ (define_mode_attr VNCONVERT [\n (VNx1DF \"VNx1SI\") (VNx2DF \"VNx2SI\") (VNx4DF \"VNx4SI\") (VNx8DF \"VNx8SI\") (VNx16DF \"VNx16SI\")\n ])\n \n-(define_mode_attr VWLMUL1 [\n- (VNx1QI \"VNx8HI\") (VNx2QI \"VNx8HI\") (VNx4QI \"VNx8HI\")\n- (VNx8QI \"VNx8HI\") (VNx16QI \"VNx8HI\") (VNx32QI \"VNx8HI\") (VNx64QI \"VNx8HI\") (VNx128QI \"VNx8HI\")\n- (VNx1HI \"VNx4SI\") (VNx2HI \"VNx4SI\") (VNx4HI \"VNx4SI\")\n- (VNx8HI \"VNx4SI\") (VNx16HI \"VNx4SI\") (VNx32HI \"VNx4SI\") (VNx64HI \"VNx4SI\")\n- (VNx1SI \"VNx2DI\") (VNx2SI \"VNx2DI\") (VNx4SI \"VNx2DI\")\n- (VNx8SI \"VNx2DI\") (VNx16SI \"VNx2DI\") (VNx32SI \"VNx2DI\")\n- (VNx1HF \"VNx4SF\") (VNx2HF \"VNx4SF\") (VNx4HF \"VNx4SF\") (VNx8HF \"VNx4SF\") (VNx16HF \"VNx4SF\") (VNx32HF \"VNx4SF\") (VNx64HF \"VNx4SF\")\n- (VNx1SF \"VNx2DF\") (VNx2SF \"VNx2DF\")\n- (VNx4SF \"VNx2DF\") (VNx8SF \"VNx2DF\") (VNx16SF \"VNx2DF\") (VNx32SF \"VNx2DF\")\n-])\n-\n-(define_mode_attr VWLMUL1_ZVE64 [\n- (VNx1QI \"VNx4HI\") (VNx2QI \"VNx4HI\") (VNx4QI \"VNx4HI\")\n- (VNx8QI \"VNx4HI\") (VNx16QI \"VNx4HI\") (VNx32QI \"VNx4HI\") (VNx64QI \"VNx4HI\")\n- (VNx1HI \"VNx2SI\") (VNx2HI \"VNx2SI\") (VNx4HI \"VNx2SI\")\n- (VNx8HI \"VNx2SI\") (VNx16HI \"VNx2SI\") (VNx32HI \"VNx2SI\")\n- (VNx1SI \"VNx1DI\") (VNx2SI \"VNx1DI\") (VNx4SI \"VNx1DI\")\n- (VNx8SI \"VNx1DI\") (VNx16SI \"VNx1DI\")\n- (VNx1HF \"VNx2SF\") (VNx2HF \"VNx2SF\") (VNx4HF \"VNx2SF\") (VNx8HF \"VNx2SF\") (VNx16HF \"VNx2SF\") (VNx32HF \"VNx2SF\")\n- (VNx1SF \"VNx1DF\") (VNx2SF \"VNx1DF\")\n- (VNx4SF \"VNx1DF\") (VNx8SF \"VNx1DF\") (VNx16SF \"VNx1DF\")\n-])\n-\n-(define_mode_attr VWLMUL1_ZVE32 [\n- (VNx1QI \"VNx2HI\") (VNx2QI \"VNx2HI\") (VNx4QI \"VNx2HI\")\n- (VNx8QI \"VNx2HI\") (VNx16QI \"VNx2HI\") (VNx32QI \"VNx2HI\")\n- (VNx1HI \"VNx1SI\") (VNx2HI \"VNx1SI\") (VNx4HI \"VNx1SI\")\n- (VNx8HI \"VNx1SI\") (VNx16HI \"VNx1SI\")\n-])\n-\n-(define_mode_attr vwlmul1 [\n- (VNx1QI \"vnx8hi\") (VNx2QI \"vnx8hi\") (VNx4QI \"vnx8hi\")\n- (VNx8QI \"vnx8hi\") (VNx16QI \"vnx8hi\") (VNx32QI \"vnx8hi\") (VNx64QI \"vnx8hi\") (VNx128QI \"vnx8hi\")\n- (VNx1HI \"vnx4si\") (VNx2HI \"vnx4si\") (VNx4HI \"vnx4si\")\n- (VNx8HI \"vnx4si\") (VNx16HI \"vnx4si\") (VNx32HI \"vnx4si\") (VNx64HI \"vnx4si\")\n- (VNx1SI \"vnx2di\") (VNx2SI \"vnx2di\") (VNx4SI \"vnx2di\")\n- (VNx8SI \"vnx2di\") (VNx16SI \"vnx2di\") (VNx32SI \"vnx2di\")\n- (VNx1HF \"vnx4sf\") (VNx2HF \"vnx4sf\") (VNx4HF \"vnx4sf\") (VNx8HF \"vnx4sf\") (VNx16HF \"vnx4sf\") (VNx32HF \"vnx4sf\") (VNx64HF \"vnx4sf\")\n- (VNx1SF \"vnx2df\") (VNx2SF \"vnx2df\")\n- (VNx4SF \"vnx2df\") (VNx8SF \"vnx2df\") (VNx16SF \"vnx2df\") (VNx32SF \"vnx2df\")\n-])\n-\n-(define_mode_attr vwlmul1_zve64 [\n- (VNx1QI \"vnx4hi\") (VNx2QI \"vnx4hi\") (VNx4QI \"vnx4hi\")\n- (VNx8QI \"vnx4hi\") (VNx16QI \"vnx4hi\") (VNx32QI \"vnx4hi\") (VNx64QI \"vnx4hi\")\n- (VNx1HI \"vnx2si\") (VNx2HI \"vnx2si\") (VNx4HI \"vnx2si\")\n- (VNx8HI \"vnx2si\") (VNx16HI \"vnx2si\") (VNx32HI \"vnx2si\")\n- (VNx1SI \"vnx1di\") (VNx2SI \"vnx1di\") (VNx4SI \"vnx1di\")\n- (VNx8SI \"vnx1di\") (VNx16SI \"vnx1di\")\n- (VNx1HF \"vnx2sf\") (VNx2HF \"vnx2sf\") (VNx4HF \"vnx2sf\") (VNx8HF \"vnx2sf\") (VNx16HF \"vnx2sf\") (VNx32HF \"vnx2sf\")\n- (VNx1SF \"vnx1df\") (VNx2SF \"vnx1df\")\n- (VNx4SF \"vnx1df\") (VNx8SF \"vnx1df\") (VNx16SF \"vnx1df\")\n-])\n-\n-(define_mode_attr vwlmul1_zve32 [\n- (VNx1QI \"vnx2hi\") (VNx2QI \"vnx2hi\") (VNx4QI \"vnx2hi\")\n- (VNx8QI \"vnx2hi\") (VNx16QI \"vnx2hi\") (VNx32QI \"vnx2hi\")\n- (VNx1HI \"vnx1si\") (VNx2HI \"vnx1si\") (VNx4HI \"vnx1si\")\n- (VNx8HI \"vnx1si\") (VNx16HI \"vnx1si\")\n-])\n-\n (define_mode_attr VDEMOTE [\n (VNx1DI \"VNx2SI\") (VNx2DI \"VNx4SI\")\n (VNx4DI \"VNx8SI\") (VNx8DI \"VNx16SI\") (VNx16DI \"VNx32SI\")\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex efce992a012..884e7435cc2 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -7407,60 +7407,101 @@ (define_insn \"@pred_reduc_\"\n ]\n )\n \n-(define_insn \"@pred_widen_reduc_plus\"\n- [(set (match_operand: 0 \"register_operand\" \"=&vr, &vr\")\n-\t(unspec:\n-\t [(unspec:\n-\t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n-\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n-\t (match_operand 6 \"const_int_operand\" \" i, i\")\n-\t (match_operand 7 \"const_int_operand\" \" i, i\")\n+;; Integer Reduction Widen for QI, HI = QI op HI\n+(define_insn \"@pred_widen_reduc_plus\"\n+ [\n+ (set\n+ (match_operand:VHI_LMUL1 0 \"register_operand\" \"=&vr,&vr\")\n+ (unspec:VHI_LMUL1\n+\t[\n+\t (unspec:\n+\t [\n+\t (match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n+\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n+\t (match_operand 6 \"const_int_operand\" \" i, i\")\n+\t (match_operand 7 \"const_int_operand\" \" i, i\")\n \t (reg:SI VL_REGNUM)\n-\t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VWI 3 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 4 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 2 \"vector_merge_operand\" \" vu, 0\")] WREDUC))]\n- \"TARGET_VECTOR && TARGET_MIN_VLEN >= 128\"\n+\t (reg:SI VTYPE_REGNUM)\n+\t ] UNSPEC_VPREDICATE\n+\t )\n+\t (match_operand:VQI 3 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VHI_LMUL1 4 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VHI_LMUL1 2 \"vector_merge_operand\" \" vu, 0\")\n+\t] WREDUC\n+ )\n+ )\n+ ]\n+ \"TARGET_VECTOR\"\n \"vwredsum.vs\\t%0,%3,%4%p1\"\n- [(set_attr \"type\" \"viwred\")\n- (set_attr \"mode\" \"\")])\n+ [\n+ (set_attr \"type\" \"viwred\")\n+ (set_attr \"mode\" \"\")\n+ ]\n+)\n \n-(define_insn \"@pred_widen_reduc_plus\"\n- [(set (match_operand: 0 \"register_operand\" \"=&vr, &vr\")\n-\t(unspec:\n-\t [(unspec:\n-\t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n-\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n-\t (match_operand 6 \"const_int_operand\" \" i, i\")\n-\t (match_operand 7 \"const_int_operand\" \" i, i\")\n+;; Integer Reduction Widen for HI, SI = HI op SI\n+(define_insn \"@pred_widen_reduc_plus\"\n+ [\n+ (set\n+ (match_operand:VSI_LMUL1 0 \"register_operand\" \"=&vr,&vr\")\n+ (unspec:VSI_LMUL1\n+\t[\n+\t (unspec:\n+\t [\n+\t (match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n+\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n+\t (match_operand 6 \"const_int_operand\" \" i, i\")\n+\t (match_operand 7 \"const_int_operand\" \" i, i\")\n \t (reg:SI VL_REGNUM)\n-\t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VWI_ZVE64 3 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 4 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 2 \"vector_merge_operand\" \" vu, 0\")] WREDUC))]\n- \"TARGET_VECTOR && TARGET_MIN_VLEN == 64\"\n+\t (reg:SI VTYPE_REGNUM)\n+\t ] UNSPEC_VPREDICATE\n+\t )\n+\t (match_operand:VHI 3 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VSI_LMUL1 4 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VSI_LMUL1 2 \"vector_merge_operand\" \" vu, 0\")\n+\t] WREDUC\n+ )\n+ )\n+ ]\n+ \"TARGET_VECTOR\"\n \"vwredsum.vs\\t%0,%3,%4%p1\"\n- [(set_attr \"type\" \"viwred\")\n- (set_attr \"mode\" \"\")])\n-\n+ [\n+ (set_attr \"type\" \"viwred\")\n+ (set_attr \"mode\" \"\")\n+ ]\n+)\n \n-(define_insn \"@pred_widen_reduc_plus\"\n- [(set (match_operand: 0 \"register_operand\" \"=&vr, &vr\")\n-\t(unspec:\n-\t [(unspec:\n-\t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n-\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n-\t (match_operand 6 \"const_int_operand\" \" i, i\")\n-\t (match_operand 7 \"const_int_operand\" \" i, i\")\n+;; Integer Reduction Widen for SI, DI = SI op DI\n+(define_insn \"@pred_widen_reduc_plus\"\n+ [\n+ (set\n+ (match_operand:VDI_LMUL1 0 \"register_operand\" \"=&vr,&vr\")\n+ (unspec:VDI_LMUL1\n+\t[\n+\t (unspec:\n+\t [\n+\t (match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n+\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n+\t (match_operand 6 \"const_int_operand\" \" i, i\")\n+\t (match_operand 7 \"const_int_operand\" \" i, i\")\n \t (reg:SI VL_REGNUM)\n-\t (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VWI_ZVE32 3 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 4 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 2 \"vector_merge_operand\" \" vu, 0\")] WREDUC))]\n- \"TARGET_VECTOR && TARGET_MIN_VLEN == 32\"\n+\t (reg:SI VTYPE_REGNUM)\n+\t ] UNSPEC_VPREDICATE\n+\t )\n+\t (match_operand:VSI 3 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VDI_LMUL1 4 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VDI_LMUL1 2 \"vector_merge_operand\" \" vu, 0\")\n+\t] WREDUC\n+ )\n+ )\n+ ]\n+ \"TARGET_VECTOR\"\n \"vwredsum.vs\\t%0,%3,%4%p1\"\n- [(set_attr \"type\" \"viwred\")\n- (set_attr \"mode\" \"\")])\n+ [\n+ (set_attr \"type\" \"viwred\")\n+ (set_attr \"mode\" \"\")\n+ ]\n+)\n \n ;; Float Reduction for HF\n (define_insn \"@pred_reduc_\"\n@@ -7714,47 +7755,81 @@ (define_insn \"@pred_reduc_plus\"\n ]\n )\n \n-(define_insn \"@pred_widen_reduc_plus\"\n- [(set (match_operand: 0 \"register_operand\" \"=&vr, &vr\")\n-\t(unspec:\n-\t [(unspec:\n-\t [(unspec:\n-\t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n-\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n-\t (match_operand 6 \"const_int_operand\" \" i, i\")\n-\t (match_operand 7 \"const_int_operand\" \" i, i\")\n-\t (match_operand 8 \"const_int_operand\" \" i, i\")\n-\t (reg:SI VL_REGNUM)\n-\t (reg:SI VTYPE_REGNUM)\n-\t (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VWF 3 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 4 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 2 \"vector_merge_operand\" \" vu, 0\")] UNSPEC_WREDUC_SUM)] ORDER))]\n- \"TARGET_VECTOR && TARGET_MIN_VLEN >= 128\"\n+;; Float Widen Reduction for HF, aka SF = HF op SF\n+(define_insn \"@pred_widen_reduc_plus\"\n+ [\n+ (set\n+ (match_operand:VSF_LMUL1 0 \"register_operand\" \"=&vr, &vr\")\n+ (unspec:VSF_LMUL1\n+\t[\n+\t (unspec:VSF_LMUL1\n+\t [\n+\t (unspec:\n+\t\t[\n+\t\t (match_operand: 1 \"vector_merge_operand\" \"vmWc1,vmWc1\")\n+\t\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n+\t\t (match_operand 6 \"const_int_operand\" \" i, i\")\n+\t\t (match_operand 7 \"const_int_operand\" \" i, i\")\n+\t\t (match_operand 8 \"const_int_operand\" \" i, i\")\n+\t\t (reg:SI VL_REGNUM)\n+\t\t (reg:SI VTYPE_REGNUM)\n+\t\t (reg:SI FRM_REGNUM)\n+\t\t] UNSPEC_VPREDICATE\n+\t )\n+\t (match_operand:VHF 3 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VSF_LMUL1 4 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VSF_LMUL1 2 \"vector_merge_operand\" \" vu, 0\")\n+\t ] UNSPEC_WREDUC_SUM\n+\t )\n+\t] ORDER\n+ )\n+ )\n+ ]\n+ \"TARGET_VECTOR\"\n \"vfwredsum.vs\\t%0,%3,%4%p1\"\n- [(set_attr \"type\" \"vfwred\")\n- (set_attr \"mode\" \"\")])\n+ [\n+ (set_attr \"type\" \"vfwred\")\n+ (set_attr \"mode\" \"\")\n+ ]\n+)\n \n-(define_insn \"@pred_widen_reduc_plus\"\n- [(set (match_operand: 0 \"register_operand\" \"=&vr, &vr\")\n-\t(unspec:\n-\t [(unspec:\n-\t [(unspec:\n-\t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n-\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n-\t (match_operand 6 \"const_int_operand\" \" i, i\")\n-\t (match_operand 7 \"const_int_operand\" \" i, i\")\n-\t (match_operand 8 \"const_int_operand\" \" i, i\")\n-\t (reg:SI VL_REGNUM)\n-\t (reg:SI VTYPE_REGNUM)\n-\t (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)\n-\t (match_operand:VWF_ZVE64 3 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 4 \"register_operand\" \" vr, vr\")\n-\t (match_operand: 2 \"vector_merge_operand\" \" vu, 0\")] UNSPEC_WREDUC_SUM)] ORDER))]\n- \"TARGET_VECTOR && TARGET_MIN_VLEN == 64\"\n+;; Float Widen Reduction for SF, aka DF = SF * DF\n+(define_insn \"@pred_widen_reduc_plus\"\n+ [\n+ (set\n+ (match_operand:VDF_LMUL1 0 \"register_operand\" \"=&vr, &vr\")\n+ (unspec:VDF_LMUL1\n+\t[\n+\t (unspec:VDF_LMUL1\n+\t [\n+\t (unspec:\n+\t\t[\n+\t\t (match_operand: 1 \"vector_merge_operand\" \"vmWc1,vmWc1\")\n+\t\t (match_operand 5 \"vector_length_operand\" \" rK, rK\")\n+\t\t (match_operand 6 \"const_int_operand\" \" i, i\")\n+\t\t (match_operand 7 \"const_int_operand\" \" i, i\")\n+\t\t (match_operand 8 \"const_int_operand\" \" i, i\")\n+\t\t (reg:SI VL_REGNUM)\n+\t\t (reg:SI VTYPE_REGNUM)\n+\t\t (reg:SI FRM_REGNUM)\n+\t\t] UNSPEC_VPREDICATE\n+\t )\n+\t (match_operand:VSF 3 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VDF_LMUL1 4 \"register_operand\" \" vr, vr\")\n+\t (match_operand:VDF_LMUL1 2 \"vector_merge_operand\" \" vu, 0\")\n+\t ] UNSPEC_WREDUC_SUM\n+\t )\n+\t] ORDER\n+ )\n+ )\n+ ]\n+ \"TARGET_VECTOR\"\n \"vfwredsum.vs\\t%0,%3,%4%p1\"\n- [(set_attr \"type\" \"vfwred\")\n- (set_attr \"mode\" \"\")])\n+ [\n+ (set_attr \"type\" \"vfwred\")\n+ (set_attr \"mode\" \"\")\n+ ]\n+)\n \n ;; -------------------------------------------------------------------------------\n ;; ---- Predicated permutation operations\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c\nnew file mode 100644\nindex 00000000000..d83eea925a7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.c\n@@ -0,0 +1,7 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gc_zve32f_zvfh -mabi=ilp32f -O3 -Wno-psabi\" } */\n+\n+#include \"pr110299-1.h\"\n+\n+/* { dg-final { scan-assembler-times {vfwredosum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+,\\s*v0.t} 1 } } */\n+/* { dg-final { scan-assembler-times {vfwredusum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+,\\s*v0.t} 1 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h\nnew file mode 100644\nindex 00000000000..a8ea018ccc9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-1.h\n@@ -0,0 +1,9 @@\n+#include \"riscv_vector.h\"\n+\n+vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {\n+ return __riscv_vfwredosum_vs_f16m8_f32m1(vector, scalar, vl);\n+}\n+\n+vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1(vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) {\n+ return __riscv_vfwredusum_vs_f16m8_f32m1(vector, scalar, vl);\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c\nnew file mode 100644\nindex 00000000000..cdcde1b89a4\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.c\n@@ -0,0 +1,8 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gc_zve64d_zvfh -mabi=ilp32d -O3 -Wno-psabi\" } */\n+\n+#include \"pr110299-1.h\"\n+#include \"pr110299-2.h\"\n+\n+/* { dg-final { scan-assembler-times {vfwredosum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+,\\s*v0.t} 3 } } */\n+/* { dg-final { scan-assembler-times {vfwredusum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+,\\s*v0.t} 3 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h\nnew file mode 100644\nindex 00000000000..51d4d4470d8\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-2.h\n@@ -0,0 +1,17 @@\n+#include \"riscv_vector.h\"\n+\n+vfloat32m1_t test_vfwredosum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {\n+ return __riscv_vfwredosum_vs_f16mf4_f32m1(vector, scalar, vl);\n+}\n+\n+vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1(vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) {\n+ return __riscv_vfwredusum_vs_f16mf4_f32m1(vector, scalar, vl);\n+}\n+\n+vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {\n+ return __riscv_vfwredusum_vs_f32m8_f64m1(vector, scalar, vl);\n+}\n+\n+vfloat64m1_t test_vfwredosum_vs_f32m8_f64m1(vfloat32m8_t vector, vfloat64m1_t scalar, size_t vl) {\n+ return __riscv_vfwredosum_vs_f32m8_f64m1(vector, scalar, vl);\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299 100 35986 100 35836 100 150 514k 2205 --:--:-- --:--:-- --:--:-- 509k -3.c\nnew file mode 100644\nindex 00000000000..0f84c17d6f1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.c\n@@ -0,0 +1,7 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gc_zve32f -mabi=ilp32f -O3 -Wno-psabi\" } */\n+\n+#include \"pr110299-3.h\"\n+\n+/* { dg-final { scan-assembler-times {vwredsum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+} 2 } } */\n+/* { dg-final { scan-assembler-times {vwredsumu\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+} 2 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h\nnew file mode 100644\nindex 00000000000..3416196b8cc\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-3.h\n@@ -0,0 +1,17 @@\n+#include \"riscv_vector.h\"\n+\n+vint16m1_t test_vwredsum_vs_i8mf4_i16m1(vint8mf4_t vector, vint16m1_t scalar, size_t vl) {\n+ return __riscv_vwredsum_vs_i8mf4_i16m1(vector, scalar, vl);\n+}\n+\n+vint32m1_t test_vwredsum_vs_i16m8_i32m1(vint16m8_t vector, vint32m1_t scalar, size_t vl) {\n+ return __riscv_vwredsum_vs_i16m8_i32m1(vector, scalar, vl);\n+}\n+\n+vuint16m1_t test_vwredsumu_vs_u8mf4_u16m1(vuint8mf4_t vector, vuint16m1_t scalar, size_t vl) {\n+ return __riscv_vwredsumu_vs_u8mf4_u16m1(vector, scalar, vl);\n+}\n+\n+vuint32m1_t test_vwredsumu_vs_u16m8_u32m1(vuint16m8_t vector, vuint32m1_t scalar, size_t vl) {\n+ return __riscv_vwredsumu_vs_u16m8_u32m1(vector, scalar, vl);\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c\nnew file mode 100644\nindex 00000000000..8297cd62f65\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.c\n@@ -0,0 +1,8 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gc_zve64d -mabi=ilp32d -O3 -Wno-psabi\" } */\n+\n+#include \"pr110299-3.h\"\n+#include \"pr110299-4.h\"\n+\n+/* { dg-final { scan-assembler-times {vwredsum\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+} 4 } } */\n+/* { dg-final { scan-assembler-times {vwredsumu\\.vs\\s+v[0-9]+,\\s*v[0-9]+,\\s*v[0-9]+} 4 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h\nnew file mode 100644\nindex 00000000000..b4f7d403fe3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110299-4.h\n@@ -0,0 +1,17 @@\n+#include \"riscv_vector.h\"\n+\n+vint16m1_t test_vwredsum_vs_i8mf8_i16m1(vint8mf8_t vector, vint16m1_t scalar, size_t vl) {\n+ return __riscv_vwredsum_vs_i8mf8_i16m1(vector, scalar, vl);\n+}\n+\n+vint64m1_t test_vwredsum_vs_i32m8_i64m1(vint32m8_t vector, vint64m1_t scalar, size_t vl) {\n+ return __riscv_vwredsum_vs_i32m8_i64m1(vector, scalar, vl);\n+}\n+\n+vuint16m1_t test_vwredsumu_vs_u8mf8_u16m1(vuint8mf8_t vector, vuint16m1_t scalar, size_t vl) {\n+ return __riscv_vwredsumu_vs_u8mf8_u16m1(vector, scalar, vl);\n+}\n+\n+vuint64m1_t test_vwredsumu_vs_u32m8_u64m1(vuint32m8_t vector, vuint64m1_t scalar, size_t vl) {\n+ return __riscv_vwredsumu_vs_u32m8_u64m1(vector, scalar, vl);\n+}\n","prefixes":["v1"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE