Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 Commit message: "RISC-V: Reorganize binary autovec testcases" > git rev-list --no-walk c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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gcc-patch_2023-01 gcc-patch_2023-02 gcc-patch_2023-03 gcc-patch_2023-04 gcc-patch_2023-05 gcc-patch_2023-06 =~ 2023-06 ]] ++ jq -rc --arg bundle_name gcc-patch_2023-06 '.[] | select(.name==$bundle_name) | (.id|tostring)' ++ echo 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|------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------| | ID | 24 | | Name | gcc-patch_2023-06 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-06/ | | Owner | patchwork-bot | | Project | gcc-patch | | Public | True | | Patches | 101534 [1/3] testsuite: Unbork multilib testing on RISC-V (and any target really) | | | 101535 [2/3] RISC-V: Add missing torture-init and torture-finish for rvv.exp | | | 101536 [3/3] testsuite: print any leaking torture options for debugging | | | 101552 Move std::search into algobase.h | | | 101560 [1/3] testsuite: move handle-multiline-outputs to before check for blank lines | | | 101562 [2/3] diagnostics: add support for "text art" diagrams | | | 101561 [3/3] analyzer: add text-art visualizations of out-of-bounds accesses [PR106626] | | | 101569 OpenMP/Fortran: Permit pure directives inside PURE | | | 101571 [committed] libstdc++: Fix configure test for 32-bit targets | | | 101575 [committed] libstdc++: Fix build for targets without _Float128 [PR109921] | | | 101582 [committed] libstdc++: Express std::vector's size() <= capacity() invariant in code | | | 101583 [committed] libstdc++: Stop using _GLIBCXX_USE_C99_MATH_TR1 in | | | 101584 [committed] libstdc++: Add separate autoconf macro for std::float_t and std::double_t [PR109818] | | | 101653 [V2] RISC-V: Support RVV permutation auto-vectorization | | | 101677 libstdc++: optimize EH phase 2 | | | 101686 [pushed] c++: make -fpermissive avoid -Werror=narrowing | | | 101690 doc: improve docs for -pedantic{,-errors} | | | 101693 RISC-V: Add vwadd.wv/vwsub.wv auto-vectorization lowering optimization | | | 101701 [v5] MIPS: Add speculation_barrier support | | | 101702 [V3] VECT: Change flow of decrement IV | | | 101704 PATCH v5 4/4] ree: Improve ree pass for rs6000 target using defined ABI interfaces. | | | 101743 [2/3,v3] xtensa: Add 'adddi3' and 'subdi3' insn patterns | | | 101786 RISC-V: Introduce vfloat16m{f}*_t and their machine mode. | | | 101787 [v5] tree-ssa-sink: Improve code sinking pass | | | 101791 RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations | | | 101796 Don't try bswap + rotate when TYPE_PRECISION(n->type) > n->range. | | | 101801 [V2] RISC-V: Add pseudo vwmul.wv pattern to enhance vwmul.vv instruction optimizations | | | 101805 [committed] libstdc++: Fix condition for supported SIMD types on ARMv8 | | | 101874 doc: Fix description of x86 -m32 option [PR109954] | | | 101902 RISC-V: Add test for vfloat16*_t (non tuple) types | | | 101964 [COMMITTED] cse: Change return type of predicate functions from int to bool | | | 101974 [1/2] c++: refine dependent_alias_template_spec_p [PR90679] | | | 101975 [2/2] c++: partial ordering and dep alias tmpl specs [PR90679] | | | 102002 [committed] libstdc++: Document removal of implicit allocator rebinding extensions | | | 102005 [committed] libstdc++: Fix code size regressions in std::vector [PR110060] | | | 102006 [committed] libstdc++: Do not use std::expected::value() in monadic ops (LWG 3938) | | | 102020 [fortran] PR87477 - [meta-bug] [F03] issues concerning the ASSOCIATE statement | | | 102062 [committed] libstdc++: Fix PSTL test that fails in C++20 | | | 102065 libstdc++: Use AS_IF in configure.ac | | | 102070 inline: improve internal function costs | | | 102073 gimple-range: implement widen plus range | | | 102141 Fortran: force error on bad KIND specifier [PR88552] | | | 102161 [Committed] testsuite: Unbork multilib setups using -march flags (RISC-V) | | | 102162 [Committed] testsuite: print any leaking torture options for debugging | | | 102163 rs6000: Fix arguments for __builtin_altivec_tr_stxvrwx, __builtin_altivec_tr_stxvrhx | | | 102171 [RFC] range-op restructuring | | | 102205 c++: fix up caching of level lowered ttps | | | 102232 RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102233 rs6000: Fix expected counts powerpc/p9-vec-length-full | | | 102236 RISC-V: Add __RISCV_ prefix to VXRM and FRM enum | | | 102248 i386: Add missing vector truncate patterns [PR92658]. | | | 102249 [vect] Use intermiediate integer type for float_expr/fix_trunc_expr when direct optab is not existed. | | | 102262 [RFA] c++: make initializer_list array static again [PR110070] | | | 102277 RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102278 [V2] RISC-V: Add _mu C++ overloaded intrinsics for load && viota && vid | | | 102280 [COMMITTED] MAINTAINERS: Add myself as MIPS port maintainer | | | 102283 [RFA] varasm: check float size | | | 102287 RISC-V: Fix warning in predicated.md | | | 102300 RISC-V: Remove unnecessary md pattern for TARGET_XTHEADCONDMOV | | | 102317 RISC-V: Optimize reverse series index vector | | | 102334 RISCV: Add -m(no)-omit-leaf-frame-pointer support. | | | 102342 rtl-optimization: [PR102733] DSE removing address which only differ by address space. | | | 102376 Fix PR101188 wrong code from postreload | | | 102412 [V2] RISC-V: Fix warning in predicated.md | | | 102426 Consider '--with-build-sysroot=[...]' for target libraries' build-tree testing (instead of build-time 'CC' etc.) [PR109951] | | | 102427 [PR110086] avr: Fix ICE on optimize attribute | | | 102473 [1/2,RISC-V] fix cfi issue in save-restore. | | | 102474 [2/2,V3,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 102502 [avr,committed] Improve operations on non-LD_REGS when the operation follows a move from LD_REGS. | | | 102549 Add more ForEachMacros to clang-format file | | | 102559 [pushed] analyzer: regions in different memory spaces can't alias | | | 102561 [pushed] analyzer: implement various atomic builtins [PR109015] | | | 102575 New wi::bitreverse function. | | | 102578 c++: is_specialization_of_friend confusion [PR109923] | | | 102579 c++: simplify TEMPLATE_TEMPLATE_PARM hashing | | | 102582 [COMMITTED] reg-stack: Change return type of predicate functions from int to bool | | | 102592 c++: replace in_template_function | | | 102596 [01/12,contrib] validate_failures.py: Avoid testsuite aliasing | | | 102601 [02/12,contrib] validate_failures.py: Support expiry attributes in manifests | | | 102600 [03/12,contrib] validate_failures.py: Read in manifest when comparing build dirs | | | 102598 [04/12,contrib] validate_failures.py: Simplify GetManifestPath() | | | 102603 [05/12,contrib] validate_failures.py: Add more verbosity levels | | | 102602 [06/12,contrib] validate_failures.py: Be more stringent in parsing result lines | | | 102604 [07/12,contrib] validate_failures.py: Use exit code "2" to indicate regression | | | 102607 [08/12,contrib] validate_failures.py: Support "$tool:" prefix in exp names | | | 102605 [09/12,contrib] validate_failures.py: Improve error output | | | 102599 [10/12,contrib] validate_failures.py: Add new option --invert_match | | | 102606 [11/12,contrib] validate_failures.py: Add "--expiry_date YYYYMMDD" option | | | 102608 [12/12,contrib] validate_failures.py: Ignore stray filesystem paths in results | | | 102628 libstdc++: Do not assume existence of char8_t codecvt facet | | | 102629 [pushed] c++: fix explicit/copy problem [PR109247] | | | 102630 c++: bad 'this' conversion for nullary memfn [PR106760] | | | 102633 [committed] btf: Fix -Wformat errors | | | 102654 [committed] btf: fix bootstrap -Wformat errors [PR110073] | | | 102659 libatomic: Enable lock-free 128-bit atomics on AArch64 [PR110061] | | | 102660 [committed] Fortran: fix diagnostics for SELECT RANK [PR100607] | | | 102677 [pushed] Darwin, PPC: Fix struct layout with pragma pack [PR110044]. | | | 102807 xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode | | | 102837 libatomic: x86_64: Always try ifunc | | | 102840 RISC-V: Support RVV zvfh{min} vfloat16*_t mov and spill | | | 102863 [x86_64] PR target/110083: Fix-up REG_EQUAL notes on COMPARE in STV. | | | 102924 [x86] Add support for stc, clc and cmc instructions in i386.md | | | 102925 xtensa: Optimize boolean evaluation or branching when EQ/NE to INT_MIN | | | 102964 RISC-V: Support RVV FP16 ZVFHMIN intrinsic API | | | 102969 RISC-V: Remove redundant vlmul_ext_* patterns to fix PR110109 | | | 102970 [NFC] RISC-V: Reorganize riscv-v.cc | | | 102975 RISC-V: Split arguments of expand_vec_perm | | | 102976 [NFC] RISC-V: Move optimization patterns into autovec-opt.md | | | 103038 [committed] Convert H8 port to LRA | | | 103046 [RFA] Improve strcmp expansion when one input is a constant string. | | | 103053 [x86] Add missing vec_pack/unpacks patterns for _Float16 <-> int/float conversion. | | | 103057 MAINTAINERS: move Matthew Fortune to Write After Approval | | | 103061 [V2] VECT: Add SELECT_VL support | | | 103081 Fix PR 110085: `make clean` in GCC directory on sh target causes a failure | | | 103086 [1/2] Improve do_store_flag for single bit when there is no non-zero bits | | | 103087 [2/2] Handle const_int in expand_single_bit_test | | | 103092 [RISC-V] add TC for save-restore cfi directives. | | | 103097 rs6000: Remove duplicate expression [PR106907] | | | 103098 [v1] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API | | | 103194 [v2] xtensa: Optimize boolean evaluation or branching when EQ/NE to zero in S[IF]mode | | | 103180 RISC-V: Fix 'REQUIREMENT' for machine_mode 'MODE' in vector-iterators.md. | | | 103182 [v2] RISC-V: Support RVV FP16 ZVFH floating-point intrinsic API | | | 103199 [V3] VECT: Add SELECT_VL support | | | 103202 ??????: Re: [PATCH V3] VECT: Add SELECT_VL support | | | 103219 Add 'libgomp.{,oacc-}fortran/fortran-torture_execute_math.f90' | | | 103222 driver: Forward '-lgfortran', '-lm' to offloading compilation | | | 103303 libiberty: writeargv: Simplify function error mode. | | | 103312 [v1] RISC-V: Support RVV FP16 ZVFH Reduction floating-point intrinsic API | | | 103318 [v1] RISC-V: Fix some typo in vector-iterators.md | | | 103334 Ping: Fwd: [V9][PATCH 1/2] Handle component_ref to a structre/union field including flexible array member [PR101832] | | | 103364 [COMMITTED] reginfo: Change return type of predicate functions from int to bool | | | 103365 [COMMITTED] print-rtl: Change return type of two print functions from int to void | | | 103397 [committed] d: Warn when declared size of a special enum does not match its intrinsic type. | | | 103502 c++: extend lookup_template_class shortcut [PR110122] | | | 103528 [RISC-V] correct machine mode in save-restore cfi RTL. | | | 103536 [committed] bootstrap rtl-checking: Fix XVEC vs XVECEXP in postreload.cc | | | 103548 RISC-V: Support RVV VLA SLP auto-vectorization | | | 103555 Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. | | | 103554 Don't fold _mm{, 256}_blendv_epi8 into (mask < 0 ? src1 : src2) when -funsigned-char. | | | 103556 riscv: Fix insn cost calculation | | | 103557 riscv: Fix scope for memory model calculation | | | 103586 [v3] MIPS16: Implement `code_readable` function attribute. | | | 103595 middle-end/110055 - avoid CLOBBERing static variables | | | 103598 tree-optimization/109143 - improve PTA compile time | | | 103627 [v2] Explicitly view_convert_expr mask to signed type when folding pblendvb builtins. | | | 103637 [1/2] Fold _mm{, 256, 512}_abs_{epi8, epi16, epi32, epi64} into gimple ABSU_EXPR + VCE. | | | 103680 rs6000: Guard __builtin_{un,}pack_vector_int128 with vsx [PR109932] | | | 103681 rs6000: Don't use TFmode for 128 bits fp constant in toc [PR110011] | | | 103695 libgcc: Fix eh_frame fast path in find_fde_tail | | | 103696 [1/2] Missed opportunity to use [SU]ABD | | | 103698 RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103736 [committed] libstdc++: Use close-on-exec for file descriptors in filesystem::copy_file | | | 103741 [committed] libstdc++: Fix ambiguous expression in std::array::front() [PR110139] | | | 103738 [V2] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103740 RISC-V: Enable SELECT_VL for RVV | | | 103739 RISC-V: Support RVV VLA SLP auto-vectorization | | | 103742 [V3] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103744 analyzer: Standalone OOB-warning [PR109437, PR109439] | | | 103749 [V4] RISC-V: Add RVV vwmacc/vwmaccu/vwmaccsu combine lowering optmization | | | 103773 [committed] libstdc++: Protect against macros | | | 103775 libstdc++: Replace use of incorrect non-temporal store | | | 103778 libstdc++: Avoid vector casts while still avoiding PR90424 | | | 103781 [v1] RISC-V: Refactor ZVFHMIN to separated iterator and pattern | | | 103830 [GCC,12,committed] d: Merge upstream dmd 316b89f1e3, phobos 8e8aaae50. | | | 103832 [1/2] rs6000: genfusion: Rewrite load/compare code | | | 103833 [2/2] rs6000: genfusion: Delete dead code | | | 103848 libstdc++: Rewrite or avoid casts to 64-bit element types | | | 103862 [1/2] Missed opportunity to use [SU]ABD | | | 103896 [committed] Re: [PATCHv2] openmp: Add support for 'present' modifier | | | 103915 [OpenACC,2.7] Implement host_data must have use_device clause requirement | | | 103917 [OpenACC,2.7] Implement default clause support for data constructs | | | 103929 [2/2] AArch64: New RTL for ABD | | | 103934 [v2] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 103936 libgomp: plugin-gcn - support 'unified_address' | | | 103960 [committed] libstdc++: Make std::numeric_limits<__float128> more portable [PR104772] | | | 103961 [committed] libstdc++: Update list of known symbol versions for abi-check | | | 103997 [COMMITTED] reload1: Change return type of predicate function from int to bool | | | 104030 c++: unsynthesized defaulted constexpr fn [PR110122] | | | 104095 [ver,2] rs6000: Add builtins for IEEE 128-bit floating point values | | | 104108 [v6,1/4] libcpp: reject codepoints above 0x10FFFF | | | 104110 [v6,2/4] p1689r5: initial support | | | 104109 [v6,4/4] c++modules: report module mapper files as a dependency | | | 104112 For the `-A CMP -B -> B CMP A` pattern allow EQ/NE for all integer types | | | 104116 modula2: Fix bootstrap | | | 104117 [COMMITTED/13] Fix PR 110085: `make clean` in GCC directory on sh target causes a failure | | | 104118 middle-end, i386: Pattern recognize add/subtract with carry [PR79173] | | | 104122 [x86_64] PR target/110104: Missing peephole2 for addcarry. | | | 104135 [x86] PR target/31985: Improve memory operand use with doubleword add. | | | 104159 [1/2] Match: zero_one_valued_p should match 0 constants too | | | 104160 [2/2] Add match patterns for `a ? onezero : onezero` where one of the two operands are constant | | | 104171 [pushed] c++: add NRV testcase [PR58050] | | | 104172 [pushed] c++: fix contracts with NRV | | | 104173 [pushed] c++: fix throwing cleanup with label | | | 104176 [pushed] c++: NRV and goto [PR92407] | | | 104174 [pushed] c++: enable NRVO from inner block [PR51571] | | | 104175 [pushed] c++: Add -Wnrvo | | | 104192 RISC-V: Fix ICE when include riscv_vector.h with rv64gcv | | | 104198 LoongArch: Change jumptable's register constraint to 'q' [PR110136] | | | 104208 [v3] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104213 [V2] RISC-V: Support RVV VLA SLP auto-vectorization | | | 104223 [v1] LoongArch:Change the default value of LARCH_CALL_RATIO to 6 on the LoongArch architecture. | | | 104243 rs6000: Remove redundant initialization [PR106907] | | | 104248 [1/4,V4,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 104247 [2/4,RISC-V] support cm.popretz in zcmp | | | 104250 [3/4,RISC-V] resolve confilct between zcmp multi push/pop and shrink-wrap-separate | | | 104249 [4/4,RISC-V] support cm.mva01s cm.mvsa01 in zcmp | | | 104258 Add parentheses to clarify precedence between operators [PR106907] | | | 104277 RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104279 Support 'UNSUPPORTED: [...]: exception handling disabled' for libstdc++ testing (was: Support in the GCC(/C++) test suites for '-fno-exceptions') | | | 104317 [v2] LoongArch:Change the default value of LARCH_CALL_RATIO to 6 on the LoongArch architecture. | | | 104323 [v5] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104326 [testsuite] bump some tsvc timeouts | | | 104338 [V2] Optimize '(X - N * M) / N' to 'X / N - M' if valid | | | 104344 [avr] : Improve bit-extractions as of PR109907. | | | 104385 libiberty: pex-unix.c: Make pex_unix_cleanup signature always match body. | | | 104387 [3/4] ree: Improve functionality of ree pass for rs6000 target. | | | 104444 [committed] testsuite/libgomp.*/target-present-*.{c, f90}: Improve and fix (was: Re: [og12] Fix 'libgomp.{c-c++-common, fortran}/target-present-*' test cases) | | | 104485 [V4] VECT: Add SELECT_VL support | | | 104506 [v2,1/3] RISC-V: Minimal support for ZC* extensions. | | | 104507 [v2,2/3] RISC-V: Enable compressible features when use ZC* extensions. | | | 104508 [v2,3/3] RISC-V: Add ZC* test for failed march args being passed. | | | 104515 RISC-V: Add Veyron V1 pipeline description | | | 104524 [1/3] aarch64: Fix whitespace in ls64 builtin implementation [PR110100] | | | 104523 [2/3] aarch64: Fix wrong code with st64b builtin [PR110100] | | | 104525 [3/3] aarch64: Allow compiler to define ls64 builtins [PR110132] | | | 104534 vect: Don't pass subtype to vect_widened_op_tree where not needed [PR 110142] | | | 104548 [committed] Fix expected test output on hppa | | | 104552 Remove 'gcc/testsuite/g++.dg/warn/Wfree-nonheap-object.s' (was: [PATCH] add -Wmismatched-new-delete to middle end (PR 90629)) | | | 104560 Tighten 'dg-warning' alternatives in 'c-c++-common/Wfree-nonheap-object{,-2,-3}.c' (was: [PATCH] correct -Wmismatched-new-delete (PR 98160, 98166)) | | | 104593 [committed] libstdc++: Fix some tests that fail with -fexcess-precision=standard | | | 104597 [committed] libstdc++: Fix some tests that fail with -fno-exceptions | | | 104598 [committed] libstdc++: Restore accidentally removed version in abi-check | | | 104608 [fortran] PR87477 - (associate) - [meta-bug] [F03] issues concerning the ASSOCIATE statement | | | 104628 i386: Fix endless recursion in ix86_expand_vector_init_general with MMX [PR110152] | | | 104630 optabs: Implement double-word ctz and ffs expansion | | | 104634 libstdc++: Fix up 20_util/to_chars/double.cc test for excess precision [PR110145] | | | 104708 MATCH: Fix comment for `(zero_one ==/!= 0) ? y : z y` patterns | | | 104712 [1/3] MATCH: Allow unsigned types for `X & -Y -> X * Y` pattern | | | 104713 [2/3] Change the `zero_one ==/!= 0) ? y : z y` patterns to use multiply rather than `(-zero_one) & z` | | | 104714 [3/3] Add Plus to the op list of `(zero_one == 0) ? y : z y` pattern | | | 104741 [pushed] c++: allow NRV and non-NRV returns [PR58487] | | | 104772 [Committed] Bug fix to new wi::bitreverse_large function. | | | 104774 [nvptx] Update nvptx's bitrev2 pattern to use BITREVERSE rtx. | | | 104789 [1/4] rs6000: build constant via li;rotldi | | | 104792 [2/4] rs6000: build constant via lis;rotldi | | | 104791 [3/4] rs6000: build constant via li/lis;rldicl/rldicr | | | 104790 [4/4] rs6000: build constant via li/lis;rldic | | | 104794 [V5] VECT: Add SELECT_VL support | | | 104800 [v2] LoongArch: Modify the register constraints for template "jumptable" and "indirect_jump" from "r" to "e" [PR110136] | | | 104823 [v6] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104827 [v7] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104830 [v8] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 104861 [v2] RISC-V: Add more test cases for RVV FP16 | | | 104891 [COMMITTED] analyzer: Standalone OOB-warning, formatting fixed [PR109437, PR109439] | | | 104902 [GCC,AArch64] convert some patterns to new MD syntax | | | 104916 [1/2] Missed opportunity to use [SU]ABD | | | 104920 [2/2] AArch64: New RTL for ABD | | | 104932 [RFC] c++: Accept elaborated-enum-base in system headers | | | 104935 testsuite: fix the condition bug in tsvc s176 | | | 104998 fix frange_nextafter odr violation | | | 105006 [ver,3] rs6000: Add builtins for IEEE 128-bit floating point values | | | 105077 doc: Clarification for -Wmissing-field-initializers | | | 105084 [COMMITTED,1/4] Fix floating point bug in fold_range. | | | 105085 [COMMITTED,2/4] - Remove tree_code from range-operator. | | | 105087 [COMMITTED,3/4] Unify range_operators to one class. | | | 105086 [COMMITTED,4/4] Provide a new dispatch mechanism for range-ops. | | | 105212 MATCH: Fix zero_one_valued_p not to match signed 1 bit integers | | | 105280 [v9] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 105284 [v4] RISC-V: Add vector psabi checking. | | | 105297 [v10] RISC-V: Refactor requirement of ZVFH and ZVFHMIN. | | | 105316 middle-end/110182 - TYPE_PRECISION on VECTOR_TYPE causes wrong-code | | | 105317 Prevent TYPE_PRECISION on VECTOR_TYPEs | | | 105328 [v1] RISC-V: Fix one warning of frm enum. | | | 105355 [committed] fortran: Fix ICE on pr96024.f90 on big-endian hosts [PR96024] | | | 105424 [V6] VECT: Add SELECT_VL support | | | 105441 [committed] libstdc++: Improve tests for emplace member of sequence containers | | | 105520 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS | +------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master fatal: refusing to merge unrelated histories + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series43111-patch105520 ++ git branch -a ++ grep 'series43111-patch105520$' + checkbranch= + checkbranchresult=null + '[' null = series43111-patch105520 ']' + git checkout -b series43111-patch105520 Switched to a new branch 'series43111-patch105520' ++ curl https://patchwork.plctlab.org/api/1.2/series/43111/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1383 100 1383 0 0 27117 0 --:--:-- --:--:-- --:--:-- 27117 + series_response='{"id":43111,"url":"https://patchwork.plctlab.org/api/1.2/series/43111/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=43111","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","date":"2023-06-09T10:32:51","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/43111/mbox/","cover_letter":null,"patches":[{"id":105520,"url":"https://patchwork.plctlab.org/api/1.2/patches/105520/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/","msgid":"<20230609103251.335449-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-06-09T10:32:51","name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ echo '{"id":43111,"url":"https://patchwork.plctlab.org/api/1.2/series/43111/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=43111","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","date":"2023-06-09T10:32:51","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/43111/mbox/","cover_letter":null,"patches":[{"id":105520,"url":"https://patchwork.plctlab.org/api/1.2/patches/105520/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/","msgid":"<20230609103251.335449-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-06-09T10:32:51","name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"105520,https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/"' + echo '"105520,https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"105520' ++ sed 's/"//g' + series_patch_id=105520 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++ git rev-parse HEAD + commitid_before=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='\''\'\'''\''Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='\''Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins14073989153114092736.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='\''Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins14073989153114092736.sh: line 162: ++: command not found ++ ++ declare -p berr /tmp/jenkins14073989153114092736.sh: line 163: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='\''Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 38509 100 38509 0 0 723k 0 --:--:-- --:--:-- --:--:-- 723k +++ bout='Applying: RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS Using index info to reconstruct a base tree... M gcc/config/riscv/riscv-vsetvl.cc Falling back to patching base and 3-way merge... Auto-merging gcc/config/riscv/riscv-vsetvl.cc CONFLICT (content): Merge conflict in gcc/config/riscv/riscv-vsetvl.cc error: Failed to merge in the changes. hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ Failed to merge in the changes ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/8081/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/8081/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/8081/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/105520/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 966 100 426 100 540 7888 10000 --:--:-- --:--:-- --:--:-- 17888 {"id":9374,"url":"https://patchwork.plctlab.org/api/patches/105520/checks/9374/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-06-09T11:17:10.038074","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/8081/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/105520/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":105520,"url":"https://patchwork.plctlab.org/api/1.2/patches/105520/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230609103251.335449-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-06-09T10:32:51","name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"8f3ecf767d32e009327229129c38516e38c2b034","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230609103251.335449-1-juzhe.zhong@rivai.ai/mbox/","series":[{"id":43111,"url":"https://patchwork.plctlab.org/api/1.2/series/43111/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=43111","date":"2023-06-09T10:32:51","name":"RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","version":1,"mbox":"https://patchwork.plctlab.org/series/43111/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/105520/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/105520/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp847733vqr;\n Fri, 9 Jun 2023 03:33:51 -0700 (PDT)","from sourceware.org (server2.sourceware.org. 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mx.google.com;\n spf=pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","Received-SPF":"pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender) client-ip=8.43.85.97;","Authentication-Results":["mx.google.com;\n spf=pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","sourceware.org;\n dmarc=none (p=none dis=none) header.from=rivai.ai","sourceware.org; spf=pass smtp.mailfrom=rivai.ai"],"X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org 43B823858D35","X-QQ-mid":"bizesmtp71t1686306776tzd3uw1d","X-QQ-SSF":"01400000000000F0S000000A0000000","X-QQ-FEAT":"CR3LFp2JE4ntGi7jg2iQgKJJDmi4wmiUs7Oj0zkcYInnaCUTrBr9uXMaf47Rx\n jezv8eAwaHKhcqulWU68vDiin7DyKSUjuoPAKaF0sWOBPfOu8v22xxtB4wbxW9HbTjJXs7K\n HRUtblMGmP49LtX5BrieLTugjoqfB7Vk5jSkzo9zq4udJSfEoZ5x4YhjKUTzK/2usJX8sCD\n G3yjs8gUMMr4bFkBSMl67rJQCl0WGqJ5lOC/Wy+0JW1HH/Mb4Sw5wWXWfwx7OQUmOI9/Hip\n BMwfFl7FRUlUWQn+eP8X1q57z+Ylxzt7VQ3+b6je+GN0vrei0ejs/9OytCiGOsGbdJ5H0hv\n d3BEaOz1UhWyFVm3+lwaPqDi3nXEz/yEK6EYdWz3L6Cur8N57UPx/BgeXG7B7m1A7hxGYRl\n z5QsiagbfdE=","X-QQ-GoodBg":"2","X-BIZMAIL-ID":"138639123165100767","From":"juzhe.zhong@rivai.ai","To":"gcc-patches@gcc.gnu.org","Cc":"kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com,\n palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com,\n pan2.li@intel.com, Juzhe-Zhong ","Subject":"[PATCH] RISC-V: Rework Phase 5 && Phase 6 of VSETVL PASS","Date":"Fri, 9 Jun 2023 18:32:51 +0800","Message-Id":"<20230609103251.335449-1-juzhe.zhong@rivai.ai>","X-Mailer":"git-send-email 2.36.1","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-QQ-SENDSIZE":"520","Feedback-ID":"bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0","X-Spam-Status":"No, score=-8.3 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_BARRACUDACENTRAL,\n RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL,\n SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS,\n TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1768220871114561934?=","X-GMAIL-MSGID":"=?utf-8?q?1768220871114561934?="},"content":"From: Juzhe-Zhong \n\nThis patch is to rework Phase 5 && Phase 6 of VSETVL PASS since Phase 5 && Phase 6\nare quite messy and cause some bugs discovered by my downstream auto-vectorization\ntest-generator.\n\nBefore this patch.\n\nPhase 5 is cleanup_insns is the function remove AVL operand dependency from each RVV instruction.\nE.g. vadd.vv (use a5), after Phase 5, ====> vadd.vv (use const_int 0). Since \"a5\" is used in \"vsetvl\" instructions and\nafter the correct \"vsetvl\" instructions are inserted, each RVV instruction doesn't need AVL operand \"a5\" anymore. Then,\nwe remove this operand dependency helps for the following scheduling PASS.\n\nPhase 6 is propagate_avl do the following 2 things:\n1. Local && Global user vsetvl instructions optimization.\n E.g.\n vsetvli a2, a2, e8, mf8 ======> Change it into vsetvli a2, a2, e32, mf2\n vsetvli zero,a2, e32, mf2 ======> eliminate\n2. Optimize user vsetvl from \"vsetvl a2,a2\" into \"vsetvl zero,a2\" if \"a2\" is not used by any instructions.\nSince from Phase 1 ~ Phase 4 which inserts \"vsetvli\" instructions base on LCM which change the CFG, I re-new a new\nRTL_SSA framework (which is more expensive than just using DF) for Phase 6 and optmize user vsetvli base on the new RTL_SSA.\n\nThere are 2 issues in Phase 5 && Phase 6:\n1. local_eliminate_vsetvl_insn was introduced by @kito which can do better local user vsetvl optimizations better than\n Phase 6 do, such approach doesn't need to re-new the RTL_SSA framework. So the local user vsetvli instructions optimizaiton\n in Phase 6 is redundant and should be removed.\n2. A bug discovered by my downstream auto-vectorization test-generator (I can't put the test in this patch since we are missing autovec\n patterns for it so we can't use the upstream GCC directly reproduce such issue but I will remember put it back after I support the\n necessary autovec patterns). Such bug is causing by using RTL_SSA re-new framework. The issue description is this:\n \nBefore Phase 6:\n ...\n insn1: vsetlvi a3, 17 <========== generated by SELECT_VL auto-vec pattern.\n slli a4,a3,3\n ...\n insn2: vsetvli zero, a3, ... \n load (use const_int 0, before Phase 5, it's using a3, but the use of \"a3\" is removed in Phase 5)\n ...\n\nIn Phase 6, we iterate to insn2, then get the def of \"a3\" which is the insn1.\ninsn2 is the vsetvli instruction inserted in Phase 4 which is not included in the RLT_SSA framework\neven though we renew it (I didn't take a look at it and I don't think we need to now).\nBase on this situation, the def_info of insn2 has the information \"set->single_nondebug_insn_use ()\"\nwhich return true. Obviously, this information is not correct, since insn1 has aleast 2 uses:\n1). slli a4,a3,3 2).insn2: vsetvli zero, a3, ... Then, the test generated by my downstream test-generator\nexecution test failed.\n\nConclusion of RTL_SSA framework:\nBefore this patch, we initialize RTL_SSA 2 times. One is at the beginning of the VSETVL PASS which is absolutely correct, the other\nis re-new after Phase 4 (LCM) has incorrect information that causes bugs.\n\nBesides, we don't like to initialize RTL_SSA second time it seems to be a waste since we just need to do a little optimization.\n\nBase on all circumstances I described above, I rework and reorganize Phase 5 && Phase 6 as follows:\n1. Phase 5 is called ssa_post_optimization which is doing the optimization base on the RTL_SSA information (The RTL_SSA is initialized\n at the beginning of the VSETVL PASS, no need to re-new it again). This phase includes 3 optimizaitons:\n 1). local_eliminate_vsetvl_insn we already have (no change).\n 2). global_eliminate_vsetvl_insn ---> new optimizaiton splitted from orignal Phase 6 but with more powerful and reliable implementation.\n E.g. \n void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {\n size_t avl;\n if (m > 100)\n avl = __riscv_vsetvl_e16mf4(vl << 4);\n else{\n avl = __riscv_vsetvl_e8mf8(vl);\n }\n for (size_t i = 0; i < m; i++) {\n vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);\n __riscv_vse8_v_i8mf8(out + i, v0, avl);\n }\n }\n This example failed to global user vsetvl optimize before this patch:\n f:\n ...\n vsetvli a2,a2,e16,mf4,ta,mu\n .L3:\n li a5,0\n vsetvli zero,a2,e8,mf8,ta,ma\n .L5:\n ...\n vle8.v v1,0(a6)\n addi a5,a5,1\n vse8.v v1,0(a4)\n bgtu a3,a5,.L5\n .L10:\n ret\n .L2:\n beq a3,zero,.L10\n vsetvli a2,a2,e8,mf8,ta,mu\n j .L3\n With this patch:\n f:\n ...\n vsetvli zero,a2,e16,mf4,ta,mu\n .L3:\n li a5,0\n .L5:\n ...\n vle8.v v1,0(a6)\n addi a5,a5,1\n vse8.v v1,0(a4)\n bgtu a3,a5,.L5\n .L10:\n ret\n .L2:\n beq a3,zero,.L10\n vsetvli zero,a2,e8,mf8,ta,mu\n j .L3\n 3). Remove AVL operand dependency of each RVV instructions.\n\n2. Phase 6 is called df_post_optimization: Optimize \"vsetvl a3,a2....\" into Optimize \"vsetvl zero,a2....\" base on\n dataflow analysis of new CFG (new CFG is created by LCM). The reason we need to do use new CFG and after Phase 5:\n ...\n vsetvl a3, a2...\n vadd.vv (use a3)\n If we don't have Phase 5 which removes the \"a3\" use in vadd.vv, we will fail to optimize vsetvl a3,a2 into vsetvl zero,a2.\n \n This patch passed all tests in rvv.exp with no peformance && codegen improved (no performance decline and no bugs including my\n downstream tests).\n\ngcc/ChangeLog:\n\n * config/riscv/riscv-vsetvl.cc (available_occurrence_p): Ehance user vsetvl optimization.\n (vector_insn_info::parse_insn): Add rtx_insn parse.\n (pass_vsetvl::local_eliminate_vsetvl_insn): Ehance user vsetvl optimization.\n (get_first_vsetvl): New function.\n (pass_vsetvl::global_eliminate_vsetvl_insn): Ditto.\n (pass_vsetvl::cleanup_insns): Remove it.\n (pass_vsetvl::ssa_post_optimization): New function.\n (has_no_uses): Ditto.\n (pass_vsetvl::propagate_avl): Remove it.\n (pass_vsetvl::df_post_optimization): New function.\n (pass_vsetvl::lazy_vsetvl): Rework Phase 5 && Phase 6.\n * config/riscv/riscv-vsetvl.h: Adapt declaration.\n\ngcc/testsuite/ChangeLog:\n\n * gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: Adapt test.\n * gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: Ditto.\n * gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: Ditto.\n * gcc.target/riscv/rvv/vsetvl/vsetvl-21.c: New test.\n * gcc.target/riscv/rvv/vsetvl/vsetvl-22.c: New test.\n * gcc.target/riscv/rvv/vsetvl/vsetvl-23.c: New test.\n\n---\n gcc/config/riscv/riscv-vsetvl.cc | 400 +++++++++++-------\n gcc/config/riscv/riscv-vsetvl.h | 34 +-\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-16.c | 2 +-\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-2.c | 2 +-\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-21.c | 21 +\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-22.c | 21 +\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c | 37 ++\n .../gcc.target/riscv/rvv/vsetvl/vsetvl-3.c | 2 +-\n 8 files changed, 366 insertions(+), 153 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c","diff":"diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc\nindex fe55f4ccd30..924a94adf9c 100644\n--- a/gcc/config/riscv/riscv-vsetvl.cc\n+++ b/gcc/config/riscv/riscv-vsetvl.cc\n@@ -395,10 +395,15 @@ available_occurrence_p (const bb_info *bb, const vector_insn_info dem)\n if (!vlmax_avl_p (dem.get_avl ()))\n \t{\n \t rtx dest = NULL_RTX;\n+\t insn_info *i = insn;\n \t if (vsetvl_insn_p (insn->rtl ()))\n-\t dest = get_vl (insn->rtl ());\n-\t for (const insn_info *i = insn; real_insn_and_same_bb_p (i, bb);\n-\t i = i->next_nondebug_insn ())\n+\t {\n+\t dest = get_vl (insn->rtl ());\n+\t /* For user vsetvl a2, a2 instruction, we consider it as\n+\t\t available even though it modifies \"a2\". */\n+\t i = i->next_nondebug_insn ();\n+\t }\n+\t for (; real_insn_and_same_bb_p (i, bb); i = i->next_nondebug_insn ())\n \t {\n \t if (read_vl_insn_p (i->rtl ()))\n \t\tcontinue;\n@@ -1893,11 +1898,13 @@ vector_insn_info::parse_insn (rtx_insn *rinsn)\n *this = vector_insn_info ();\n if (!NONDEBUG_INSN_P (rinsn))\n return;\n- if (!has_vtype_op (rinsn))\n+ if (optimize == 0 && !has_vtype_op (rinsn))\n+ return;\n+ if (optimize > 0 && !vsetvl_insn_p (rinsn))\n return;\n m_state = VALID;\n extract_insn_cached (rinsn);\n- const rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)];\n+ rtx avl = ::get_avl (rinsn);\n m_avl = avl_info (avl, nullptr);\n m_sew = ::get_sew (rinsn);\n m_vlmul = ::get_vlmul (rinsn);\n@@ -2730,10 +2737,11 @@ private:\n /* Phase 5. */\n rtx_insn *get_vsetvl_at_end (const bb_info *, vector_insn_info *) const;\n void local_eliminate_vsetvl_insn (const bb_info *) const;\n- void cleanup_insns (void) const;\n+ bool global_eliminate_vsetvl_insn (const bb_info *) const;\n+ void ssa_post_optimization (void) const;\n \n /* Phase 6. */\n- void propagate_avl (void) const;\n+ void df_post_optimization (void) const;\n \n void init (void);\n void done (void);\n@@ -4246,7 +4254,7 @@ pass_vsetvl::local_eliminate_vsetvl_insn (const bb_info *bb) const\n \n /* Local AVL compatibility checking is simpler than global, we only\n \t need to check the REGNO is same. */\n- if (prev_dem.valid_p () && prev_dem.skip_avl_compatible_p (curr_dem)\n+ if (prev_dem.valid_or_dirty_p () && prev_dem.skip_avl_compatible_p (curr_dem)\n \t && local_avl_compatible_p (prev_avl, curr_avl))\n \t{\n \t /* curr_dem and prev_dem is compatible! */\n@@ -4277,27 +4285,187 @@ pass_vsetvl::local_eliminate_vsetvl_insn (const bb_info *bb) const\n }\n }\n \n-/* Before VSETVL PASS, RVV instructions pattern is depending on AVL operand\n- implicitly. Since we will emit VSETVL instruction and make RVV instructions\n- depending on VL/VTYPE global status registers, we remove the such AVL operand\n- in the RVV instructions pattern here in order to remove AVL dependencies when\n- AVL operand is a register operand.\n-\n- Before the VSETVL PASS:\n- li a5,32\n- ...\n- vadd.vv (..., a5)\n- After the VSETVL PASS:\n- li a5,32\n- vsetvli zero, a5, ...\n- ...\n- vadd.vv (..., const_int 0). */\n+/* Get the first vsetvl instructions of the block. */\n+static rtx_insn *\n+get_first_vsetvl (basic_block cfg_bb)\n+{\n+ rtx_insn *rinsn;\n+ FOR_BB_INSNS (cfg_bb, rinsn)\n+ {\n+ if (!NONDEBUG_INSN_P (rinsn))\n+\tcontinue;\n+ /* If we don't find any inserted vsetvli before user RVV instructions,\n+\t we don't need to optimize the vsetvls in this block. */\n+ if (has_vtype_op (rinsn) || vsetvl_insn_p (rinsn))\n+\treturn nullptr;\n+\n+ if (vsetvl_discard_result_insn_p (rinsn))\n+\treturn rinsn;\n+ }\n+ return nullptr;\n+}\n+\n+/* Global user vsetvl optimizaiton:\n+\n+ Case 1:\n+ bb 1:\n+ vsetvl a5,a4,e8,mf8\n+ ...\n+ bb 2:\n+ ...\n+ vsetvl zero,a5,e8,mf8 --> Eliminate directly.\n+\n+ Case 2:\n+ bb 1:\n+ vsetvl a5,a4,e8,mf8 --> vsetvl a5,a4,e32,mf2\n+ ...\n+ bb 2:\n+ ...\n+ vsetvl zero,a5,e32,mf2 --> Eliminate directly.\n+\n+ Case 3:\n+ bb 1:\n+ vsetvl a5,a4,e8,mf8 --> vsetvl a5,a4,e32,mf2\n+ ...\n+ bb 2:\n+ ...\n+ vsetvl a5,a4,e8,mf8 --> vsetvl a5,a4,e32,mf2\n+ goto bb 3\n+ bb 3:\n+ ...\n+ vsetvl zero,a5,e32,mf2 --> Eliminate directly.\n+*/\n+bool\n+pass_vsetvl::global_eliminate_vsetvl_insn (const bb_info *bb) const\n+{\n+ rtx_insn *vsetvl_rinsn;\n+ vector_insn_info dem = vector_insn_info ();\n+ const auto &block_info = get_block_info (bb);\n+ basic_block cfg_bb = bb->cfg_bb ();\n+\n+ if (block_info.local_dem.valid_or_dirty_p ())\n+ {\n+ /* Optimize the local vsetvl. */\n+ dem = block_info.local_dem;\n+ vsetvl_rinsn = get_first_vsetvl (cfg_bb);\n+ }\n+ if (!vsetvl_rinsn)\n+ /* Optimize the global vsetvl inserted by LCM. */\n+ vsetvl_rinsn = get_vsetvl_at_end (bb, &dem);\n+\n+ /* No need to optimize if block doesn't have vsetvl instructions. */\n+ if (!dem.valid_or_dirty_p () || !vsetvl_rinsn || !dem.get_avl_source ()\n+ || !dem.has_avl_reg ())\n+ return false;\n+\n+ /* If all preds has VL/VTYPE status setted by user vsetvls, and these\n+ user vsetvls are all skip_avl_compatible_p with the vsetvl in this\n+ block, we can eliminate this vsetvl instruction. */\n+ sbitmap avin = m_vector_manager->vector_avin[cfg_bb->index];\n+\n+ unsigned int bb_index;\n+ sbitmap_iterator sbi;\n+ rtx avl = get_avl (dem.get_insn ()->rtl ());\n+ hash_set sets\n+ = get_all_sets (dem.get_avl_source (), true, false, false);\n+ /* Condition 1: All VL/VTYPE available in are all compatible. */\n+ EXECUTE_IF_SET_IN_BITMAP (avin, 0, bb_index, sbi)\n+ {\n+ const auto &expr = m_vector_manager->vector_exprs[bb_index];\n+ const auto &insn = expr->get_insn ();\n+ def_info *def = find_access (insn->defs (), REGNO (avl));\n+ set_info *set = safe_dyn_cast (def);\n+ if (!vsetvl_insn_p (insn->rtl ()) || insn->bb () == bb\n+\t || !sets.contains (set))\n+\treturn false;\n+ }\n+\n+ /* Condition 2: Check it has preds. */\n+ if (EDGE_COUNT (cfg_bb->preds) == 0)\n+ return false;\n+\n+ /* Condition 3: We don't do the global optimization for the block\n+ has a pred is entry block or exit block. */\n+ /* Condition 4: All preds have available VL/VTYPE out. */\n+ edge e;\n+ edge_iterator ei;\n+ FOR_EACH_EDGE (e, ei, cfg_bb->preds)\n+ {\n+ sbitmap avout = m_vector_manager->vector_avout[e->src->index];\n+ if (e->src == ENTRY_BLOCK_PTR_FOR_FN (cfun)\n+\t || e->src == EXIT_BLOCK_PTR_FOR_FN (cfun) || bitmap_empty_p (avout))\n+\treturn false;\n+\n+ EXECUTE_IF_SET_IN_BITMAP (avout, 0, bb_index, sbi)\n+\t{\n+\t const auto &expr = m_vector_manager->vector_exprs[bb_index];\n+\t const auto &insn = expr->get_insn ();\n+\t def_info *def = find_access (insn->defs (), REGNO (avl));\n+\t set_info *set = safe_dyn_cast (def);\n+\t if (!vsetvl_insn_p (insn->rtl ()) || insn->bb () == bb\n+\t || !sets.contains (set) || !expr->skip_avl_compatible_p (dem))\n+\t return false;\n+\t}\n+ }\n+\n+ /* Step1: Reshape the VL/VTYPE status to make sure everything compatible. */\n+ hash_set pred_cfg_bbs = get_all_predecessors (cfg_bb);\n+ FOR_EACH_EDGE (e, ei, cfg_bb->preds)\n+ {\n+ sbitmap avout = m_vector_manager->vector_avout[e->src->index];\n+ EXECUTE_IF_SET_IN_BITMAP (avout, 0, bb_index, sbi)\n+\t{\n+\t vector_insn_info prev_dem = *m_vector_manager->vector_exprs[bb_index];\n+\t vector_insn_info curr_dem = dem;\n+\t insn_info *insn = prev_dem.get_insn ();\n+\t if (!pred_cfg_bbs.contains (insn->bb ()->cfg_bb ()))\n+\t continue;\n+\t /* Update avl info since we need to make sure they are fully\n+\t compatible before merge. */\n+\t curr_dem.set_avl_info (prev_dem.get_avl_info ());\n+\t /* Merge both and update into curr_vsetvl. */\n+\t prev_dem = curr_dem.merge (prev_dem, LOCAL_MERGE);\n+\t change_vsetvl_insn (insn, prev_dem);\n+\t}\n+ }\n+\n+ /* Step2: eliminate the vsetvl instruction. */\n+ eliminate_insn (vsetvl_rinsn);\n+ return true;\n+}\n+\n+/* This function does the following post optimization base on RTL_SSA:\n+\n+ 1. Local user vsetvl optimizations.\n+ 2. Global user vsetvl optimizations.\n+ 3. AVL dependencies removal:\n+ Before VSETVL PASS, RVV instructions pattern is depending on AVL operand\n+ implicitly. Since we will emit VSETVL instruction and make RVV\n+ instructions depending on VL/VTYPE global status registers, we remove the\n+ such AVL operand in the RVV instructions pattern here in order to remove\n+ AVL dependencies when AVL operand is a register operand.\n+\n+ Before the VSETVL PASS:\n+\tli a5,32\n+\t...\n+\tvadd.vv (..., a5)\n+ After the VSETVL PASS:\n+\tli a5,32\n+\tvsetvli zero, a5, ...\n+\t...\n+\tvadd.vv (..., const_int 0). */\n void\n-pass_vsetvl::cleanup_insns (void) const\n+pass_vsetvl::ssa_post_optimization (void) const\n {\n for (const bb_info *bb : crtl->ssa->bbs ())\n {\n local_eliminate_vsetvl_insn (bb);\n+ bool changed_p = true;\n+ while (changed_p)\n+\t{\n+\t changed_p = false;\n+\t changed_p |= global_eliminate_vsetvl_insn (bb);\n+\t}\n for (insn_info *insn : bb->real_nondebug_insns ())\n \t{\n \t rtx_insn *rinsn = insn->rtl ();\n@@ -4342,135 +4510,81 @@ pass_vsetvl::cleanup_insns (void) const\n }\n }\n \n+/* Return true if the SET result is not used by any instructions. */\n+static bool\n+has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int regno)\n+{\n+ /* Handle the following case that can not be detected in RTL_SSA. */\n+ /* E.g.\n+\t li a5, 100\n+\t vsetvli a6, a5...\n+\t ...\n+\t vadd (use a6)\n+\n+\tThe use of \"a6\" is removed from \"vadd\" but the information is\n+\tnot updated in RTL_SSA framework. We don't want to re-new\n+\ta new RTL_SSA which is expensive, instead, we use data-flow\n+\tanalysis to check whether \"a6\" has no uses. */\n+ if (bitmap_bit_p (df_get_live_out (cfg_bb), regno))\n+ return false;\n+\n+ rtx_insn *iter;\n+ for (iter = NEXT_INSN (rinsn); iter && iter != NEXT_INSN (BB_END (cfg_bb));\n+ iter = NEXT_INSN (iter))\n+ if (df_find_use (iter, regno_reg_rtx[regno]))\n+ return false;\n+\n+ return true;\n+}\n+\n+/* This function does the following post optimization base on dataflow\n+ analysis:\n+\n+ 1. Change vsetvl rd, rs1 --> vsevl zero, rs1, if rd is not used by any\n+ nondebug instructions. Even though this PASS runs after RA and it doesn't\n+ help for reduce register pressure, it can help instructions scheduling since\n+ we remove the dependencies.\n+\n+ 2. Remove redundant user vsetvls base on outcome of Phase 4 (LCM) && Phase 5\n+ (AVL dependencies removal). */\n void\n-pass_vsetvl::propagate_avl (void) const\n-{\n- /* Rebuild the RTL_SSA according to the new CFG generated by LCM. */\n- /* Finalization of RTL_SSA. */\n- free_dominance_info (CDI_DOMINATORS);\n- if (crtl->ssa->perform_pending_updates ())\n- cleanup_cfg (0);\n- delete crtl->ssa;\n- crtl->ssa = nullptr;\n- /* Initialization of RTL_SSA. */\n- calculate_dominance_info (CDI_DOMINATORS);\n+pass_vsetvl::df_post_optimization (void) const\n+{\n df_analyze ();\n- crtl->ssa = new function_info (cfun);\n-\n hash_set to_delete;\n- for (const bb_info *bb : crtl->ssa->bbs ())\n+ basic_block cfg_bb;\n+ rtx_insn *rinsn;\n+ FOR_ALL_BB_FN (cfg_bb, cfun)\n {\n- for (insn_info *insn : bb->real_nondebug_insns ())\n+ FOR_BB_INSNS (cfg_bb, rinsn)\n \t{\n-\t if (vsetvl_discard_result_insn_p (insn->rtl ()))\n+\t if (NONDEBUG_INSN_P (rinsn) && vsetvl_insn_p (rinsn))\n \t {\n-\t rtx avl = get_avl (insn->rtl ());\n-\t if (!REG_P (avl))\n-\t\tcontinue;\n-\n-\t set_info *set = find_access (insn->uses (), REGNO (avl))->def ();\n-\t insn_info *def_insn = extract_single_source (set);\n-\t if (!def_insn)\n-\t\tcontinue;\n-\n-\t /* Handle this case:\n-\t\t vsetvli\ta6,zero,e32,m1,ta,mu\n-\t\t li\ta5,4096\n-\t\t add\ta7,a0,a5\n-\t\t addi\ta7,a7,-96\n-\t\t vsetvli\tt1,zero,e8,mf8,ta,ma\n-\t\t vle8.v\tv24,0(a7)\n-\t\t add\ta5,a3,a5\n-\t\t addi\ta5,a5,-96\n-\t\t vse8.v\tv24,0(a5)\n-\t\t vsetvli\tzero,a6,e32,m1,tu,ma\n-\t */\n-\t if (vsetvl_insn_p (def_insn->rtl ()))\n-\t\t{\n-\t\t vl_vtype_info def_info = get_vl_vtype_info (def_insn);\n-\t\t vl_vtype_info info = get_vl_vtype_info (insn);\n-\t\t rtx avl = get_avl (def_insn->rtl ());\n-\t\t rtx vl = get_vl (def_insn->rtl ());\n-\t\t if (def_info.get_ratio () == info.get_ratio ())\n-\t\t {\n-\t\t if (vlmax_avl_p (def_info.get_avl ()))\n-\t\t\t{\n-\t\t\t info.set_avl_info (\n-\t\t\t avl_info (def_info.get_avl (), nullptr));\n-\t\t\t rtx new_pat\n-\t\t\t = gen_vsetvl_pat (VSETVL_NORMAL, info, vl);\n-\t\t\t validate_change (insn->rtl (),\n-\t\t\t\t\t &PATTERN (insn->rtl ()), new_pat,\n-\t\t\t\t\t false);\n-\t\t\t continue;\n-\t\t\t}\n-\t\t if (def_info.has_avl_imm () || rtx_equal_p (avl, vl))\n-\t\t\t{\n-\t\t\t info.set_avl_info (avl_info (avl, nullptr));\n-\t\t\t emit_vsetvl_insn (VSETVL_DISCARD_RESULT, EMIT_AFTER,\n-\t\t\t\t\t info, NULL_RTX, insn->rtl ());\n-\t\t\t if (set->single_nondebug_insn_use ())\n-\t\t\t {\n-\t\t\t to_delete.add (insn->rtl ());\n-\t\t\t to_delete.add (def_insn->rtl ());\n-\t\t\t }\n-\t\t\t continue;\n-\t\t\t}\n-\t\t }\n-\t\t}\n-\t }\n-\n-\t /* Change vsetvl rd, rs1 --> vsevl zero, rs1,\n-\t if rd is not used by any nondebug instructions.\n-\t Even though this PASS runs after RA and it doesn't help for\n-\t reduce register pressure, it can help instructions scheduling\n-\t since we remove the dependencies. */\n-\t if (vsetvl_insn_p (insn->rtl ()))\n-\t {\n-\t rtx vl = get_vl (insn->rtl ());\n-\t rtx avl = get_avl (insn->rtl ());\n-\t def_info *def = find_access (insn->defs (), REGNO (vl));\n-\t set_info *set = safe_dyn_cast (def);\n+\t rtx vl = get_vl (rinsn);\n \t vector_insn_info info;\n-\t info.parse_insn (insn);\n-\t gcc_assert (set);\n-\t if (m_vector_manager->to_delete_vsetvls.contains (insn->rtl ()))\n-\t\t{\n-\t\t m_vector_manager->to_delete_vsetvls.remove (insn->rtl ());\n-\t\t if (m_vector_manager->to_refine_vsetvls.contains (\n-\t\t\tinsn->rtl ()))\n-\t\t m_vector_manager->to_refine_vsetvls.remove (insn->rtl ());\n-\t\t if (!set->has_nondebug_insn_uses ())\n-\t\t {\n-\t\t to_delete.add (insn->rtl ());\n-\t\t continue;\n-\t\t }\n-\t\t}\n-\t if (m_vector_manager->to_refine_vsetvls.contains (insn->rtl ()))\n+\t info.parse_insn (rinsn);\n+\t bool to_delete_p = m_vector_manager->to_delete_p (rinsn);\n+\t bool to_refine_p = m_vector_manager->to_refine_p (rinsn);\n+\t if (has_no_uses (cfg_bb, rinsn, REGNO (vl)))\n \t\t{\n-\t\t m_vector_manager->to_refine_vsetvls.remove (insn->rtl ());\n-\t\t if (!set->has_nondebug_insn_uses ())\n+\t\t if (to_delete_p)\n+\t\t to_delete.add (rinsn);\n+\t\t else if (to_refine_p)\n \t\t {\n \t\t rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY,\n \t\t\t\t\t\t info, NULL_RTX);\n-\t\t change_insn (insn->rtl (), new_pat);\n-\t\t continue;\n+\t\t validate_change (rinsn, &PATTERN (rinsn), new_pat, false);\n+\t\t }\n+\t\t else if (!vlmax_avl_p (info.get_avl ()))\n+\t\t {\n+\t\t rtx new_pat = gen_vsetvl_pat (VSETVL_DISCARD_RESULT, info,\n+\t\t\t\t\t\t NULL_RTX);\n+\t\t validate_change (rinsn, &PATTERN (rinsn), new_pat, false);\n \t\t }\n-\t\t}\n-\t if (vlmax_avl_p (avl))\n-\t\tcontinue;\n-\t rtx new_pat\n-\t\t= gen_vsetvl_pat (VSETVL_DISCARD_RESULT, info, NULL_RTX);\n-\t if (!set->has_nondebug_insn_uses ())\n-\t\t{\n-\t\t validate_change (insn->rtl (), &PATTERN (insn->rtl ()),\n-\t\t\t\t new_pat, false);\n-\t\t continue;\n \t\t}\n \t }\n \t}\n }\n-\n for (rtx_insn *rinsn : to_delete)\n eliminate_insn (rinsn);\n }\n@@ -4593,16 +4707,16 @@ pass_vsetvl::lazy_vsetvl (void)\n fprintf (dump_file, \"\\nPhase 4: PRE vsetvl by Lazy code motion (LCM)\\n\");\n pre_vsetvl ();\n \n- /* Phase 5 - Cleanup AVL && VL operand of RVV instruction. */\n+ /* Phase 5 - Post optimization base on RTL_SSA. */\n if (dump_file)\n- fprintf (dump_file, \"\\nPhase 5: Cleanup AVL and VL operands\\n\");\n- cleanup_insns ();\n+ fprintf (dump_file, \"\\nPhase 5: Post optimization base on RTL_SSA\\n\");\n+ ssa_post_optimization ();\n \n- /* Phase 6 - Rebuild RTL_SSA to propagate AVL between vsetvls. */\n+ /* Phase 6 - Post optimization base on data-flow analysis. */\n if (dump_file)\n fprintf (dump_file,\n-\t \"\\nPhase 6: Rebuild RTL_SSA to propagate AVL between vsetvls\\n\");\n- propagate_avl ();\n+\t \"\\nPhase 6: Post optimization base on data-flow analysis\\n\");\n+ df_post_optimization ();\n }\n \n /* Main entry point for this pass. */\ndiff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h\nindex d7a6c14e931..4257451bb74 100644\n--- a/gcc/config/riscv/riscv-vsetvl.h\n+++ b/gcc/config/riscv/riscv-vsetvl.h\n@@ -290,13 +290,6 @@ private:\n definition of AVL. */\n rtl_ssa::insn_info *m_insn;\n \n- /* Parse the instruction to get VL/VTYPE information and demanding\n- * information. */\n- /* This is only called by simple_vsetvl subroutine when optimize == 0.\n- Since RTL_SSA can not be enabled when optimize == 0, we don't initialize\n- the m_insn. */\n- void parse_insn (rtx_insn *);\n-\n friend class vector_infos_manager;\n \n public:\n@@ -305,6 +298,12 @@ public:\n m_insn (nullptr)\n {}\n \n+ /* Parse the instruction to get VL/VTYPE information and demanding\n+ * information. */\n+ /* This is only called by simple_vsetvl subroutine when optimize == 0.\n+ Since RTL_SSA can not be enabled when optimize == 0, we don't initialize\n+ the m_insn. */\n+ void parse_insn (rtx_insn *);\n /* This is only called by lazy_vsetvl subroutine when optimize > 0.\n We use RTL_SSA framework to initialize the insn_info. */\n void parse_insn (rtl_ssa::insn_info *);\n@@ -454,6 +453,27 @@ public:\n bool all_empty_predecessor_p (const basic_block) const;\n bool all_avail_in_compatible_p (const basic_block) const;\n \n+ bool to_delete_p (rtx_insn *rinsn)\n+ {\n+ if (to_delete_vsetvls.contains (rinsn))\n+ {\n+\tto_delete_vsetvls.remove (rinsn);\n+\tif (to_refine_vsetvls.contains (rinsn))\n+\t to_refine_vsetvls.remove (rinsn);\n+\treturn true;\n+ }\n+ return false;\n+ }\n+ bool to_refine_p (rtx_insn *rinsn)\n+ {\n+ if (to_refine_vsetvls.contains (rinsn))\n+ {\n+\tto_refine_vsetvls.remove (rinsn);\n+\treturn true;\n+ }\n+ return false;\n+ }\n+\n void release (void);\n void create_bitmap_vectors (void);\n void free_bitmap_vectors (void);\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c\nindex e0c6588b1db..29e05c4982b 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-16.c\n@@ -16,5 +16,5 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m) {\n }\n }\n \n-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n /* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*10} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c\nindex 0c5da5e640c..ff0171b3ff6 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-2.c\n@@ -17,4 +17,4 @@ void f(int8_t *base, int8_t *out, size_t vl, size_t m) {\n }\n \n /* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*10} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c\nnew file mode 100644\nindex 00000000000..551920c6a72\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-21.c\n@@ -0,0 +1,21 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2\" } */\n+\n+#include \"riscv_vector.h\"\n+\n+void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {\n+ size_t avl;\n+ if (m > 100)\n+ avl = __riscv_vsetvl_e16mf4(vl << 4);\n+ else{\n+ if (k)\n+ avl = __riscv_vsetvl_e8mf8(vl);\n+ }\n+ for (size_t i = 0; i < m; i++) {\n+ vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);\n+ __riscv_vse8_v_i8mf8(out + i, v0, avl);\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*4} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c\nnew file mode 100644\nindex 00000000000..103f4238c76\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-22.c\n@@ -0,0 +1,21 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2\" } */\n+\n+#include \"riscv_vector.h\"\n+\n+void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {\n+ size_t avl;\n+ if (m > 100)\n+ avl = __riscv_vsetvl_e16mf4(vl << 4);\n+ else\n+ avl = __riscv_vsetvl_e32mf2(vl >> 8);\n+ for (size_t i = 0; i < m; i++) {\n+ vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);\n+ v0 = __riscv_vadd_vv_i8mf8 (v0, v0, avl);\n+ __riscv_vse8_v_i8mf8(out + i, v0, avl);\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*4} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e8,\\s*mf8,\\s*t[au],\\s*m[au]} 2 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c\nnew file mode 100644\nindex 00000000000..66c90ac10e7\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-23.c\n@@ -0,0 +1,37 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2\" } */\n+\n+#include \"riscv_vector.h\"\n+\n+void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t k) {\n+ size_t avl;\n+ switch (m)\n+ {\n+ case 50:\n+ avl = __riscv_vsetvl_e16mf4(vl << 4);\n+ break;\n+ case 1:\n+ avl = __riscv_vsetvl_e32mf2(k);\n+ break;\n+ case 2:\n+ avl = __riscv_vsetvl_e64m1(vl);\n+ break;\n+ case 3:\n+ avl = __riscv_vsetvl_e32mf2(k >> 8);\n+ break;\n+ default:\n+ avl = __riscv_vsetvl_e32mf2(k + vl);\n+ break;\n+ }\n+ for (size_t i = 0; i < m; i++) {\n+ vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);\n+ v0 = __riscv_vadd_vv_i8mf8 (v0, v0, avl);\n+ v0 = __riscv_vadd_vv_i8mf8_tu (v0, v0, v0, avl);\n+ __riscv_vse8_v_i8mf8(out + i, v0, avl);\n+ }\n+}\n+\n+/* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*4} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {srli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*8} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli\\s+zero,\\s*[a-x0-9]+,\\s*e8,\\s*mf8,\\s*tu,\\s*m[au]} 5 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c\nindex f995e04aacc..13d09fc3fd1 100644\n--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-3.c\n@@ -18,4 +18,4 @@ void f(int8_t *base, 100 41658 100 41508 100 150 587k 2173 --:--:-- --:--:-- --:--:-- 598k int8_t *out, size_t vl, size_t m) {\n }\n \n /* { dg-final { scan-assembler-times {slli\\s+[a-x0-9]+,\\s*[a-x0-9]+,\\s*10} 1 { target { no-opts \"-O0\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n-/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n+/* { dg-final { scan-assembler-times {vsetvli} 2 { target { no-opts \"-O0\" no-opts \"-Os\" no-opts \"-Oz\" no-opts \"-g\" no-opts \"-funroll-loops\" } } } } */\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE