Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 Commit message: "RISC-V: Reorganize binary autovec testcases" > git rev-list --no-walk c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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possible","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525080624.1957802-1-poulhies@adacore.com/mbox/"},{"id":98873,"url":"https://patchwork.plctlab.org/api/1.2/patches/98873/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525080625.1957864-1-poulhies@adacore.com/","msgid":"<20230525080625.1957864-1-poulhies@adacore.com>","list_archive_url":null,"date":"2023-05-25T08:06:25","name":"[COMMITTED] ada: Expect Exceptional_Cases as a context for attribute Old","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525080625.1957864-1-poulhies@adacore.com/mbox/"},{"id":98876,"url":"https://patchwork.plctlab.org/api/1.2/patches/98876/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525080628.1957926-1-poulhies@adacore.com/","msgid":"<20230525080628.1957926-1-poulhies@adacore.com>","list_archive_url":null,"date":"2023-05-25T08:06:28","name":"[COMMITTED] ada: Missing warning on null-excluding array aggregate component","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525080628.1957926-1-poulhies@adacore.com/mbox/"},{"id":98881,"url":"https://patchwork.plctlab.org/api/1.2/patches/98881/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525083231.234-1-jinma@linux.alibaba.com/","msgid":"<20230525083231.234-1-jinma@linux.alibaba.com>","list_archive_url":null,"date":"2023-05-25T08:32:31","name":"RISC-V: In pipeline scheduling, insns should not be fusion in different BB blocks.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525083231.234-1-jinma@linux.alibaba.com/mbox/"},{"id":98902,"url":"https://patchwork.plctlab.org/api/1.2/patches/98902/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525090006.E0AA93857702@sourceware.org/","msgid":"<20230525090006.E0AA93857702@sourceware.org>","list_archive_url":null,"date":"2023-05-25T08:59:21","name":"tree-optimization/109791 - expand &x + off for niter compute","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230525090006.E0AA93857702@sourceware.org/mbox/"},{"id":98906,"url":"https://patchwork.plctlab.org/api/1.2/patches/98906/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/1a1cc437-12bd-b3e8-5fe4-7edb41625753@gmail.com/","msgid":"<1a1cc437-12bd-b3e8-5fe4-7edb41625753@gmail.com>","list_archive_url":null,"date":"2023-05-25T09:03:27","name":"RISC-V: Add autovec sign/zero extension and truncation.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/1a1cc437-12bd-b3e8-5fe4-7edb41625753@gmail.com/mbox/"}],"public":true,"mbox":"https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-05/mbox/"}]' + bundle_id=21 + git-pw bundle add 21 100116 Traceback (most recent call last): File "/usr/local/lib/python3.9/dist-packages/requests/models.py", line 971, in json return complexjson.loads(self.text, **kwargs) File "/usr/lib/python3.9/json/__init__.py", line 346, in loads return _default_decoder.decode(s) File "/usr/lib/python3.9/json/decoder.py", line 337, in decode obj, end = self.raw_decode(s, idx=_w(s, 0).end()) File "/usr/lib/python3.9/json/decoder.py", line 355, in raw_decode raise JSONDecodeError("Expecting value", s, err.value) from None json.decoder.JSONDecodeError: Expecting value: line 1 column 1 (char 0) During handling of the above exception, another exception occurred: Traceback (most recent call last): File "/usr/local/bin/git-pw", line 8, in sys.exit(cli()) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1130, in __call__ return self.main(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1657, in invoke return _process_result(sub_ctx.command.invoke(sub_ctx)) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1657, in invoke return _process_result(sub_ctx.command.invoke(sub_ctx)) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, **ctx.params) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 760, in invoke return __callback(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/decorators.py", line 26, in new_func return f(get_current_context(), *args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 418, in new_func return ctx.invoke(f, *args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 760, in invoke return __callback(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/git_pw/bundle.py", line 339, in add_cmd bundle = api.update('bundles', bundle_id, data) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 404, in update return _patch(url, data).json() File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 203, in _patch _handle_error('update', exc) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 125, in _handle_error LOG.error(exc.response.json()) File "/usr/local/lib/python3.9/dist-packages/requests/models.py", line 975, in json raise RequestsJSONDecodeError(e.msg, e.doc, e.pos) requests.exceptions.JSONDecodeError: Expecting value: line 1 column 1 (char 0) + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master fatal: refusing to merge unrelated histories + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series40716-patch100116 ++ git branch -a ++ grep 'series40716-patch100116$' + checkbranch= + checkbranchresult=null + '[' null = series40716-patch100116 ']' + git checkout -b series40716-patch100116 Switched to a new branch 'series40716-patch100116' ++ curl https://patchwork.plctlab.org/api/1.2/series/40716/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1381 100 1381 0 0 30021 0 --:--:-- --:--:-- --:--:-- 30021 + series_response='{"id":40716,"url":"https://patchwork.plctlab.org/api/1.2/series/40716/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=40716","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"RISC-V: Add RVV FNMA auto-vectorization support","date":"2023-05-29T06:50:56","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/40716/mbox/","cover_letter":null,"patches":[{"id":100116,"url":"https://patchwork.plctlab.org/api/1.2/patches/100116/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/","msgid":"<20230529065056.199188-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-05-29T06:50:56","name":"RISC-V: Add RVV FNMA auto-vectorization support","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ echo '{"id":40716,"url":"https://patchwork.plctlab.org/api/1.2/series/40716/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=40716","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"RISC-V: Add RVV FNMA auto-vectorization support","date":"2023-05-29T06:50:56","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/40716/mbox/","cover_letter":null,"patches":[{"id":100116,"url":"https://patchwork.plctlab.org/api/1.2/patches/100116/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/","msgid":"<20230529065056.199188-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-05-29T06:50:56","name":"RISC-V: Add RVV FNMA auto-vectorization support","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"100116,https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/"' + echo '"100116,https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"100116' ++ sed 's/"//g' + series_patch_id=100116 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++ git rev-parse HEAD + commitid_before=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 28950 100 28950 0 0 673k 0 --:--:-- --:--:-- --:--:-- 689k +++ bout='\''\'\'''\''Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 28950 100 28950 0 0 673k 0 --:--:-- --:--:-- --:--:-- 689k +++ bout='\''Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins16405488039916355908.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 28950 100 28950 0 0 673k 0 --:--:-- --:--:-- --:--:-- 689k +++ bout='\''Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins16405488039916355908.sh: line 154: ++: command not found ++ ++ declare -p berr /tmp/jenkins16405488039916355908.sh: line 155: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 28950 100 28950 0 0 673k 0 --:--:-- --:--:-- --:--:-- 689k +++ bout='\''Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 28950 100 28950 0 0 673k 0 --:--:-- --:--:-- --:--:-- 689k +++ bout='Applying: RISC-V: Add RVV FNMA auto-vectorization support error: sha1 information is lacking or useless (gcc/config/riscv/autovec.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Add RVV FNMA auto-vectorization support When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/7663/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/7663/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/7663/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/100116/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 966 100 426 100 540 10923 13846 --:--:-- --:--:-- --:--:-- 24769 {"id":8888,"url":"https://patchwork.plctlab.org/api/patches/100116/checks/8888/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-05-29T07:16:52.023442","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/7663/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/100116/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":100116,"url":"https://patchwork.plctlab.org/api/1.2/patches/100116/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20230529065056.199188-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-05-29T06:50:56","name":"RISC-V: Add RVV FNMA auto-vectorization support","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"72849adaebc2571cbc1108917c2dc3c040ad72ea","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"juzhe.zhong@rivai.ai","email":"juzhe.zhong@rivai.ai"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20230529065056.199188-1-juzhe.zhong@rivai.ai/mbox/","series":[{"id":40716,"url":"https://patchwork.plctlab.org/api/1.2/series/40716/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=40716","date":"2023-05-29T06:50:56","name":"RISC-V: Add RVV FNMA auto-vectorization support","version":1,"mbox":"https://patchwork.plctlab.org/series/40716/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/100116/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/100116/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:994d:0:b0:3d9:f83d:47d9 with SMTP id k13csp1320126vqr;\n Sun, 28 May 2023 23:51:40 -0700 (PDT)","from sourceware.org (ip-8-43-85-97.sourceware.org. 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mx.google.com;\n spf=pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","Received-SPF":"pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender) client-ip=8.43.85.97;","Authentication-Results":["mx.google.com;\n spf=pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as\n permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","sourceware.org;\n dmarc=none (p=none dis=none) header.from=rivai.ai","sourceware.org; spf=pass smtp.mailfrom=rivai.ai"],"X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org B6CCE3858D32","X-QQ-mid":"bizesmtp66t1685343059tph5wcxe","X-QQ-SSF":"01400000000000F0R000000A0000000","X-QQ-FEAT":"eeGIu46hDGhwsfDR0osQ8Exv699iT/f6kFe0ijW8Q1KTxlKHJw8UZ8n4BK9oh\n 1/kV1Bz89bd0gh87jsS+lo0lm4syChivbG6Sn9gWh+fD5YoQQyM0FGJQ0sU/NXUGwl+uRMP\n 1jJhmkf+sflVLcdVjDXwF94X1mGGfSfCehVi9VNGBQFaR3IOQWW+83bPUE7WjEcpOJ/s05o\n cRmyXDGIEEmTr8G8r68hY4+MNFl2IPFIIVdr1PxLGm56jebFtTOX94+headCOH5R5syPsXR\n jmyPw8EhlobQ5Vry4wzCsEvyOj+Flk4OerMZ0eSn4Z+rdBxrXEy0X6qRC7MjHsbyHnArZhc\n YiBicJK/x2e8aqp5z/FgVoQC03MPDsTLNlr1h1OVCeTqaEDV9HXg7Ufchf94eZv+1ge2QpD\n 2FKQS7AgM8E=","X-QQ-GoodBg":"2","X-BIZMAIL-ID":"5931725277954640257","From":"juzhe.zhong@rivai.ai","To":"gcc-patches@gcc.gnu.org","Cc":"kito.cheng@gmail.com, kito.cheng@sifive.com, palmer@dabbelt.com,\n palmer@rivosinc.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com,\n Juzhe-Zhong ","Subject":"[PATCH] RISC-V: Add RVV FNMA auto-vectorization support","Date":"Mon, 29 May 2023 14:50:56 +0800","Message-Id":"<20230529065056.199188-1-juzhe.zhong@rivai.ai>","X-Mailer":"git-send-email 2.36.3","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-QQ-SENDSIZE":"520","Feedback-ID":"bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0","X-Spam-Status":"No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE,\n RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1767210327291977901?=","X-GMAIL-MSGID":"=?utf-8?q?1767210327291977901?="},"content":"From: Juzhe-Zhong \n\nLike FMA, Add FNMA auto-vectorization support.\n\ngcc/ChangeLog:\n\n * config/riscv/autovec.md (fnma4): New pattern.\n (*fnma): Ditto.\n\ngcc/testsuite/ChangeLog:\n\n * gcc.target/riscv/rvv/autovec/ternop/ternop-4.c: New test.\n * gcc.target/riscv/rvv/autovec/ternop/ternop-5.c: New test.\n * gcc.target/riscv/rvv/autovec/ternop/ternop-6.c: New test.\n * gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c: New test.\n * gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c: New test.\n * gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c: New test.\n\n---\n gcc/config/riscv/autovec.md | 45 ++++++++\n .../riscv/rvv/autovec/ternop/ternop-4.c | 28 +++++\n .../riscv/rvv/autovec/ternop/ternop-5.c | 34 ++++++\n .../riscv/rvv/autovec/ternop/ternop-6.c | 33 ++++++\n .../riscv/rvv/autovec/ternop/ternop_run-4.c | 84 ++++++++++++++\n .../riscv/rvv/autovec/ternop/ternop_run-5.c | 104 ++++++++++++++++++\n .../riscv/rvv/autovec/ternop/ternop_run-6.c | 104 ++++++++++++++++++\n 7 files changed, 432 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c","diff":"diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md\nindex eff3e484fb4..20004a8af27 100644\n--- a/gcc/config/riscv/autovec.md\n+++ b/gcc/config/riscv/autovec.md\n@@ -606,3 +606,48 @@\n }\n [(set_attr \"type\" \"vimuladd\")\n (set_attr \"mode\" \"\")])\n+\n+;; -------------------------------------------------------------------------\n+;; ---- [INT] VMACC and VMADD\n+;; -------------------------------------------------------------------------\n+;; Includes:\n+;; - vnmsac\n+;; - vnmsub\n+;; -------------------------------------------------------------------------\n+\n+(define_expand \"fnma4\"\n+ [(parallel\n+ [(set (match_operand:VI 0 \"register_operand\" \"=vr\")\n+\t (minus:VI\n+\t (match_operand:VI 3 \"register_operand\" \" vr\")\n+\t (mult:VI\n+\t (match_operand:VI 1 \"register_operand\" \" vr\")\n+\t (match_operand:VI 2 \"register_operand\" \" vr\"))))\n+ (clobber (match_scratch:SI 4))])]\n+ \"TARGET_VECTOR\"\n+ {})\n+\n+(define_insn_and_split \"*fnma\"\n+ [(set (match_operand:VI 0 \"register_operand\" \"=vr, vr, ?&vr\")\n+\t(minus:VI\n+\t (match_operand:VI 3 \"register_operand\" \" vr, 0, vr\")\n+\t (mult:VI\n+\t (match_operand:VI 1 \"register_operand\" \" %0, vr, vr\")\n+\t (match_operand:VI 2 \"register_operand\" \" vr, vr, vr\"))))\n+ (clobber (match_scratch:SI 4 \"=r,r,r\"))]\n+ \"TARGET_VECTOR\"\n+ \"#\"\n+ \"&& reload_completed\"\n+ [(const_int 0)]\n+ {\n+ PUT_MODE (operands[4], Pmode);\n+ riscv_vector::emit_vlmax_vsetvl (mode, operands[4]);\n+ if (which_alternative == 2)\n+ emit_insn (gen_rtx_SET (operands[0], operands[3]));\n+ rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[0]};\n+ riscv_vector::emit_vlmax_ternary_insn (code_for_pred_minus_mul (mode),\n+\t\t\t\t\t riscv_vector::RVV_TERNOP, ops, operands[4]);\n+ DONE;\n+ }\n+ [(set_attr \"type\" \"vimuladd\")\n+ (set_attr \"mode\" \"\")])\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c\nnew file mode 100644\nindex 00000000000..22d11de89a1\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-4.c\n@@ -0,0 +1,28 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable\" } */\n+\n+#include \n+\n+#define TEST_TYPE(TYPE) \\\n+ __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dst, \\\n+\t\t\t\t\t TYPE *__restrict a, \\\n+\t\t\t\t\t TYPE *__restrict b, int n) \\\n+ { \\\n+ for (int i = 0; i < n; i++) \\\n+ dst[i] += -(a[i] * b[i]); \\\n+ }\n+\n+#define TEST_ALL() \\\n+ TEST_TYPE (int8_t) \\\n+ TEST_TYPE (uint8_t) \\\n+ TEST_TYPE (int16_t) \\\n+ TEST_TYPE (uint16_t) \\\n+ TEST_TYPE (int32_t) \\\n+ TEST_TYPE (uint32_t) \\\n+ TEST_TYPE (int64_t) \\\n+ TEST_TYPE (uint64_t)\n+\n+TEST_ALL ()\n+\n+/* { dg-final { scan-assembler-times {\\tvnmsub\\.vv} 8 } } */\n+/* { dg-final { scan-assembler-not {\\tvmv} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c\nnew file mode 100644\nindex 00000000000..6d5cf0a4da3\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-5.c\n@@ -0,0 +1,34 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable\" } */\n+\n+#include \n+\n+#define TEST_TYPE(TYPE) \\\n+ __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \\\n+\t\t\t\t\t TYPE *__restrict dest2, \\\n+\t\t\t\t\t TYPE *__restrict dest3, \\\n+\t\t\t\t\t TYPE *__restrict src1, \\\n+\t\t\t\t\t TYPE *__restrict src2, int n) \\\n+ { \\\n+ for (int i = 0; i < n; ++i) \\\n+ { \\\n+\tdest1[i] += -(src1[i] * src2[i]); \\\n+\tdest2[i] += src1[i] * dest1[i]; \\\n+\tdest3[i] += src2[i] * dest2[i]; \\\n+ } \\\n+ }\n+\n+#define TEST_ALL() \\\n+ TEST_TYPE (int8_t) \\\n+ TEST_TYPE (uint8_t) \\\n+ TEST_TYPE (int16_t) \\\n+ TEST_TYPE (uint16_t) \\\n+ TEST_TYPE (int32_t) \\\n+ TEST_TYPE (uint32_t) \\\n+ TEST_TYPE (int64_t) \\\n+ TEST_TYPE (uint64_t)\n+\n+TEST_ALL ()\n+\n+/* { dg-final { scan-assembler-times {\\tvnmsac\\.vv} 8 } } */\n+/* { dg-final { scan-assembler-not {\\tvmv} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c\nnew file mode 100644\nindex 00000000000..a2186e67222\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop-6.c\n@@ -0,0 +1,33 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv32gcv -mabi=ilp32d --param=riscv-autovec-preference=scalable\" } */\n+\n+#include \n+\n+#define TEST_TYPE(TYPE) \\\n+ __attribute__ ((noipa)) void ternop_##TYPE (TYPE *__restrict dest1, \\\n+\t\t\t\t\t TYPE *__restrict dest2, \\\n+\t\t\t\t\t TYPE *__restrict dest3, \\\n+\t\t\t\t\t TYPE *__restrict src1, \\\n+\t\t\t\t\t TYPE *__restrict src2, int n) \\\n+ { \\\n+ for (int i = 0; i < n; ++i) \\\n+ { \\\n+\tdest1[i] = -(src1[i] * src2[i]) + dest2[i]; \\\n+\tdest2[i] += src1[i] * dest1[i]; \\\n+\tdest3[i] += src2[i] * dest2[i]; \\\n+ } \\\n+ }\n+\n+#define TEST_ALL() \\\n+ TEST_TYPE (int8_t) \\\n+ TEST_TYPE (uint8_t) \\\n+ TEST_TYPE (int16_t) \\\n+ TEST_TYPE (uint16_t) \\\n+ TEST_TYPE (int32_t) \\\n+ TEST_TYPE (uint32_t) \\\n+ TEST_TYPE (int64_t) \\\n+ TEST_TYPE (uint64_t)\n+\n+TEST_ALL ()\n+\n+/* { dg-final { scan-assembler-times {\\tvmv} 8 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c\nnew file mode 100644\nindex 00000000000..379ab259816\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-4.c\n@@ -0,0 +1,84 @@\n+/* { dg-do run { target { riscv_vector } } } */\n+/* { dg-additional-options \"--param=riscv-autovec-preference=scalable\" } */\n+\n+#include \"ternop-4.c\"\n+\n+#define TEST_LOOP(TYPE, NUM) \\\n+ { \\\n+ TYPE array1_##NUM[NUM] = {}; \\\n+ TYPE array2_##NUM[NUM] = {}; \\\n+ TYPE array3_##NUM[NUM] = {}; \\\n+ TYPE array4_##NUM[NUM] = {}; \\\n+ for (int i = 0; i < NUM; ++i) \\\n+ { \\\n+\tarray1_##NUM[i] = (i & 1) + 5; \\\n+\tarray2_##NUM[i] = i - NUM / 3; \\\n+\tarray3_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tarray4_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tasm volatile(\"\" ::: \"memory\"); \\\n+ } \\\n+ ternop_##TYPE (array3_##NUM, array1_##NUM, array2_##NUM, NUM); \\\n+ for (int i = 0; i < NUM; i++) \\\n+ if (array3_##NUM[i] \\\n+\t != (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array4_##NUM[i])) \\\n+\t__builtin_abort (); \\\n+ }\n+\n+int __attribute__ ((optimize (0))) main ()\n+{\n+ TEST_LOOP (int8_t, 7)\n+ TEST_LOOP (uint8_t, 7)\n+ TEST_LOOP (int16_t, 7)\n+ TEST_LOOP (uint16_t, 7)\n+ TEST_LOOP (int32_t, 7)\n+ TEST_LOOP (uint32_t, 7)\n+ TEST_LOOP (int64_t, 7)\n+ TEST_LOOP (uint64_t, 7)\n+\n+ TEST_LOOP (int8_t, 16)\n+ TEST_LOOP (uint8_t, 16)\n+ TEST_LOOP (int16_t, 16)\n+ TEST_LOOP (uint16_t, 16)\n+ TEST_LOOP (int32_t, 16)\n+ TEST_LOOP (uint32_t, 16)\n+ TEST_LOOP (int64_t, 16)\n+ TEST_LOOP (uint64_t, 16)\n+\n+ TEST_LOOP (int8_t, 77)\n+ TEST_LOOP (uint8_t, 77)\n+ TEST_LOOP (int16_t, 77)\n+ TEST_LOOP (uint16_t, 77)\n+ TEST_LOOP (int32_t, 77)\n+ TEST_LOOP (uint32_t, 77)\n+ TEST_LOOP (int64_t, 77)\n+ TEST_LOOP (uint64_t, 77)\n+ \n+ TEST_LOOP (int8_t, 128)\n+ TEST_LOOP (uint8_t, 128)\n+ TEST_LOOP (int16_t, 128)\n+ TEST_LOOP (uint16_t, 128)\n+ TEST_LOOP (int32_t, 128)\n+ TEST_LOOP (uint32_t, 128)\n+ TEST_LOOP (int64_t, 128)\n+ TEST_LOOP (uint64_t, 128)\n+\n+ TEST_LOOP (int8_t, 15641)\n+ TEST_LOOP (uint8_t, 15641)\n+ TEST_LOOP (int16_t, 15641)\n+ TEST_LOOP (uint16_t, 15641)\n+ TEST_LOOP (int32_t, 15641)\n+ TEST_LOOP (uint32_t, 15641)\n+ TEST_LOOP (int64_t, 15641)\n+ TEST_LOOP (uint64_t, 15641)\n+ \n+ TEST_LOOP (int8_t, 795)\n+ TEST_LOOP (uint8_t, 795)\n+ TEST_LOOP (int16_t, 795)\n+ TEST_LOOP (uint16_t, 795)\n+ TEST_LOOP (int32_t, 795)\n+ TEST_LOOP (uint32_t, 795)\n+ TEST_LOOP (int64_t, 795)\n+ TEST_LOOP (uint64_t, 795)\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c\nnew file mode 100644\nindex 00000000000..f9bdf92cc2c\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-5.c\n@@ -0,0 +1,104 @@\n+/* { dg-do run { target { riscv_vector } } } */\n+/* { dg-additional-options \"--param=riscv-autovec-preference=scalable\" } */\n+\n+#include \"ternop-5.c\"\n+\n+#define TEST_LOOP(TYPE, NUM) \\\n+ { \\\n+ TYPE array1_##NUM[NUM] = {}; \\\n+ TYPE array2_##NUM[NUM] = {}; \\\n+ TYPE array3_##NUM[NUM] = {}; \\\n+ TYPE array4_##NUM[NUM] = {}; \\\n+ TYPE array5_##NUM[NUM] = {}; \\\n+ TYPE array6_##NUM[NUM] = {}; \\\n+ TYPE array7_##NUM[NUM] = {}; \\\n+ TYPE array8_##NUM[NUM] = {}; \\\n+ for (int i = 0; i < NUM; ++i) \\\n+ { \\\n+\tarray1_##NUM[i] = (i & 1) + 5; \\\n+\tarray2_##NUM[i] = i - NUM / 3; \\\n+\tarray3_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tarray6_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tarray4_##NUM[i] = NUM - NUM / 2 + i; \\\n+\tarray7_##NUM[i] = NUM - NUM / 2 + i; \\\n+\tarray5_##NUM[i] = NUM + i * 7; \\\n+\tarray8_##NUM[i] = NUM + i * 7; \\\n+\tasm volatile(\"\" ::: \"memory\"); \\\n+ } \\\n+ ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \\\n+\t\t array2_##NUM, NUM); \\\n+ for (int i = 0; i < NUM; i++) \\\n+ { \\\n+\tarray6_##NUM[i] \\\n+\t = (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array6_##NUM[i]); \\\n+\tif (array3_##NUM[i] != array6_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+\tarray7_##NUM[i] \\\n+\t = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \\\n+\tif (array4_##NUM[i] != array7_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+\tarray8_##NUM[i] \\\n+\t = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \\\n+\tif (array5_##NUM[i] != array8_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+ } \\\n+ }\n+\n+int __attribute__ ((optimize (0))) main ()\n+{\n+ TEST_LOOP (int8_t, 7)\n+ TEST_LOOP (uint8_t, 7)\n+ TEST_LOOP (int16_t, 7)\n+ TEST_LOOP (uint16_t, 7)\n+ TEST_LOOP (int32_t, 7)\n+ TEST_LOOP (uint32_t, 7)\n+ TEST_LOOP (int64_t, 7)\n+ TEST_LOOP (uint64_t, 7)\n+\n+ TEST_LOOP (int8_t, 16)\n+ TEST_LOOP (uint8_t, 16)\n+ TEST_LOOP (int16_t, 16)\n+ TEST_LOOP (uint16_t, 16)\n+ TEST_LOOP (int32_t, 16)\n+ TEST_LOOP (uint32_t, 16)\n+ TEST_LOOP (int64_t, 16)\n+ TEST_LOOP (uint64_t, 16)\n+\n+ TEST_LOOP (int8_t, 77)\n+ TEST_LOOP (uint8_t, 77)\n+ TEST_LOOP (int16_t, 77)\n+ TEST_LOOP (uint16_t, 77)\n+ TEST_LOOP (int32_t, 77)\n+ TEST_LOOP (uint32_t, 77)\n+ TEST_LOOP (int64_t, 77)\n+ TEST_LOOP (uint64_t, 77)\n+\n+ TEST_LOOP (int8_t, 128)\n+ TEST_LOOP (uint8_t, 128)\n+ TEST_LOOP (int16_t, 128)\n+ TEST_LOOP (uint16_t, 128)\n+ TEST_LOOP (int32_t, 128)\n+ TEST_LOOP (uint32_t, 128)\n+ TEST_LOOP (int64_t, 128)\n+ TEST_LOOP (uint64_t, 128)\n+\n+ TEST_LOOP (int8_t, 15641)\n+ TEST_LOOP (uint8_t, 15641)\n+ TEST_LOOP (int16_t, 15641)\n+ TEST_LOOP (uint16_t, 15641)\n+ TEST_LOOP (int32_t, 15641)\n+ TEST_LOOP (uint32_t, 15641)\n+ TEST_LOOP (int64_t, 15641)\n+ TEST_LOOP (uint64_t, 15641)\n+\n+ TEST_LOOP (int8_t, 795)\n+ TEST_LOOP (uint8_t, 795)\n+ TEST_LOOP (int16_t, 795)\n+ TEST_LOOP (uint16_t, 795)\n+ TEST_LOOP (int32_t, 795)\n+ TEST_LOOP (uint32_t, 795)\n+ TEST_LOOP (int64_t, 795)\n+ TEST_LOOP (uint64_t, 795)\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c\nnew file mode 100644\nindex 00000000000..c000e331084\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/ternop/ternop_run-6.c\n@@ -0,0 +1,104 @@\n+/* { dg-do run { target { riscv_vector } } } */\n+/* { dg-additional-options \"--param=riscv-autovec-preference=scalable\" } */\n+\n+#include \"ternop-6.c\"\n+\n+#define TEST_LOOP(TYPE, NUM) \\\n+ { \\\n+ TYPE array1_##NUM[NUM] = {}; \\\n+ TYPE array2_##NUM[NUM] = {}; \\\n+ TYPE array3_##NUM[NUM] = {}; \\\n+ TYPE array4_##NUM[NUM] = {}; \\\n+ TYPE array5_##NUM[NUM] = {}; \\\n+ TYPE array6_##NUM[NUM] = {}; \\\n+ TYPE array7_##NUM[NUM] = {}; \\\n+ TYPE array8_##NUM[NUM] = {}; \\\n+ for (int i = 0; i < NUM; ++i) \\\n+ { \\\n+\tarray1_##NUM[i] = (i & 1) + 5; \\\n+\tarray2_##NUM[i] = i - NUM / 3; \\\n+\tarray3_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tarray6_##NUM[i] = NUM - NUM / 3 - i; \\\n+\tarray4_##NUM[i] = NUM - NUM / 2 + i; \\\n+\tarray7_##NUM[i] = NUM - NUM / 2 + i; \\\n+\tarray5_##NUM[i] = NUM + i * 7; \\\n+\tarray8_##NUM[i] = NUM + i * 7; \\\n+\tasm volatile(\"\" ::: \"memory\"); \\\n+ } \\\n+ ternop_##TYPE (array3_##NUM, array4_##NUM, array5_##NUM, array1_##NUM, \\\n+\t\t 100 31574 100 31424 100 150 458k 2238 --:--:-- --:--:-- --:--:-- 460k array2_##NUM, NUM); \\\n+ for (int i = 0; i < NUM; i++) \\\n+ { \\\n+\tarray6_##NUM[i] \\\n+\t = (TYPE) (-(array1_##NUM[i] * array2_##NUM[i]) + array7_##NUM[i]); \\\n+\tif (array3_##NUM[i] != array6_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+\tarray7_##NUM[i] \\\n+\t = (TYPE) (array1_##NUM[i] * array6_##NUM[i] + array7_##NUM[i]); \\\n+\tif (array4_##NUM[i] != array7_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+\tarray8_##NUM[i] \\\n+\t = (TYPE) (array2_##NUM[i] * array7_##NUM[i] + array8_##NUM[i]); \\\n+\tif (array5_##NUM[i] != array8_##NUM[i]) \\\n+\t __builtin_abort (); \\\n+ } \\\n+ }\n+\n+int __attribute__ ((optimize (0))) main ()\n+{\n+ TEST_LOOP (int8_t, 7)\n+ TEST_LOOP (uint8_t, 7)\n+ TEST_LOOP (int16_t, 7)\n+ TEST_LOOP (uint16_t, 7)\n+ TEST_LOOP (int32_t, 7)\n+ TEST_LOOP (uint32_t, 7)\n+ TEST_LOOP (int64_t, 7)\n+ TEST_LOOP (uint64_t, 7)\n+\n+ TEST_LOOP (int8_t, 16)\n+ TEST_LOOP (uint8_t, 16)\n+ TEST_LOOP (int16_t, 16)\n+ TEST_LOOP (uint16_t, 16)\n+ TEST_LOOP (int32_t, 16)\n+ TEST_LOOP (uint32_t, 16)\n+ TEST_LOOP (int64_t, 16)\n+ TEST_LOOP (uint64_t, 16)\n+\n+ TEST_LOOP (int8_t, 77)\n+ TEST_LOOP (uint8_t, 77)\n+ TEST_LOOP (int16_t, 77)\n+ TEST_LOOP (uint16_t, 77)\n+ TEST_LOOP (int32_t, 77)\n+ TEST_LOOP (uint32_t, 77)\n+ TEST_LOOP (int64_t, 77)\n+ TEST_LOOP (uint64_t, 77)\n+\n+ TEST_LOOP (int8_t, 128)\n+ TEST_LOOP (uint8_t, 128)\n+ TEST_LOOP (int16_t, 128)\n+ TEST_LOOP (uint16_t, 128)\n+ TEST_LOOP (int32_t, 128)\n+ TEST_LOOP (uint32_t, 128)\n+ TEST_LOOP (int64_t, 128)\n+ TEST_LOOP (uint64_t, 128)\n+\n+ TEST_LOOP (int8_t, 15641)\n+ TEST_LOOP (uint8_t, 15641)\n+ TEST_LOOP (int16_t, 15641)\n+ TEST_LOOP (uint16_t, 15641)\n+ TEST_LOOP (int32_t, 15641)\n+ TEST_LOOP (uint32_t, 15641)\n+ TEST_LOOP (int64_t, 15641)\n+ TEST_LOOP (uint64_t, 15641)\n+\n+ TEST_LOOP (int8_t, 795)\n+ TEST_LOOP (uint8_t, 795)\n+ TEST_LOOP (int16_t, 795)\n+ TEST_LOOP (uint16_t, 795)\n+ TEST_LOOP (int32_t, 795)\n+ TEST_LOOP (uint32_t, 795)\n+ TEST_LOOP (int64_t, 795)\n+ TEST_LOOP (uint64_t, 795)\n+\n+ return 0;\n+}\n","prefixes":[]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE