Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 6445f1224509861f2d471a66134b98f26290586e (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 6445f1224509861f2d471a66134b98f26290586e # timeout=10 Commit message: "RISC-V: Allow vector constants in riscv_const_insns." > git rev-list --no-walk 6445f1224509861f2d471a66134b98f26290586e # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | ID | 21 | | Name | gcc-patch_2023-05 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-05/ | | Owner | patchwork-bot | | Project | gcc-patch | | Public | True | | Patches | 88946 [(pushed)] libsanitizer: link hwasan against lsan library | | | 88948 [(pushed)] hwasan: adjust wording in expected output in tests | | | 88955 MATCH: Port CLRSB part of builtin_zero_pattern | | | 88956 PHIOPT: small refactoring of match_simplify_replacement. | | | 88957 PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 88960 [Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag. | | | 88972 [COMMITTED] vrange_storage overhaul | | | 88970 [COMMITTED] Remove irange::{min,max,kind}. | | | 88969 [COMMITTED] Remove irange::tree_{lower,upper}_bound. | | | 88971 [COMMITTED] Various cleanups in vr-values.cc towards ranger API. | | | 88977 [COMMITTED] Convert get_legacy_range in bounds_of_var_in_loop to irange API. | | | 88974 [COMMITTED] Merge irange::union/intersect into irange_union/intersect. | | | 88980 [COMMITTED] Conversion to irange wide_int API. | | | 88975 [COMMITTED] Replace vrp_val* with wide_ints. | | | 88978 [COMMITTED] Rewrite bounds_of_var_in_loop() to use ranges. | | | 88976 [COMMITTED] Convert internal representation of irange to wide_ints. | | | 88973 [COMMITTED] Cleanup irange::set. | | | 88979 [COMMITTED] Inline irange::set_nonzero. | | | 88981 [COMMITTED] Remove unused friends in int_range<>. | | | 88984 [committed] libgcc pru: Define TARGET_HAS_NO_HW_DIVIDE | | | 89047 [committed] Enable LRA on several ports | | | 89048 [committed] Convert xstormy16 to LRA | | | 89080 RISC-V: Name newly added flags in changelog | | | 89081 Fortran: overloading of intrinsic binary operators [PR109641] | | | 89082 PHIOPT: Update comment about what the pass now does | | | 89168 [1/2] c++: potentiality of templated memfn call [PR109480] | | | 89167 [2/2] c++: non-dep init folding and access checking [PR109480] | | | 89176 [pushed] c++: array DMI and member fn [PR109666] | | | 89185 [pushed] ubsan: ubsan_maybe_instrument_array_ref tweak | | | 89207 c++: Move -Wdangling-reference to -Wextra [PR109642] | | | 89266 i386: Fix up handling of debug insns in STV [PR109676] | | | 89284 libstdc++: Shut up -Wattribute-alias warning [PR109694] | | | 89286 libstdc++: Regenerate baseline_symbols.txt files for Linux | | | 89300 [i386] Fix testcases for emulated scatter | | | 89301 tree-optimization/109672 - properly check emulated plus during vect | | | 89330 RISC-V: fix build issue with gcc 4.9.x | | | 89343 [(pushed)] docs: port documentation of VRP params | | | 89344 [pushed] c++: Add testcase for already fixed PR [PR109506] | | | 89396 release the sorted FDE array when deregistering a frame [PR109685] | | | 89397 do not tailcall __sanitizer_cov_trace_pc [PR90746] | | | 89403 c++: Fix up VEC_INIT_EXPR gimplification after r12-7069 | | | 89407 rs6000: Add builtins for IEEE 128-bit floating point values | | | 89443 [1/2] c++: std::variant slow to compile [PR109678] | | | 89444 [2/2] c++: look for empty base at specific offset [PR109678] | | | 89445 [pushed] c++: less invalidate_class_lookup_cache | | | 89446 [Committed,11/11] RISC-V: Table A.6 conformance tests | | | 89460 c++: satisfaction of non-dep member alias template-id | | | 89463 [COMMITTED] tree-optimization: [PR109702] MATCH: Fix a ? func(a) : N patterns | | | 89488 [pushed] c++: simplify member template substitution | | | 89514 c++: wrong std::is_convertible with cv-qual fn [PR109680] | | | 89515 Add stats to simple_dce_from_worklist | | | 89539 [v2,1/1] libstdc++: Set _M_string_length before calling _M_dispose() [PR109703] | | | 89541 [1/2] Factor out copy_phi_args from gimple_duplicate_sese_tail and remove_forwarder_block. | | | 89542 [2/2] PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 89557 [pushed] c++: fix TTP level reduction cache | | | 89662 [(pushed)] clang warning: warning: private field 'm_gc' is not used [-Wunused-private-field] | | | 89680 [GCC,11] tree-optimization/109473 - fix type mismatch in reduction vectorization | | | 89701 riscv: Don't add -latomic with -pthread | | | 89712 Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS' (was: Update testsuite to run with slim LTO) | | | 89720 Remove type from vrange_storage::equal_p. | | | 89738 [10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes | | | 89740 More last_stmt removal | | | 89741 Rename last_stmt to last_nondebug_stmt | | | 89753 c++: ahead of time variable template-id coercion [PR89442] | | | 89768 [(pushed)] riscv: fix error: control reaches end of non-void function | | | 89769 [v2,03/22] arm: [MVE intrinsics] Rework vreinterpretq | | | 89775 rs6000: vec_cmpne confusing implementation | | | 89783 [1/2] aarch64: Rename abi_break parameters [PR109661] | | | 89784 [2/2] aarch64: Fix ABI handling of aligned enums [PR109661] | | | 89798 [COMMITTED] Allow varying ranges of unknown types in irange::verify_range [PR109711] | | | 89802 [gcc13,backport] RISCV: Inline subword atomic ops | | | 89823 libstdc++: Fix up abi.exp FAILs on powerpc64-linux | | | 89830 libstdc++: Fix up abi.exp FAILs on powerpc64le-linux | | | 89833 [pushed] c++: over-eager friend matching [PR109649] | | | 89859 [PUSHED,gcc-11] extend.texi: replace @itemx not preceded by @item. | | | 89869 PHIOPT: Improve replace_phi_edge_with_variable's dce_ssa_names slightly | | | 89870 [1/2] Move copy_phi_arg_into_existing_phi to common location and use it | | | 89871 [PATCHv2,2/2] PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 89881 [committed] CRIS-LRA: Fix uses of reload_in_progress | | | 89883 [committed] CRIS-LRA: Define TARGET_SPILL_CLASS | | | 89884 [committed] CRIS: peephole2 an "and" with a contiguous "one-sided" sequences of 1s | | | 89902 [v2] Canonicalize vec_merge when mask is constant. | | | 89921 [V3] RISC-V: Enable basic RVV auto-vectorization support. | | | 89922 [powerpc] Add a peephole2 to eliminate redundant move from VSX_REGS to GENERAL_REGS when it's from memory. | | | 89936 RISC-V: Handle multi-lib path correclty for linux | | | 89939 tree-optimization/109724 - new testcase | | | 89951 libgomp C++ testsuite: Use 'lang_include_flags' instead of 'libstdcxx_includes' (was: [PATCH] libgomp: Add openacc_{cuda,cublas,cudart} effective targets and use them in openacc testsuite) | | | 89954 [v2] RISC-V: Handle multi-lib path correclty for linux | | | 89995 RISC-V: Legitimise the const0_rtx for RVV indexed load/store | | | 90000 [PATCHv2,rs6000] Splat vector small V2DI constants with ISA 2.07 instructions [PR104124] | | | 90007 [v2] RISC-V: Legitimise the const0_rtx for RVV indexed load/store | | | 90040 tree-optimization/109721 - emulated vectors | | | 90050 i386: Improve index_register_operand predicate | | | 90056 [committed] libstdc++: Document new library version in manual | | | 90059 [libstdc++] use strtold for from_chars even without locale | | | 90060 [vxworks,testsuite,aarch64] use builtin in pred-not-gen-4.c | | | 90082 [V4] VECT: Add decrement IV iteration loop control by variable amount support | | | 90090 [RFC] tree-optimization/104475 - bogus -Wstringop-overflow | | | 90139 c++: some assorted code improvements | | | 90140 c++: fix pretty printing of 'alignof' vs '__alignof__' [PR85979] | | | 90153 RISC-V: Add bext pattern for ZBS | | | 90154 RISC-V: Fix CTZ unnecessary sign extension [PR #106888] | | | 90174 i386: Tighten ashift to lea splitter operand predicates [PR109733] | | | 90218 libffi: fix handling of homogeneous float128 structs [PR109447] | | | 90255 PHIOPT: Fix diamond case of match_simplify_replacement | | | 90263 MATCH: Add ABSU == 0 to a == 0 simplification | | | 90269 [pushed] Revert "c++: restore instantiate_decl assert" | | | 90292 RISC-V: Fix PR109615 | | | 90307 [V2] RISC-V: Fix PR109615 | | | 90323 [committed] builtins: Fix comment typo mpft_t -> mpfr_t | | | 90327 gimple-range-op: Improve handling of sqrt ranges | | | 90349 [01/23] arm: [MVE intrinsics] add binary_round_lshift shape | | | 90348 [02/23] arm: [MVE intrinsics] factorize vqrshlq vrshlq | | | 90360 [03/23] arm: [MVE intrinsics] rework vrshlq vqrshlq | | | 90351 [04/23] arm: [MVE intrinsics] factorize vqshlq vshlq | | | 90356 [05/23] arm: [MVE intrinsics] rework vqrdmulhq | | | 90347 [06/23] arm: [MVE intrinsics] factorize vabdq | | | 90355 [07/23] arm: [MVE intrinsics] rework vabdq | | | 90354 [08/23] arm: [MVE intrinsics] add binary_lshift shape | | | 90353 [09/23] arm: [MVE intrinsics] add support for MODE_r | | | 90350 [10/23] arm: [MVE intrinsics] add binary_lshift_r shape | | | 90352 [11/23] arm: [MVE intrinsics] add unspec_mve_function_exact_insn_vshl | | | 90368 [12/23] arm: [MVE intrinsics] rework vqshlq vshlq | | | 90361 [13/23] arm: [MVE intrinsics] factorize vmaxq vminq | | | 90365 [14/23] arm: [MVE intrinsics] rework vmaxq vminq | | | 90364 [15/23] arm: [MVE intrinsics] add binary_rshift_narrow shape | | | 90366 [16/23] arm: [MVE intrinsics] factorize vshrntq vshrnbq vrshrnbq vrshrntq vqshrnbq vqshrntq vqrshrnbq vqrshrntq | | | 90367 [17/23] arm: [MVE intrinsics] rework vshrnbq vshrntq vrshrnbq vrshrntq vqshrnbq vqshrntq vqrshrnbq vqrshrntq | | | 90358 [18/23] arm: [MVE intrinsics] add binary_rshift_narrow_unsigned shape | | | 90362 [19/23] arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt vqshrunb vqshrunt | | | 90363 [20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntq | | | 90357 [21/23] arm: [MVE intrinsics] add binary_rshift shape | | | 90359 [22/23] arm: [MVE intrinsics] factorize vsrhrq vrshrq | | | 90369 [23/23] arm: [MVE intrinsics] rework vshrq vrshrq | | | 90370 Support parallel testing in libgomp, part I [PR66005] | | | 90372 Support parallel testing in libgomp, part II [PR66005] | | | 90373 tree: Fix up save_expr [PR52339] | | | 90393 [1/8] MIPS: Add basic support for mips16e2 | | | 90391 [2/8] MIPS: Add MOVx instructions support for mips16e2 | | | 90392 [3/8] MIPS: Add instruction about global pointer register for mips16e2 | | | 90394 [4/8] MIPS: Add bitwise instructions for mips16e2 | | | 90388 [5/8] MIPS: Add LUI instruction for mips16e2 | | | 90389 [6/8] MIPS: Add load/store word left/right instructions for mips16e2 | | | 90395 [7/8] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 | | | 90396 [8/8] MIPS: Add CACHE instruction for mips16e2 | | | 90409 GCN: Silence unused-variable warning | | | 90426 i386: Introduce mulv2si3 instruction | | | 90428 tree-optimization/109735 - conversion for vectorized pointer-diff | | | 90438 i386: Rename index_register_operand predicate to register_no_SP_operand | | | 90446 RISC-V: Fix PR109748 | | | 90453 [V4] RISC-V: Enable basic RVV auto-vectorization support. | | | 90455 [V2] RISC-V: Fix incorrect demand info merge in local vsetvli optimization [PR109748] | | | 90469 [V5] RISC-V: Enable basic RVV auto-vectorization support. | | | 90474 Move substitute_and_fold over to use simple_dce_from_worklist | | | 90482 [v6,1/9] RISC-V: autovec: Add new predicates and function prototypes | | | 90483 [v6,2/9] RISC-V: autovec: Export policy functions to global scope | | | 90490 [v6,3/9] RISC-V:autovec: Add auto-vectorization support functions | | | 90489 [v6,4/9] RISC-V:autovec: Add target vectorization hooks | | | 90484 [v6,5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store | | | 90495 [v6,6/9] RISC-V:autovec: Add autovectorization tests for add & sub | | | 90493 [v6,7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2. | | | 90491 [v6,8/9] RISC-V:autovec: Add autovectorization tests for binary integer | | | 90494 [v6,9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv. | | | 90498 [01/10] arm: [MVE intrinsics] add unary shape | | | 90499 [02/10] arm: [MVE intrinsics] factorize several unary operations | | | 90502 [03/10] arm: [MVE intrinsics] rework vabsq vnegq vclsq vclzq, vqabsq, vqnegq | | | 90506 [04/10] arm: [MVE intrinsics] rework vrndq vrndaq vrndmq vrndnq vrndpq vrndxq | | | 90500 [05/10] arm: [MVE intrinsics] add binary_move_narrow and binary_move_narrow_unsigned shapes | | | 90505 [06/10] arm: [MVE intrinsics] factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq | | | 90507 [07/10] arm: [MVE intrinsics] rework vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq | | | 90504 [08/10] arm: [MVE intrinsics] add binary_widen_n shape | | | 90501 [09/10] arm: [MVE intrinsics] factorize vshllbq vshlltq | | | 90503 [10/10] arm: [MVE intrinsics] rework vshllbq vshlltq | | | 90508 ira: Don't create copies for earlyclobbered pairs | | | 90511 Makefile.in: clean up match.pd-related dependencies | | | 90514 [RFC] RISC-V: Add proposed Ztso atomic mappings | | | 90523 c++: list CTAD and resolve_nondeduced_context [PR106214] | | | 90524 c++: goto entering scope of obj w/ non-trivial dtor [PR103091] | | | 90552 c++: parenthesized -> resolving to static member [PR98283] | | | 90581 gimple-range-op: Improve handling of sin/cos ranges | | | 90624 [committed] CRIS: peephole2 a lsrq into a lslq+lsrq pair | | | 90631 [committed] CRIS: peephole2 a move of constant followed by and of same register | | | 90633 [committed] CRIS: peephole2 an add into two addq or subq | | | 90657 ISC-V: Enable basic RVV auto-vectorization support. | | | 90658 [V6] RISC-V: Enable basic RVV auto-vectorization support. | | | 90670 [fortran] PR109662 Namelist input with comma after name accepted | | | 90671 [V7] RISC-V: Enable basic RVV auto-vectorization support. | | | 90710 [1/2,RISC-V] disable shrink-wrap-separate if zcmp enabled. | | | 90711 [2/2,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 90729 RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 90734 hurd: Add multilib paths for gnu-x86_64 | | | 90736 hurd: Ad default-pie and static-pie support | | | 90755 Don't call emit_clobber in lower-subreg.cc's resolve_simple_move. | | | 90758 [x86_64] Introduce insvti_highpart define_insn_and_split. | | | 90778 nvptx: Add suppport for __builtin_nvptx_brev instrinsic. | | | 90781 Add RTX codes for BITREVERSE and COPYSIGN. | | | 90783 Pushed: [PATCH v2] LoongArch: Enable shrink wrapping | | | 90785 [libgcc] Add bit reversal functions __bitrev[qhsd]i2. | | | 90799 [committed] Partial revert of recent changes | | | 90817 [1/3] PHIOPT: Add diamond bb form to factor_out_conditional_conversion | | | 90816 [2/3] PHIOPT: Loop over calling factor_out_conditional_conversion | | | 90815 [3/3] PHIOPT: factor out unary operations instead of just conversions | | | 90819 [1/3] PHIOPT: Add diamond bb form to factor_out_conditional_conversion | | | 90824 [pushed] wwwdocs: onlinedocs: Fix markup | | | 90851 Fix aarch64/109762: push_options/push_options does not work sometimes | | | 90876 [GCC,13] Fix aarch64/109762: push_options/push_options does not work sometimes | | | 90887 MATCH: Move `a <= CST1 ? MAX : a` optimization to match | | | 90914 [V2,vect] Enhance NARROW FLOAT_EXPR vectorization by truncating integer to lower precision. | | | 90929 RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization | | | 90936 Add a != MIN/MAX_VALUE_CST ? CST-+1 : a to minmax_from_comparison | | | 91031 RISC-V: Update RVV integer compare simplification comments | | | 91038 [v4] libgfortran: Replace mutex with rwlock | | | 91153 xtensa: Make full transition to LRA | | | 91165 libgm2: Remove 'autogen.sh' (was: libgm2: Adjust 'autogen.sh' to 'ACLOCAL_AMFLAGS', and simplify) | | | 91167 [v2] RISC-V: Add bext pattern for ZBS | | | 91168 [v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] | | | 91176 [committed] Fix minor length computation on stormy16 | | | 91185 [committed] RISC-V: Factor out vector manager code in vsetvli insertion pass. [NFC] | | | 91186 [committed] RISC-V: Improve portability of testcases | | | 91187 [V2] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 91189 [v2] xtensa: Make full transition to LRA | | | 91219 [COMMITTED] Fix pr81192.c for int16 targets | | | 91222 [1/3] genmatch: clean up emit_func | | | 91221 [2/3] genmatch: clean up showUsage | | | 91220 [3/3] genmatch: fixup get_out_file | | | 91311 [PUSHED] Fix cfg maintenance after inlining in AutoFDO | | | 91314 [V3] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 91346 RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773] | | | 91352 [v5] libgfortran: Replace mutex with rwlock | | | 91387 [committed,gcc,12] Fix ICE related to implicit access attributes for VLA arguments [PR105660] | | | 91388 [1/6] aarch64: Fix move-after-intrinsic function-body tests | | | 91390 [2/6] aarch64: Allow moves after tied-register intrinsics | | | 91389 [3/6] aarch64: Relax ordering requirements in SVE dup tests | | | 91391 [4/6] aarch64: Relax predicate register matches | | | 91392 [5/6] aarch64: Relax FP/vector register matches | | | 91393 [6/6] aarch64: Avoid hard-coding specific register allocations | | | 91396 Detect bswap + rotate for byte permutation in pass_bswap. | | | 91448 c++: Reject attributes without arguments used as pack expansion [PR109756] | | | 91449 c++: Reject pack expansion of assume attribute [PR109756] | | | 91455 tree-ssa-ccp, wide-int: Fix up handling of [LR]ROTATE_EXPR in bitwise ccp [PR109778] | | | 91460 i386: Honour -mdirect-extern-access when calling __fentry__ | | | 91461 Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS') | | | 91469 RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | | | 91495 [committed] testsuite: Add further testcase for already fixed PR [PR109778] | | | 91498 [committed] mux-utils.h: Fix a comment typo | | | 91552 [V2] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | | | 91555 [RFC] c-family: Implement __has_feature and __has_extension [PR60512] | | | 91558 [01/16] arm: [MVE intrinsics] add binary_maxvminv shape | | | 91572 [02/16] arm: [MVE intrinsics] add binary_maxavminav shape | | | 91557 [03/16] arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_p | | | 91565 [04/16] arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq | | | 91579 [05/16] arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavq | | | 91559 [06/16] arm: add smax/smin expanders for v*hf | | | 91576 [07/16] arm: [MVE intrinsics] factorize vmaxnmq vminnmq | | | 91568 [08/16] arm: [MVE intrinsics] rework vmaxnmq vminnmq | | | 91577 [09/16] arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq | | | 91564 [10/16] arm: [MVE intrinsics] add support for mve_q_p_f | | | 91571 [11/16] arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvq | | | 91560 [12/16] arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq | | | 91573 [13/16] arm: [MVE intrinsics] rework vmaxnmaq vminnmaq | | | 91574 [14/16] arm: [MVE intrinsics] add binary_maxamina shape | | | 91578 [15/16] arm: [MVE intrinsics] factorize vmaxaq vminaq | | | 91567 [16/16] arm: [MVE intrinsics] rework vmaxaq vminaq | | | 91580 libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91582 libgomp testsuite: Only use 'blddir' if set (was: libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91583 libgomp testsuite: Use 'lang_test_file_found' instead of 'lang_test_file' (was: libgomp testsuite: Only use 'blddir' if set (was: libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91589 libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91592 libgomp C++, Fortran testsuites: Resolve 'lang_test_file_found' first (was: libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91595 libgomp testsuite: Get rid of 'lang_test_file_found' (was: libgomp C++, Fortran testsuites: Resolve 'lang_test_file_found' first (was: libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91598 [committed] Eliminate more comparisons on the H8 port | | | 91636 [fortran] PR97122 - Spurious FINAL ... must be in the specification part of a MODULE | | | 91638 vect: Missed opportunity to use [SU]ABD | | | 91640 [fortran] PR103716 - [10/11/12/13/14 Regression] ICE in gimplify_expr, at gimplify.c:15964 | | | 91642 vect: Missed opportunity to use [SU]ABD | | | 91649 rtl: AArch64: New RTL for ABD | | | 91656 c++: noexcept-spec from nested class confusion [PR109761] | | | 91655 c++: error-recovery ICE with unstable satisfaction [PR109752] | | | 91705 [1/2] aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.exp | | | 91706 [2/2] aarch64: Improve register allocation for lane instructions | | | 91711 [v2,06/16] arm: add smax/smin expanders for v*hf | | | 91724 c++, v2: Reject attributes without arguments used as pack expansion [PR109756] | | | 91730 configure: Implement --enable-host-pie | | | 91731 [committed] libstdc++: Fix pretty printers and add tests | | | 91784 [committed] CRIS: Fix ccmode typo in cris_postdbr_cmpelim | | | 91787 Fixes and workarounds for warnings during autoprofiledbootstrap build | | | 91795 RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0. | | | 91834 RISC-V: Support const series vector for RVV auto-vectorization | | | 91835 [V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0. | | | 91857 _Hashtable implementation cleanup | | | 91865 [Committed] New testcase | | | 91913 Var-Tracking: Leverage pointer_mux for decl_or_value | | | 91936 Testsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture-init' (was: Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'to | | | 91977 x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR. | | | 92006 ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches | | | 92013 fix radix sort on 32bit platforms [PR109670] | | | 92032 [RFC] libstdc++: Do not use pthread_mutex_clocklock with ThreadSanitizer | | | 92051 [committed] Fix a couple constraints on the H8 in preparation for LRA conversion | | | 92065 [v2] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92080 RISC-V: Add basic vec_init support for RVV auto-vectorizaiton | | | 92085 [01/20] arm: [MVE intrinsics] factorize vcmp | | | 92105 [02/20] arm: [MVE intrinsics] add cmp shape | | | 92119 [03/20] arm: [MVE intrinsics] rework vcmp | | | 92096 [04/20] arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q | | | 92118 [05/20] arm: [MVE intrinsics] rework vrev16q vrev32q vrev64q | | | 92094 [06/20] arm: [MVE intrinsics] factorize vdupq | | | 92101 [07/20] arm: [MVE intrinsics] add unary_n shape | | | 92110 [08/20] arm: [MVE intrinsics] rework vdupq | | | 92091 [09/20] arm: [MVE intrinsics] factorize vaddvq | | | 92102 [10/20] arm: [MVE intrinsics] add unary_int32 shape | | | 92087 [11/20] arm: [MVE intrinsics] rework vaddvq | | | 92116 [12/20] arm: [MVE intrinsics] factorize vaddvaq | | | 92113 [13/20] arm: [MVE intrinsics] add unary_int32_acc shape | | | 92103 [14/20] arm: [MVE intrinsics] rework vaddvaq | | | 92099 [15/20] arm: [MVE intrinsics] add unary_acc shape | | | 92104 [16/20] arm: [MVE intrinsics] factorize vaddlvq | | | 92108 [17/20] arm: [MVE intrinsics] rework vaddlvq | | | 92107 [18/20] arm: [MVE intrinsics] factorize vmovlbq vmovltq | | | 92106 [19/20] arm: [MVE intrinsics] add unary_widen shape | | | 92098 [20/20] arm: [MVE intrinsics] rework vmovlbq vmovltq | | | 92120 Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI | | | 92163 [take,#3] match.pd: Simplify popcount/parity of bswap/rotate. | | | 92170 [pushed,1/2] c++: always check consteval address | | | 92171 [pushed,2/2] c++: be stricter about constinit [CWG2543] | | | 92175 [v3] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92176 riscv: Add vectorized binops and insn_expander helpers. | | | 92179 riscv: Clarify vlmax and length handling. | | | 92177 riscv: Split off shift patterns for autovectorization. | | | 92178 riscv: Add autovectorization tests for binary integer | | | 92181 c++: converted lambda as template argument [PR83258, ...] | | | 92183 [V5,2/2] PR target/105325: Fix memory constraints for power10 fusion. | | | 92190 RISC-V: Remove masking third operand of rotate instructions | | | 92200 [committed] MAINTAINERS: Add myself to write after approval | | | 92212 [v2] Fortran: Narrow return types [PR78798] | | | 92213 [1/2] Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624] | | | 92214 [2/2] Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTION | | | 92252 Add another new testcase | | | 92253 rs6000: Fix __builtin_vec_xst_trunc definition | | | 92278 [x86_64] Use [(const_int 0)] idiom consistently in i386.md | | | 92291 i386: Add missing vector extend patterns [PR92658] | | | 92294 [pushed] c++: adjust conversion diagnostics | | | 92305 [v2] c++: wrong std::is_convertible with cv-qual fn [PR109680] | | | 92307 match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y) | | | 92346 [v4] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92348 MAINTAINERS: Add myself to write after approval | | | 92349 [commited] MAINTAINERS: Add myself to write after approval | | | 92351 [committed,v2] RISC-V: Support const series vector for RVV auto-vectorization | | | 92355 [V5] VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV. | | | 92366 [v5] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92433 mklog.py: Add --commit option. | | | 92445 [V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization | | | 92452 [V6] VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV. | | | 92472 [1/2] PR gcc/98350:Add a param to control the length of the chain with FMA in reassoc pass | | | 92471 [2/2] Add a tune option to control the length of the chain with FMA | | | 92473 [v2] RISC-V: Add vectorized binops and insn_expander helpers. | | | 92474 [v2] RISC-V: Add autovectorization tests for binary integer, operations. | | | 92475 [v2] RISC-V: Clarify vlmax and length handling. | | | 92476 [v2] RISC-V: Split off shift patterns for autovectorization. | | | 92482 [committed] VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV | | | 92483 arm: Fix ICE due to infinite splitting [PR109800] | | | 92485 aarch64: Remove alignment assertions [PR109661] | | | 92488 [committed] libstdc++: Fix std::abs(__float128) for -NaN and -0.0 [PR109758] | | | 92508 [01/24] arm: [MVE intrinsics] factorize vaddlvaq | | | 92509 [02/24] arm: [MVE intrinsics] add unary_widen_acc shape | | | 92515 [03/24] arm: [MVE intrinsics] rework vaddlvaq | | | 92514 [04/24] arm: [MVE intrinsics] add binary_acc_int32 shape | | | 92513 [05/24] arm: [MVE intrinsics] factorize vmladav vmladavx vmlsdav vmlsdavx vmladava vmladavax vmlsdava vmlsdavax | | | 92521 [06/24] arm: [MVE intrinsics] rework vmladavq vmladavxq vmlsdavq vmlsdavxq | | | 92511 [07/24] arm: [MVE intrinsics] add binary_acca_int32 shape | | | 92547 [08/24] arm: [MVE intrinsics] rework vmladavaq vmladavaxq vmlsdavaq vmlsdavaxq | | | 92516 [09/24] arm: [MVE intrinsics] factorize vabavq | | | 92524 [10/24] arm: [MVE intrinsics] rework vabavq | | | 92523 [11/24] arm: [MVE intrinsics] add binary_acc_int64 shape | | | 92512 [12/24] arm: [MVE intrinsics] factorize vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq | | | 92518 [13/24] arm: [MVE intrinsics] rework vmlaldavq vmlaldavxq vmlsldavq vmlsldavxq | | | 92522 [14/24] arm: [MVE intrinsics] factorize vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq | | | 92544 [15/24] arm: [MVE intrinsics] rework vrmlaldavhq vrmlaldavhxq vrmlsldavhq vrmlsldavhxq | | | 92517 [16/24] arm: [MVE intrinsics] add binary_acca_int64 shape | | | 92542 [17/24] arm: [MVE intrinsics] factorize vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq | | | 92538 [18/24] arm: [MVE intrinsics] rework vmlaldavaq vmlaldavaxq vmlsldavaq vmlsldavaxq | | | 92532 [19/24] arm: [MVE intrinsics] add ternary shape | | | 92519 [20/24] arm: [MVE intrinsics] factorize vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq vqrdmladhq vqrdmladhxq vqrdmlsdhq vqrdmlsdhxq | | | 92530 [21/24] arm: [MVE intrinsics] rework vqrdmladhq vqrdmladhxq vqrdmlsdhq vqrdmlsdhxq vqdmladhq vqdmladhxq vqdmlsdhq vqdmlsdhxq | | | 92520 [22/24] arm: [MVE intrinsics] add ternary_n shape | | | 92531 [23/24] arm: [MVE intrinsics] factorize vmlaq_n vmlasq_n vqdmlahq_n vqdmlashq_n vqrdmlahq_n vqrdmlashq_n | | | 92548 [24/24] arm: [MVE intrinsics] rework vmlaq vmlasq vqdmlahq vqdmlashq vqrdmlahq vqrdmlashq | | | 92549 [committed] RISC-V: Update RVV integer compare simplification comments | | | 92550 [Commited] MAINTAINERS: Fix alphabetic sorting. | | | 92555 [v2] RISC-V: Allow vector constants in riscv_const_insns. | +------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series37624-patch92555 ++ git branch -a ++ grep 'series37624-patch92555$' + checkbranch= + checkbranchresult=null + '[' null = series37624-patch92555 ']' + git checkout -b series37624-patch92555 Switched to a new branch 'series37624-patch92555' ++ curl https://patchwork.plctlab.org/api/1.2/series/37624/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1398 100 1398 0 0 42363 0 --:--:-- --:--:-- --:--:-- 42363 + series_response='{"id":37624,"url":"https://patchwork.plctlab.org/api/1.2/series/37624/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37624","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","date":"2023-05-11T12:47:24","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/37624/mbox/","cover_letter":null,"patches":[{"id":92555,"url":"https://patchwork.plctlab.org/api/1.2/patches/92555/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/","msgid":"<3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com>","list_archive_url":null,"date":"2023-05-11T12:47:24","name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":37624,"url":"https://patchwork.plctlab.org/api/1.2/series/37624/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37624","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","date":"2023-05-11T12:47:24","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/37624/mbox/","cover_letter":null,"patches":[{"id":92555,"url":"https://patchwork.plctlab.org/api/1.2/patches/92555/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/","msgid":"<3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com>","list_archive_url":null,"date":"2023-05-11T12:47:24","name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/"}]}' + patchid_patchurl='"92555,https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/"' + echo '"92555,https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"92555' ++ sed 's/"//g' + series_patch_id=92555 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++ git rev-parse HEAD + commitid_before=6445f1224509861f2d471a66134b98f26290586e + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied." declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 14997 100 14997 0 0 357k 0 --:--:-- --:--:-- --:--:-- 357k +++ bout='\''\'\'''\''Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 14997 100 14997 0 0 357k 0 --:--:-- --:--:-- --:--:-- 357k +++ bout='\''Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins13374358879110727770.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied.' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 14997 100 14997 0 0 357k 0 --:--:-- --:--:-- --:--:-- 357k +++ bout='\''Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0' /tmp/jenkins13374358879110727770.sh: line 148: ++: command not found ++ ++ declare -p berr /tmp/jenkins13374358879110727770.sh: line 149: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 14997 100 14997 0 0 357k 0 --:--:-- --:--:-- --:--:-- 357k +++ bout='\''Applying: RISC-V: Allow vector constants in riscv_const_insns. Using index info to reconstruct a base tree... M gcc/config/riscv/riscv.cc Falling back to patching base and 3-way merge... No changes -- Patch already applied.'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=6445f1224509861f2d471a66134b98f26290586e + '[' 0 = 0 ']' + '[' 6445f1224509861f2d471a66134b98f26290586e = 6445f1224509861f2d471a66134b98f26290586e ']' + submit_check warning 'Repeat Merge' https://patchwork.plctlab.org/jenkins/job/gcc-patch/6948/consoleText 'Git am fail log' + check_state=warning + patch_state='Repeat Merge' + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/6948/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/6948/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/92555/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 965 100 425 100 540 10897 13846 --:--:-- --:--:-- --:--:-- 24743 {"id":8097,"url":"https://patchwork.plctlab.org/api/patches/92555/checks/8097/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-05-11T14:28:36.353255","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/6948/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Repeat Merge' https://patchwork.plctlab.org/api/1.2/patches/92555/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":92555,"url":"https://patchwork.plctlab.org/api/1.2/patches/92555/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com>","list_archive_url":null,"date":"2023-05-11T12:47:24","name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","commit_ref":null,"pull_url":null,"state":"repeat-merge","archived":false,"hash":"a85580de9aec95515c54859c77723869ed87c238","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/3bd0d367-8ea4-3446-abe6-a7c7a5065248@gmail.com/mbox/","series":[{"id":37624,"url":"https://patchwork.plctlab.org/api/1.2/series/37624/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37624","date":"2023-05-11T12:47:24","name":"[v2] RISC-V: Allow vector constants in riscv_const_insns.","version":2,"mbox":"https://patchwork.plctlab.org/series/37624/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/92555/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/92555/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp4342136vqo;\n Thu, 11 May 2023 05:48:14 -0700 (PDT)","from sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n c13-20020a170906340d00b0096a74be3dcesi643675ejb.548.2023.05.11.05.48.13\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 11 May 2023 05:48:13 -0700 (PDT)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id 8060C3857030\n\tfor ; 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Linux x86_64; rv:102.0) Gecko/20100101\n Thunderbird/102.10.0","Subject":"[PATCH v2] RISC-V: Allow vector constants in riscv_const_insns.","Content-Language":"en-US","To":"=?utf-8?b?6ZKf5bGF5ZOy?= ,\n Jeff Law , gcc-patches ,\n \"kito.cheng\" , \"kito.cheng\" ,\n palmer , Michael Collison ","References":"<46ca12b2-8ac6-030e-92dc-6b71ab2d4ee8@gmail.com>\n <4B555E0D49C3178B+2023050413074589268520@rivai.ai>\n \n <6B74F0215DD1EAD6+2023050708091558978410@rivai.ai>","In-Reply-To":"<6B74F0215DD1EAD6+2023050708091558978410@rivai.ai>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0,\n KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Robin Dapp via Gcc-patches ","Reply-To":"Robin Dapp ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1765602014337430473?=","X-GMAIL-MSGID":"=?utf-8?q?1765602014337430473?="},"content":"> OK, you can go ahead commit patch. I am gonna send another patch to\n> fix this.\nI agree that we should handle more constants but I'd still rather go\nahead now and fix things later. The patch is more about the test\nrather than the actual change anyway.\n\nJeff already ack'ed v1, maybe waiting for Kito's OK to push still.\n\n(Minor) changes from v1:\n - Rebase vs Juzhe's patch\n - Change test format to match binops.\n\n\nThis patch adds various vector constants to riscv_const_insns in order\nfor them to be properly recognized as immediate operands. This then\nallows to emit vmv.v.i instructions via autovectorization.\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv.cc (riscv_const_insns): Add permissible\n\tvector constants.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c: New test.\n\t* gcc.target/riscv/rvv/autovec/vmv-imm-template.h: New test.\n\t* gcc.target/riscv/rvv/autovec/vmv-imm-run.c: New test.\n---\n gcc/config/riscv/riscv.cc | 7 +++\n .../riscv/rvv/autovec/vmv-imm-run.c | 57 +++++++++++++++++++\n .../riscv/rvv/autovec/vmv-imm-rv32.c | 6 ++\n .../riscv/rvv/autovec/vmv-imm-rv64.c | 6 ++\n .../riscv/rvv/autovec/vmv-imm-template.h | 54 ++++++++++++++++++\n 5 files changed, 130 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h","diff":"diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 8f032250b0f..de578b5b899 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -1291,6 +1291,13 @@ riscv_const_insns (rtx x)\n \t\treturn 1;\n \t }\n \t }\n+\t/* Constants from -16 to 15 can be loaded with vmv.v.i.\n+\t The Wc0, Wc1 constraints are already covered by the\n+\t vi constraint so we do not need to check them here\n+\t separately. */\n+\telse if (TARGET_VECTOR && satisfies_constraint_vi (x))\n+\t return 1;\n+\n \t/* TODO: We may support more const vector in the future. */\n \treturn x == CONST0_RTX (GET_MODE (x)) ? 1 : 0;\n }\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c\nnew file mode 100644\nindex 00000000000..309a296b686\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-run.c\n@@ -0,0 +1,57 @@\n+/* { dg-do run { target { riscv_vector } } } */\n+/* { dg-additional-options \"-std=c99 -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin\" } */\n+\n+#include \"vmv-imm-template.h\"\n+\n+#include \n+#include \n+\n+#define SZ 512\n+\n+#define TEST_POS(TYPE,VAL)\t\t\\\n+ TYPE a##TYPE##VAL[SZ];\t \t\\\n+ vmv_##VAL (a##TYPE##VAL, SZ);\t \t\\\n+ for (int i = 0; i < SZ; i++)\t \t\\\n+ assert (a##TYPE##VAL[i] == VAL);\n+\n+#define TEST_NEG(TYPE,VAL)\t\t\\\n+ TYPE am##TYPE##VAL[SZ];\t \t\\\n+ vmv_m##VAL (am##TYPE##VAL, SZ); \t\\\n+ for (int i = 0; i < SZ; i++)\t \t\\\n+ assert (am##TYPE##VAL[i] == -VAL);\n+\n+int main ()\n+{\n+ TEST_NEG(int8_t, 16)\n+ TEST_NEG(int8_t, 15)\n+ TEST_NEG(int8_t, 14)\n+ TEST_NEG(int8_t, 13)\n+ TEST_NEG(int16_t, 12)\n+ TEST_NEG(int16_t, 11)\n+ TEST_NEG(int16_t, 10)\n+ TEST_NEG(int16_t, 9)\n+ TEST_NEG(int32_t, 8)\n+ TEST_NEG(int32_t, 7)\n+ TEST_NEG(int32_t, 6)\n+ TEST_NEG(int32_t, 5)\n+ TEST_NEG(int64_t, 4)\n+ TEST_NEG(int64_t, 3)\n+ TEST_NEG(int64_t, 2)\n+ TEST_NEG(int64_t, 1)\n+ TEST_POS(uint8_t, 0)\n+ TEST_POS(uint8_t, 1)\n+ TEST_POS(uint8_t, 2)\n+ TEST_POS(uint8_t, 3)\n+ TEST_POS(uint16_t, 4)\n+ TEST_POS(uint16_t, 5)\n+ TEST_POS(uint16_t, 6)\n+ TEST_POS(uint16_t, 7)\n+ TEST_POS(uint32_t, 8)\n+ TEST_POS(uint32_t, 9)\n+ TEST_POS(uint32_t, 10)\n+ TEST_POS(uint32_t, 11)\n+ TEST_POS(uint64_t, 12)\n+ TEST_POS(uint64_t, 13)\n+ TEST_POS(uint64_t, 14)\n+ TEST_POS(uint64_t, 15)\n+}\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c\nnew file mode 100644\nindex 00000000000..c419256cd45\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv32.c\n@@ -0,0 +1,6 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-std=c99 -march=rv32gcv -mabi=ilp32d -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin\" } */\n+\n+#include \"vmv-imm-template.h\"\n+\n+/* { dg-final { scan-assembler-times \"vmv.v.i\" 32 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c\nnew file mode 100644\nindex 00000000000..520321e1c73\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-rv64.c\n@@ -0,0 +1,6 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-std=c99 -march=rv64gcv -fno-vect-cost-model --param=riscv-autovec-preference=scalable -fno-builtin\" } */\n+\n+#include \"vmv-imm-template.h\"\n+\n+/* { dg-final { scan-assembler-times \"vmv.v.i\" 32 } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h\nnew file mode 100644\nindex 00000000000..93ba5204c2e\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vmv-imm-template.h\n@@ -0,0 +1,54 @@\n+#include \n+#include \n+\n+#define VMV_POS(TYPE,VAL)\t\t\t\t\\\n+ __attribute__ ((noipa)) \\\n+ void vmv_##VAL (TYPE dst[], int n)\t\t\t\\\n+ { \\\n+ for (int i = 0; i < n; i++) \\\n+ dst[i] = VAL;\t\t\t\t\t\\\n+ }\n+\n+#define VMV_NEG(TYPE,VAL)\t\t\t\t\\\n+ __attribute__ ((noipa)) \\\n+ void vmv_m##VAL (TYPE dst[], int n)\t\t\t\\\n+ { \\\n+ for (int i = 0; i < n; i++) \\\n+ dst[i] = -VAL;\t\t\t\t\t\\\n+ }\n+\n+#define TEST_ALL()\t\\\n+VMV_NEG(int8_t,16)\t\\\n+VMV_NEG(int8_t,15) \t\\\n+VMV_NEG(int8_t,14) \t\\\n+VMV_NEG(int8_t,13) \t\\\n+VMV_NEG(int16_t,12) \\\n+VMV_NEG(int16_t,11) \\\n+VMV_NEG(int16_t,10) \\\n+VMV_NEG(int16_t,9)\t\\\n+VMV_ 100 17181 100 17029 100 152 426k 3897 --:--:-- --:--:-- --:--:-- 430k NEG(int32_t,8)\t\\\n+VMV_NEG(int32_t,7)\t\\\n+VMV_NEG(int32_t,6)\t\\\n+VMV_NEG(int32_t,5)\t\\\n+VMV_NEG(int64_t,4)\t\\\n+VMV_NEG(int64_t,3)\t\\\n+VMV_NEG(int64_t,2)\t\\\n+VMV_NEG(int64_t,1)\t\\\n+VMV_POS(uint8_t,0)\t\\\n+VMV_POS(uint8_t,1)\t\\\n+VMV_POS(uint8_t,2)\t\\\n+VMV_POS(uint8_t,3)\t\\\n+VMV_POS(uint16_t,4)\t\\\n+VMV_POS(uint16_t,5)\t\\\n+VMV_POS(uint16_t,6)\t\\\n+VMV_POS(uint16_t,7)\t\\\n+VMV_POS(uint32_t,8)\t\\\n+VMV_POS(uint32_t,9)\t\\\n+VMV_POS(uint32_t,10)\t\\\n+VMV_POS(uint32_t,11)\t\\\n+VMV_POS(uint64_t,12)\t\\\n+VMV_POS(uint64_t,13)\t\\\n+VMV_POS(uint64_t,14)\t\\\n+VMV_POS(uint64_t,15)\n+\n+TEST_ALL()\n","prefixes":["v2"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE