Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 0918360d709a32294913aef4392cec6c1dec1857 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 0918360d709a32294913aef4392cec6c1dec1857 # timeout=10 Commit message: "VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV" > git rev-list --no-walk 0918360d709a32294913aef4392cec6c1dec1857 # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Property | Value | |------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------| | ID | 21 | | Name | gcc-patch_2023-05 | | URL | https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-05/ | | Owner | patchwork-bot | | Project | gcc-patch | | Public | True | | Patches | 88946 [(pushed)] libsanitizer: link hwasan against lsan library | | | 88948 [(pushed)] hwasan: adjust wording in expected output in tests | | | 88955 MATCH: Port CLRSB part of builtin_zero_pattern | | | 88956 PHIOPT: small refactoring of match_simplify_replacement. | | | 88957 PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 88960 [Committed] Update xstormy16's neghi2 pattern to not clobber the carry flag. | | | 88972 [COMMITTED] vrange_storage overhaul | | | 88970 [COMMITTED] Remove irange::{min,max,kind}. | | | 88969 [COMMITTED] Remove irange::tree_{lower,upper}_bound. | | | 88971 [COMMITTED] Various cleanups in vr-values.cc towards ranger API. | | | 88977 [COMMITTED] Convert get_legacy_range in bounds_of_var_in_loop to irange API. | | | 88974 [COMMITTED] Merge irange::union/intersect into irange_union/intersect. | | | 88980 [COMMITTED] Conversion to irange wide_int API. | | | 88975 [COMMITTED] Replace vrp_val* with wide_ints. | | | 88978 [COMMITTED] Rewrite bounds_of_var_in_loop() to use ranges. | | | 88976 [COMMITTED] Convert internal representation of irange to wide_ints. | | | 88973 [COMMITTED] Cleanup irange::set. | | | 88979 [COMMITTED] Inline irange::set_nonzero. | | | 88981 [COMMITTED] Remove unused friends in int_range<>. | | | 88984 [committed] libgcc pru: Define TARGET_HAS_NO_HW_DIVIDE | | | 89047 [committed] Enable LRA on several ports | | | 89048 [committed] Convert xstormy16 to LRA | | | 89080 RISC-V: Name newly added flags in changelog | | | 89081 Fortran: overloading of intrinsic binary operators [PR109641] | | | 89082 PHIOPT: Update comment about what the pass now does | | | 89168 [1/2] c++: potentiality of templated memfn call [PR109480] | | | 89167 [2/2] c++: non-dep init folding and access checking [PR109480] | | | 89176 [pushed] c++: array DMI and member fn [PR109666] | | | 89185 [pushed] ubsan: ubsan_maybe_instrument_array_ref tweak | | | 89207 c++: Move -Wdangling-reference to -Wextra [PR109642] | | | 89266 i386: Fix up handling of debug insns in STV [PR109676] | | | 89284 libstdc++: Shut up -Wattribute-alias warning [PR109694] | | | 89286 libstdc++: Regenerate baseline_symbols.txt files for Linux | | | 89300 [i386] Fix testcases for emulated scatter | | | 89301 tree-optimization/109672 - properly check emulated plus during vect | | | 89330 RISC-V: fix build issue with gcc 4.9.x | | | 89343 [(pushed)] docs: port documentation of VRP params | | | 89344 [pushed] c++: Add testcase for already fixed PR [PR109506] | | | 89396 release the sorted FDE array when deregistering a frame [PR109685] | | | 89397 do not tailcall __sanitizer_cov_trace_pc [PR90746] | | | 89403 c++: Fix up VEC_INIT_EXPR gimplification after r12-7069 | | | 89407 rs6000: Add builtins for IEEE 128-bit floating point values | | | 89443 [1/2] c++: std::variant slow to compile [PR109678] | | | 89444 [2/2] c++: look for empty base at specific offset [PR109678] | | | 89445 [pushed] c++: less invalidate_class_lookup_cache | | | 89446 [Committed,11/11] RISC-V: Table A.6 conformance tests | | | 89460 c++: satisfaction of non-dep member alias template-id | | | 89463 [COMMITTED] tree-optimization: [PR109702] MATCH: Fix a ? func(a) : N patterns | | | 89488 [pushed] c++: simplify member template substitution | | | 89514 c++: wrong std::is_convertible with cv-qual fn [PR109680] | | | 89515 Add stats to simple_dce_from_worklist | | | 89539 [v2,1/1] libstdc++: Set _M_string_length before calling _M_dispose() [PR109703] | | | 89541 [1/2] Factor out copy_phi_args from gimple_duplicate_sese_tail and remove_forwarder_block. | | | 89542 [2/2] PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 89557 [pushed] c++: fix TTP level reduction cache | | | 89662 [(pushed)] clang warning: warning: private field 'm_gc' is not used [-Wunused-private-field] | | | 89680 [GCC,11] tree-optimization/109473 - fix type mismatch in reduction vectorization | | | 89701 riscv: Don't add -latomic with -pthread | | | 89712 Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS' (was: Update testsuite to run with slim LTO) | | | 89720 Remove type from vrange_storage::equal_p. | | | 89738 [10/10] arm testsuite: Shifts and get_FPSCR ACLE optimisation fixes | | | 89740 More last_stmt removal | | | 89741 Rename last_stmt to last_nondebug_stmt | | | 89753 c++: ahead of time variable template-id coercion [PR89442] | | | 89768 [(pushed)] riscv: fix error: control reaches end of non-void function | | | 89769 [v2,03/22] arm: [MVE intrinsics] Rework vreinterpretq | | | 89775 rs6000: vec_cmpne confusing implementation | | | 89783 [1/2] aarch64: Rename abi_break parameters [PR109661] | | | 89784 [2/2] aarch64: Fix ABI handling of aligned enums [PR109661] | | | 89798 [COMMITTED] Allow varying ranges of unknown types in irange::verify_range [PR109711] | | | 89802 [gcc13,backport] RISCV: Inline subword atomic ops | | | 89823 libstdc++: Fix up abi.exp FAILs on powerpc64-linux | | | 89830 libstdc++: Fix up abi.exp FAILs on powerpc64le-linux | | | 89833 [pushed] c++: over-eager friend matching [PR109649] | | | 89859 [PUSHED,gcc-11] extend.texi: replace @itemx not preceded by @item. | | | 89869 PHIOPT: Improve replace_phi_edge_with_variable's dce_ssa_names slightly | | | 89870 [1/2] Move copy_phi_arg_into_existing_phi to common location and use it | | | 89871 [PATCHv2,2/2] PHIOPT: Improve replace_phi_edge_with_variable for diamond shapped bb | | | 89881 [committed] CRIS-LRA: Fix uses of reload_in_progress | | | 89883 [committed] CRIS-LRA: Define TARGET_SPILL_CLASS | | | 89884 [committed] CRIS: peephole2 an "and" with a contiguous "one-sided" sequences of 1s | | | 89902 [v2] Canonicalize vec_merge when mask is constant. | | | 89921 [V3] RISC-V: Enable basic RVV auto-vectorization support. | | | 89922 [powerpc] Add a peephole2 to eliminate redundant move from VSX_REGS to GENERAL_REGS when it's from memory. | | | 89936 RISC-V: Handle multi-lib path correclty for linux | | | 89939 tree-optimization/109724 - new testcase | | | 89951 libgomp C++ testsuite: Use 'lang_include_flags' instead of 'libstdcxx_includes' (was: [PATCH] libgomp: Add openacc_{cuda,cublas,cudart} effective targets and use them in openacc testsuite) | | | 89954 [v2] RISC-V: Handle multi-lib path correclty for linux | | | 89995 RISC-V: Legitimise the const0_rtx for RVV indexed load/store | | | 90000 [PATCHv2,rs6000] Splat vector small V2DI constants with ISA 2.07 instructions [PR104124] | | | 90007 [v2] RISC-V: Legitimise the const0_rtx for RVV indexed load/store | | | 90040 tree-optimization/109721 - emulated vectors | | | 90050 i386: Improve index_register_operand predicate | | | 90056 [committed] libstdc++: Document new library version in manual | | | 90059 [libstdc++] use strtold for from_chars even without locale | | | 90060 [vxworks,testsuite,aarch64] use builtin in pred-not-gen-4.c | | | 90082 [V4] VECT: Add decrement IV iteration loop control by variable amount support | | | 90090 [RFC] tree-optimization/104475 - bogus -Wstringop-overflow | | | 90139 c++: some assorted code improvements | | | 90140 c++: fix pretty printing of 'alignof' vs '__alignof__' [PR85979] | | | 90153 RISC-V: Add bext pattern for ZBS | | | 90154 RISC-V: Fix CTZ unnecessary sign extension [PR #106888] | | | 90174 i386: Tighten ashift to lea splitter operand predicates [PR109733] | | | 90218 libffi: fix handling of homogeneous float128 structs [PR109447] | | | 90255 PHIOPT: Fix diamond case of match_simplify_replacement | | | 90263 MATCH: Add ABSU == 0 to a == 0 simplification | | | 90269 [pushed] Revert "c++: restore instantiate_decl assert" | | | 90292 RISC-V: Fix PR109615 | | | 90307 [V2] RISC-V: Fix PR109615 | | | 90323 [committed] builtins: Fix comment typo mpft_t -> mpfr_t | | | 90327 gimple-range-op: Improve handling of sqrt ranges | | | 90349 [01/23] arm: [MVE intrinsics] add binary_round_lshift shape | | | 90348 [02/23] arm: [MVE intrinsics] factorize vqrshlq vrshlq | | | 90360 [03/23] arm: [MVE intrinsics] rework vrshlq vqrshlq | | | 90351 [04/23] arm: [MVE intrinsics] factorize vqshlq vshlq | | | 90356 [05/23] arm: [MVE intrinsics] rework vqrdmulhq | | | 90347 [06/23] arm: [MVE intrinsics] factorize vabdq | | | 90355 [07/23] arm: [MVE intrinsics] rework vabdq | | | 90354 [08/23] arm: [MVE intrinsics] add binary_lshift shape | | | 90353 [09/23] arm: [MVE intrinsics] add support for MODE_r | | | 90350 [10/23] arm: [MVE intrinsics] add binary_lshift_r shape | | | 90352 [11/23] arm: [MVE intrinsics] add unspec_mve_function_exact_insn_vshl | | | 90368 [12/23] arm: [MVE intrinsics] rework vqshlq vshlq | | | 90361 [13/23] arm: [MVE intrinsics] factorize vmaxq vminq | | | 90365 [14/23] arm: [MVE intrinsics] rework vmaxq vminq | | | 90364 [15/23] arm: [MVE intrinsics] add binary_rshift_narrow shape | | | 90366 [16/23] arm: [MVE intrinsics] factorize vshrntq vshrnbq vrshrnbq vrshrntq vqshrnbq vqshrntq vqrshrnbq vqrshrntq | | | 90367 [17/23] arm: [MVE intrinsics] rework vshrnbq vshrntq vrshrnbq vrshrntq vqshrnbq vqshrntq vqrshrnbq vqrshrntq | | | 90358 [18/23] arm: [MVE intrinsics] add binary_rshift_narrow_unsigned shape | | | 90362 [19/23] arm: [MVE intrinsics] factorize vqrshrunb vqrshrunt vqshrunb vqshrunt | | | 90363 [20/23] arm: [MVE intrinsics] rework vqrshrunbq vqrshruntq vqshrunbq vqshruntq | | | 90357 [21/23] arm: [MVE intrinsics] add binary_rshift shape | | | 90359 [22/23] arm: [MVE intrinsics] factorize vsrhrq vrshrq | | | 90369 [23/23] arm: [MVE intrinsics] rework vshrq vrshrq | | | 90370 Support parallel testing in libgomp, part I [PR66005] | | | 90372 Support parallel testing in libgomp, part II [PR66005] | | | 90373 tree: Fix up save_expr [PR52339] | | | 90393 [1/8] MIPS: Add basic support for mips16e2 | | | 90391 [2/8] MIPS: Add MOVx instructions support for mips16e2 | | | 90392 [3/8] MIPS: Add instruction about global pointer register for mips16e2 | | | 90394 [4/8] MIPS: Add bitwise instructions for mips16e2 | | | 90388 [5/8] MIPS: Add LUI instruction for mips16e2 | | | 90389 [6/8] MIPS: Add load/store word left/right instructions for mips16e2 | | | 90395 [7/8] MIPS: Use ISA_HAS_9BIT_DISPLACEMENT for mips16e2 | | | 90396 [8/8] MIPS: Add CACHE instruction for mips16e2 | | | 90409 GCN: Silence unused-variable warning | | | 90426 i386: Introduce mulv2si3 instruction | | | 90428 tree-optimization/109735 - conversion for vectorized pointer-diff | | | 90438 i386: Rename index_register_operand predicate to register_no_SP_operand | | | 90446 RISC-V: Fix PR109748 | | | 90453 [V4] RISC-V: Enable basic RVV auto-vectorization support. | | | 90455 [V2] RISC-V: Fix incorrect demand info merge in local vsetvli optimization [PR109748] | | | 90469 [V5] RISC-V: Enable basic RVV auto-vectorization support. | | | 90474 Move substitute_and_fold over to use simple_dce_from_worklist | | | 90482 [v6,1/9] RISC-V: autovec: Add new predicates and function prototypes | | | 90483 [v6,2/9] RISC-V: autovec: Export policy functions to global scope | | | 90490 [v6,3/9] RISC-V:autovec: Add auto-vectorization support functions | | | 90489 [v6,4/9] RISC-V:autovec: Add target vectorization hooks | | | 90484 [v6,5/9] RISC-V:autovec: Add autovectorization patterns for binary integer & len_load/store | | | 90495 [v6,6/9] RISC-V:autovec: Add autovectorization tests for add & sub | | | 90493 [v6,7/9] RISC-V: autovec: Verify that GET_MODE_NUNITS is a multiple of 2. | | | 90491 [v6,8/9] RISC-V:autovec: Add autovectorization tests for binary integer | | | 90494 [v6,9/9] RISC-V:autovec: This patch supports 8 bit auto-vectorization in riscv. | | | 90498 [01/10] arm: [MVE intrinsics] add unary shape | | | 90499 [02/10] arm: [MVE intrinsics] factorize several unary operations | | | 90502 [03/10] arm: [MVE intrinsics] rework vabsq vnegq vclsq vclzq, vqabsq, vqnegq | | | 90506 [04/10] arm: [MVE intrinsics] rework vrndq vrndaq vrndmq vrndnq vrndpq vrndxq | | | 90500 [05/10] arm: [MVE intrinsics] add binary_move_narrow and binary_move_narrow_unsigned shapes | | | 90505 [06/10] arm: [MVE intrinsics] factorize vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq | | | 90507 [07/10] arm: [MVE intrinsics] rework vmovnbq vmovntq vqmovnbq vqmovntq vqmovunbq vqmovuntq | | | 90504 [08/10] arm: [MVE intrinsics] add binary_widen_n shape | | | 90501 [09/10] arm: [MVE intrinsics] factorize vshllbq vshlltq | | | 90503 [10/10] arm: [MVE intrinsics] rework vshllbq vshlltq | | | 90508 ira: Don't create copies for earlyclobbered pairs | | | 90511 Makefile.in: clean up match.pd-related dependencies | | | 90514 [RFC] RISC-V: Add proposed Ztso atomic mappings | | | 90523 c++: list CTAD and resolve_nondeduced_context [PR106214] | | | 90524 c++: goto entering scope of obj w/ non-trivial dtor [PR103091] | | | 90552 c++: parenthesized -> resolving to static member [PR98283] | | | 90581 gimple-range-op: Improve handling of sin/cos ranges | | | 90624 [committed] CRIS: peephole2 a lsrq into a lslq+lsrq pair | | | 90631 [committed] CRIS: peephole2 a move of constant followed by and of same register | | | 90633 [committed] CRIS: peephole2 an add into two addq or subq | | | 90657 ISC-V: Enable basic RVV auto-vectorization support. | | | 90658 [V6] RISC-V: Enable basic RVV auto-vectorization support. | | | 90670 [fortran] PR109662 Namelist input with comma after name accepted | | | 90671 [V7] RISC-V: Enable basic RVV auto-vectorization support. | | | 90710 [1/2,RISC-V] disable shrink-wrap-separate if zcmp enabled. | | | 90711 [2/2,RISC-V] support cm.push cm.pop cm.popret in zcmp | | | 90729 RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 90734 hurd: Add multilib paths for gnu-x86_64 | | | 90736 hurd: Ad default-pie and static-pie support | | | 90755 Don't call emit_clobber in lower-subreg.cc's resolve_simple_move. | | | 90758 [x86_64] Introduce insvti_highpart define_insn_and_split. | | | 90778 nvptx: Add suppport for __builtin_nvptx_brev instrinsic. | | | 90781 Add RTX codes for BITREVERSE and COPYSIGN. | | | 90783 Pushed: [PATCH v2] LoongArch: Enable shrink wrapping | | | 90785 [libgcc] Add bit reversal functions __bitrev[qhsd]i2. | | | 90799 [committed] Partial revert of recent changes | | | 90817 [1/3] PHIOPT: Add diamond bb form to factor_out_conditional_conversion | | | 90816 [2/3] PHIOPT: Loop over calling factor_out_conditional_conversion | | | 90815 [3/3] PHIOPT: factor out unary operations instead of just conversions | | | 90819 [1/3] PHIOPT: Add diamond bb form to factor_out_conditional_conversion | | | 90824 [pushed] wwwdocs: onlinedocs: Fix markup | | | 90851 Fix aarch64/109762: push_options/push_options does not work sometimes | | | 90876 [GCC,13] Fix aarch64/109762: push_options/push_options does not work sometimes | | | 90887 MATCH: Move `a <= CST1 ? MAX : a` optimization to match | | | 90914 [V2,vect] Enhance NARROW FLOAT_EXPR vectorization by truncating integer to lower precision. | | | 90929 RISC-V: Fix ugly && incorrect codes of RVV auto-vectorization | | | 90936 Add a != MIN/MAX_VALUE_CST ? CST-+1 : a to minmax_from_comparison | | | 91031 RISC-V: Update RVV integer compare simplification comments | | | 91038 [v4] libgfortran: Replace mutex with rwlock | | | 91153 xtensa: Make full transition to LRA | | | 91165 libgm2: Remove 'autogen.sh' (was: libgm2: Adjust 'autogen.sh' to 'ACLOCAL_AMFLAGS', and simplify) | | | 91167 [v2] RISC-V: Add bext pattern for ZBS | | | 91168 [v2] RISC-V: Fix CTZ unnecessary sign extension [PR #106888] | | | 91176 [committed] Fix minor length computation on stormy16 | | | 91185 [committed] RISC-V: Factor out vector manager code in vsetvli insertion pass. [NFC] | | | 91186 [committed] RISC-V: Improve portability of testcases | | | 91187 [V2] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 91189 [v2] xtensa: Make full transition to LRA | | | 91219 [COMMITTED] Fix pr81192.c for int16 targets | | | 91222 [1/3] genmatch: clean up emit_func | | | 91221 [2/3] genmatch: clean up showUsage | | | 91220 [3/3] genmatch: fixup get_out_file | | | 91311 [PUSHED] Fix cfg maintenance after inlining in AutoFDO | | | 91314 [V3] RISC-V: Optimize vsetvli of LCM INSERTED edge for user vsetvli [PR 109743] | | | 91346 RISC-V: Fix dead loop for user vsetvli intrinsic avl checking [PR109773] | | | 91352 [v5] libgfortran: Replace mutex with rwlock | | | 91387 [committed,gcc,12] Fix ICE related to implicit access attributes for VLA arguments [PR105660] | | | 91388 [1/6] aarch64: Fix move-after-intrinsic function-body tests | | | 91390 [2/6] aarch64: Allow moves after tied-register intrinsics | | | 91389 [3/6] aarch64: Relax ordering requirements in SVE dup tests | | | 91391 [4/6] aarch64: Relax predicate register matches | | | 91392 [5/6] aarch64: Relax FP/vector register matches | | | 91393 [6/6] aarch64: Avoid hard-coding specific register allocations | | | 91396 Detect bswap + rotate for byte permutation in pass_bswap. | | | 91448 c++: Reject attributes without arguments used as pack expansion [PR109756] | | | 91449 c++: Reject pack expansion of assume attribute [PR109756] | | | 91455 tree-ssa-ccp, wide-int: Fix up handling of [LR]ROTATE_EXPR in bitwise ccp [PR109778] | | | 91460 i386: Honour -mdirect-extern-access when calling __fentry__ | | | 91461 Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'torture-init' the 'LTO_TORTURE_OPTIONS') | | | 91469 RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | | | 91495 [committed] testsuite: Add further testcase for already fixed PR [PR109778] | | | 91498 [committed] mux-utils.h: Fix a comment typo | | | 91552 [V2] RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | | | 91555 [RFC] c-family: Implement __has_feature and __has_extension [PR60512] | | | 91558 [01/16] arm: [MVE intrinsics] add binary_maxvminv shape | | | 91572 [02/16] arm: [MVE intrinsics] add binary_maxavminav shape | | | 91557 [03/16] arm: [MVE intrinsics add unspec_mve_function_exact_insn_pred_p | | | 91565 [04/16] arm: [MVE intrinsics] factorize vmaxvq vminvq vmaxavq vminavq | | | 91579 [05/16] arm: [MVE intrinsics] rework vmaxvq vminvq vmaxavq vminavq | | | 91559 [06/16] arm: add smax/smin expanders for v*hf | | | 91576 [07/16] arm: [MVE intrinsics] factorize vmaxnmq vminnmq | | | 91568 [08/16] arm: [MVE intrinsics] rework vmaxnmq vminnmq | | | 91577 [09/16] arm: [MVE intrinsics] factorize vmaxnmavq vmaxnmvq vminnmavq vminnmvq | | | 91564 [10/16] arm: [MVE intrinsics] add support for mve_q_p_f | | | 91571 [11/16] arm: [MVE intrinsics] rework vmaxnmavq vmaxnmvq vminnmavq vminnmvq | | | 91560 [12/16] arm: [MVE intrinsics] factorize vmaxnmaq vminnmaq | | | 91573 [13/16] arm: [MVE intrinsics] rework vmaxnmaq vminnmaq | | | 91574 [14/16] arm: [MVE intrinsics] add binary_maxamina shape | | | 91578 [15/16] arm: [MVE intrinsics] factorize vmaxaq vminaq | | | 91567 [16/16] arm: [MVE intrinsics] rework vmaxaq vminaq | | | 91580 libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91582 libgomp testsuite: Only use 'blddir' if set (was: libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91583 libgomp testsuite: Use 'lang_test_file_found' instead of 'lang_test_file' (was: libgomp testsuite: Only use 'blddir' if set (was: libgomp C++ testsuite: Don't compute 'blddir' twice (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91589 libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?) | | | 91592 libgomp C++, Fortran testsuites: Resolve 'lang_test_file_found' first (was: libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91595 libgomp testsuite: Get rid of 'lang_test_file_found' (was: libgomp C++, Fortran testsuites: Resolve 'lang_test_file_found' first (was: libgomp testsuite: Localize 'lang_[...]' etc. (was: libgomp testsuite: (not) using a specific driver for C++, Fortran?)) | | | 91598 [committed] Eliminate more comparisons on the H8 port | | | 91636 [fortran] PR97122 - Spurious FINAL ... must be in the specification part of a MODULE | | | 91638 vect: Missed opportunity to use [SU]ABD | | | 91640 [fortran] PR103716 - [10/11/12/13/14 Regression] ICE in gimplify_expr, at gimplify.c:15964 | | | 91642 vect: Missed opportunity to use [SU]ABD | | | 91649 rtl: AArch64: New RTL for ABD | | | 91656 c++: noexcept-spec from nested class confusion [PR109761] | | | 91655 c++: error-recovery ICE with unstable satisfaction [PR109752] | | | 91705 [1/2] aarch64: Fix cut-&-pasto in aarch64-sve2-acle-asm.exp | | | 91706 [2/2] aarch64: Improve register allocation for lane instructions | | | 91711 [v2,06/16] arm: add smax/smin expanders for v*hf | | | 91724 c++, v2: Reject attributes without arguments used as pack expansion [PR109756] | | | 91730 configure: Implement --enable-host-pie | | | 91731 [committed] libstdc++: Fix pretty printers and add tests | | | 91784 [committed] CRIS: Fix ccmode typo in cris_postdbr_cmpelim | | | 91787 Fixes and workarounds for warnings during autoprofiledbootstrap build | | | 91795 RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0. | | | 91834 RISC-V: Support const series vector for RVV auto-vectorization | | | 91835 [V2] RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instructions satisfying REG_P(operand[1]) in -O0. | | | 91857 _Hashtable implementation cleanup | | | 91865 [Committed] New testcase | | | 91913 Var-Tracking: Leverage pointer_mux for decl_or_value | | | 91936 Testsuite: Add 'torture-init-done', and use it to conditionalize implicit 'torture-init' (was: Testsuite: Add missing 'torture-init'/'torture-finish' around 'LTO_TORTURE_OPTIONS' usage (was: Let each 'lto_init' determine the default 'LTO_OPTIONS', and 'to | | | 91977 x86: Add a new option -mdaz-ftz to enable FTZ and DAZ flags in MXCSR. | | | 92006 ipa-prop: Fix ipa_get_callee_param_type for calls with argument type mismatches | | | 92013 fix radix sort on 32bit platforms [PR109670] | | | 92032 [RFC] libstdc++: Do not use pthread_mutex_clocklock with ThreadSanitizer | | | 92051 [committed] Fix a couple constraints on the H8 in preparation for LRA conversion | | | 92065 [v2] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92080 RISC-V: Add basic vec_init support for RVV auto-vectorizaiton | | | 92085 [01/20] arm: [MVE intrinsics] factorize vcmp | | | 92105 [02/20] arm: [MVE intrinsics] add cmp shape | | | 92119 [03/20] arm: [MVE intrinsics] rework vcmp | | | 92096 [04/20] arm: [MVE intrinsics] factorize vrev16q vrev32q vrev64q | | | 92118 [05/20] arm: [MVE intrinsics] rework vrev16q vrev32q vrev64q | | | 92094 [06/20] arm: [MVE intrinsics] factorize vdupq | | | 92101 [07/20] arm: [MVE intrinsics] add unary_n shape | | | 92110 [08/20] arm: [MVE intrinsics] rework vdupq | | | 92091 [09/20] arm: [MVE intrinsics] factorize vaddvq | | | 92102 [10/20] arm: [MVE intrinsics] add unary_int32 shape | | | 92087 [11/20] arm: [MVE intrinsics] rework vaddvq | | | 92116 [12/20] arm: [MVE intrinsics] factorize vaddvaq | | | 92113 [13/20] arm: [MVE intrinsics] add unary_int32_acc shape | | | 92103 [14/20] arm: [MVE intrinsics] rework vaddvaq | | | 92099 [15/20] arm: [MVE intrinsics] add unary_acc shape | | | 92104 [16/20] arm: [MVE intrinsics] factorize vaddlvq | | | 92108 [17/20] arm: [MVE intrinsics] rework vaddlvq | | | 92107 [18/20] arm: [MVE intrinsics] factorize vmovlbq vmovltq | | | 92106 [19/20] arm: [MVE intrinsics] add unary_widen shape | | | 92098 [20/20] arm: [MVE intrinsics] rework vmovlbq vmovltq | | | 92120 Avoid g++.dg/torture/pr106922.C FAIL with the pre-C++11 ABI | | | 92163 [take,#3] match.pd: Simplify popcount/parity of bswap/rotate. | | | 92170 [pushed,1/2] c++: always check consteval address | | | 92171 [pushed,2/2] c++: be stricter about constinit [CWG2543] | | | 92175 [v3] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92176 riscv: Add vectorized binops and insn_expander helpers. | | | 92179 riscv: Clarify vlmax and length handling. | | | 92177 riscv: Split off shift patterns for autovectorization. | | | 92178 riscv: Add autovectorization tests for binary integer | | | 92181 c++: converted lambda as template argument [PR83258, ...] | | | 92183 [V5,2/2] PR target/105325: Fix memory constraints for power10 fusion. | | | 92190 RISC-V: Remove masking third operand of rotate instructions | | | 92200 [committed] MAINTAINERS: Add myself to write after approval | | | 92212 [v2] Fortran: Narrow return types [PR78798] | | | 92213 [1/2] Fortran: dump-parse-tree attribs: fix unbalanced braces [PR109624] | | | 92214 [2/2] Fortran: dump-parse-tree: Mark debug functions with DEBUG_FUNCTION | | | 92252 Add another new testcase | | | 92253 rs6000: Fix __builtin_vec_xst_trunc definition | | | 92278 [x86_64] Use [(const_int 0)] idiom consistently in i386.md | | | 92291 i386: Add missing vector extend patterns [PR92658] | | | 92294 [pushed] c++: adjust conversion diagnostics | | | 92305 [v2] c++: wrong std::is_convertible with cv-qual fn [PR109680] | | | 92307 match.pd: Simplify popcount(X&Y)+popcount(X|Y) as popcount(X)+popcount(Y) | | | 92346 [v4] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92348 MAINTAINERS: Add myself to write after approval | | | 92349 [commited] MAINTAINERS: Add myself to write after approval | | | 92351 [committed,v2] RISC-V: Support const series vector for RVV auto-vectorization | | | 92355 [V5] VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV. | | | 92366 [v5] Var-Tracking: Typedef pointer_mux as decl_or_value | | | 92433 mklog.py: Add --commit option. | | | 92445 [V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization | | | 92452 [V6] VECT: Add tree_code into "creat_iv" and allow it can handle MINUS_EXPR IV. | | | 92472 [1/2] PR gcc/98350:Add a param to control the length of the chain with FMA in reassoc pass | | | 92471 [2/2] Add a tune option to control the length of the chain with FMA | | | 92473 [v2] RISC-V: Add vectorized binops and insn_expander helpers. | | | 92474 [v2] RISC-V: Add autovectorization tests for binary integer, operations. | | | 92475 [v2] RISC-V: Clarify vlmax and length handling. | +------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + git config pull.rebase false + git fetch origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Already up to date. + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Already up to date. + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series37593-patch92475 ++ git branch -a ++ grep 'series37593-patch92475$' + checkbranch= + checkbranchresult=null + '[' null = series37593-patch92475 ']' + git checkout -b series37593-patch92475 Switched to a new branch 'series37593-patch92475' ++ curl https://patchwork.plctlab.org/api/1.2/series/37593/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1378 100 1378 0 0 39371 0 --:--:-- --:--:-- --:--:-- 39371 + series_response='{"id":37593,"url":"https://patchwork.plctlab.org/api/1.2/series/37593/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37593","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] RISC-V: Clarify vlmax and length handling.","date":"2023-05-11T10:29:54","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/37593/mbox/","cover_letter":null,"patches":[{"id":92475,"url":"https://patchwork.plctlab.org/api/1.2/patches/92475/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/","msgid":"","list_archive_url":null,"date":"2023-05-11T10:29:54","name":"[v2] RISC-V: Clarify vlmax and length handling.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/"}]}' ++ echo '{"id":37593,"url":"https://patchwork.plctlab.org/api/1.2/series/37593/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37593","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[v2] RISC-V: Clarify vlmax and length handling.","date":"2023-05-11T10:29:54","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/37593/mbox/","cover_letter":null,"patches":[{"id":92475,"url":"https://patchwork.plctlab.org/api/1.2/patches/92475/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/","msgid":"","list_archive_url":null,"date":"2023-05-11T10:29:54","name":"[v2] RISC-V: Clarify vlmax and length handling.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"92475,https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/"' + echo '"92475,https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"92475' ++ sed 's/"//g' + series_patch_id=92475 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++ git rev-parse HEAD + commitid_before=0918360d709a32294913aef4392cec6c1dec1857 + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 21708 100 21708 0 0 255k 0 --:--:-- --:--:-- --:--:-- 255k +++ bout='\''\'\'''\''Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 21708 100 21708 0 0 255k 0 --:--:-- --:--:-- --:--:-- 255k +++ bout='\''Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins9491742671535981335.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 21708 100 21708 0 0 255k 0 --:--:-- --:--:-- --:--:-- 255k +++ bout='\''Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins9491742671535981335.sh: line 154: ++: command not found ++ ++ declare -p berr /tmp/jenkins9491742671535981335.sh: line 155: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 21708 100 21708 0 0 255k 0 --:--:-- --:--:-- --:--:-- 255k +++ bout='\''Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=0918360d709a32294913aef4392cec6c1dec1857 + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 21708 100 21708 0 0 255k 0 --:--:-- --:--:-- --:--:-- 255k +++ bout='Applying: RISC-V: Clarify vlmax and length handling. error: sha1 information is lacking or useless (gcc/config/riscv/riscv.cc). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Clarify vlmax and length handling. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/6908/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/6908/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/6908/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/92475/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 965 100 425 100 540 11486 14594 --:--:-- --:--:-- --:--:-- 26081 {"id":8063,"url":"https://patchwork.plctlab.org/api/patches/92475/checks/8063/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-05-11T11:19:45.917477","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/6908/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/92475/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":92475,"url":"https://patchwork.plctlab.org/api/1.2/patches/92475/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2023-05-11T10:29:54","name":"[v2] RISC-V: Clarify vlmax and length handling.","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"4b63e61b15b6c179e560062653424d256b7b280f","submitter":{"id":4498,"url":"https://patchwork.plctlab.org/api/1.2/people/4498/","name":"Robin Dapp","email":"rdapp.gcc@gmail.com"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/e21778f9-94f2-9452-f2fd-270322ab88e8@gmail.com/mbox/","series":[{"id":37593,"url":"https://patchwork.plctlab.org/api/1.2/series/37593/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=37593","date":"2023-05-11T10:29:54","name":"[v2] RISC-V: Clarify vlmax and length handling.","version":2,"mbox":"https://patchwork.plctlab.org/series/37593/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/92475/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/92475/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:b0ea:0:b0:3b6:4342:cba0 with SMTP id b10csp4260692vqo;\n Thu, 11 May 2023 03:30:43 -0700 (PDT)","from sourceware.org (server2.sourceware.org. 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Linux x86_64; rv:102.0) Gecko/20100101\n Thunderbird/102.10.0","Subject":"[PATCH v2] RISC-V: Clarify vlmax and length handling.","Content-Language":"en-US","To":"Kito Cheng , Palmer Dabbelt ","Cc":"gcc-patches@gcc.gnu.org, juzhe.zhong@rivai.ai, collison@rivosinc.com,\n jeffreyalaw@gmail.com","References":"<55666d64-ec4b-199d-81d5-26c2334606d3@gmail.com>\n \n ","In-Reply-To":"\n ","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-Spam-Status":"No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0,\n RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","From":"Robin Dapp via Gcc-patches ","Reply-To":"Robin Dapp ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","Sender":"\"Gcc-patches\" ","X-getmail-retrieved-from-mailbox":"=?utf-8?q?INBOX?=","X-GMAIL-THRID":"=?utf-8?q?1765593363365387831?=","X-GMAIL-MSGID":"=?utf-8?q?1765593363365387831?="},"content":"Changes from v1:\n - Change subject to RISC-V ;)\n - Minor comment updates and rebasing.\n\nThis patch tries to improve the wrappers that emit either vlmax or\nnon-vlmax operations. Now, emit_len_op can be used to\nemit a regular operation. Depending on whether a length != NULL\nis passed either no VLMAX flags are set or we emit a vsetvli and\nset VLMAX flags. The patch also adds some comments that describes\nsome of the rationale of the current handling of vlmax/nonvlmax\noperations.\n\ngcc/ChangeLog:\n\n\t* config/riscv/autovec.md: Use renamed functions.\n\t* config/riscv/riscv-protos.h (emit_vlmax_op): Rename.\n\t(emit_vlmax_reg_op): To this.\n\t(emit_nonvlmax_op): Rename.\n\t(emit_len_op): To this.\n\t(emit_nonvlmax_binop): Rename.\n\t(emit_len_binop): To this.\n\t* config/riscv/riscv-v.cc (emit_pred_op): Add default parameter.\n\t(emit_pred_binop): Remove vlmax_p.\n\t(emit_vlmax_op): Rename.\n\t(emit_vlmax_reg_op): To this.\n\t(emit_nonvlmax_op): Rename.\n\t(emit_len_op): To this.\n\t(emit_nonvlmax_binop): Rename.\n\t(emit_len_binop): To this.\n\t(sew64_scalar_helper): Use renamed functions.\n\t(expand_tuple_move): Use renamed functions.\n\t* config/riscv/riscv.cc (vector_zero_call_used_regs): Use\n\trenamed functions.\n\t* config/riscv/vector.md: Use renamed functions.\n---\n gcc/config/riscv/autovec.md | 26 ++++-----\n gcc/config/riscv/riscv-protos.h | 8 +--\n gcc/config/riscv/riscv-v.cc | 94 ++++++++++++++++++++-------------\n gcc/config/riscv/riscv.cc | 4 +-\n gcc/config/riscv/vector.md | 12 +++--\n 5 files changed, 83 insertions(+), 61 deletions(-)","diff":"diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md\nindex e249f4be704..58926ed3e67 100644\n--- a/gcc/config/riscv/autovec.md\n+++ b/gcc/config/riscv/autovec.md\n@@ -31,8 +31,8 @@ (define_expand \"len_load_\"\n (match_operand 3 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n {\n- riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0],\n-\t\t\t\t operands[1], operands[2], mode);\n+ riscv_vector::emit_len_op (code_for_pred_mov (mode), operands[0],\n+\t\t\t operands[1], operands[2], mode);\n DONE;\n })\n \n@@ -43,8 +43,8 @@ (define_expand \"len_store_\"\n (match_operand 3 \"const_0_operand\")]\n \"TARGET_VECTOR\"\n {\n- riscv_vector::emit_nonvlmax_op (code_for_pred_mov (mode), operands[0],\n-\t\t\t\t operands[1], operands[2], mode);\n+ riscv_vector::emit_len_op (code_for_pred_mov (mode), operands[0],\n+\t\t\t operands[1], operands[2], mode);\n DONE;\n })\n \n@@ -106,16 +106,16 @@ (define_expand \"3\"\n {\n rtx cst;\n gcc_assert (const_vec_duplicate_p(operands[2], &cst));\n- riscv_vector::emit_nonvlmax_binop (code_for_pred_scalar\n-\t\t\t\t\t (, mode),\n-\t\t\t\t\t operands[0], operands[1], cst,\n-\t\t\t\t\t NULL, mode,\n-\t\t\t\t\t mode);\n+ riscv_vector::emit_len_binop (code_for_pred_scalar\n+\t\t\t\t (, mode),\n+\t\t\t\t operands[0], operands[1], cst,\n+\t\t\t\t NULL, mode,\n+\t\t\t\t mode);\n }\n else\n- riscv_vector::emit_nonvlmax_binop (code_for_pred\n-\t\t\t\t (, mode),\n-\t\t\t\t operands[0], operands[1], operands[2],\n-\t\t\t\t NULL, mode);\n+ riscv_vector::emit_len_binop (code_for_pred\n+\t\t\t\t (, mode),\n+\t\t\t\t operands[0], operands[1], operands[2],\n+\t\t\t\t NULL, mode);\n DONE;\n })\ndiff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h\nindex 4d0589e502c..55a43d6270e 100644\n--- a/gcc/config/riscv/riscv-protos.h\n+++ b/gcc/config/riscv/riscv-protos.h\n@@ -167,10 +167,10 @@ bool legitimize_move (rtx, rtx, machine_mode);\n void emit_vlmax_vsetvl (machine_mode, rtx);\n void emit_hard_vlmax_vsetvl (machine_mode, rtx);\n void emit_vlmax_op (unsigned, rtx, rtx, machine_mode);\n-void emit_vlmax_op (unsigned, rtx, rtx, rtx, machine_mode);\n-void emit_nonvlmax_op (unsigned, rtx, rtx, rtx, machine_mode);\n-void emit_nonvlmax_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode,\n-\t\t\t machine_mode = VOIDmode);\n+void emit_vlmax_reg_op (unsigned, rtx, rtx, rtx, machine_mode);\n+void emit_len_op (unsigned, rtx, rtx, rtx, machine_mode);\n+void emit_len_binop (unsigned, rtx, rtx, rtx, rtx, machine_mode,\n+\t\t machine_mode = VOIDmode);\n enum vlmul_type get_vlmul (machine_mode);\n unsigned int get_ratio (machine_mode);\n unsigned int get_nf (machine_mode);\ndiff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc\nindex 8f46226d571..7cf5ec9f3ba 100644\n--- a/gcc/config/riscv/riscv-v.cc\n+++ b/gcc/config/riscv/riscv-v.cc\n@@ -99,27 +99,24 @@ public:\n add_vundef_operand (dest_mode);\n }\n \n- void set_len_and_policy (rtx len, bool vlmax_p)\n+ void set_len_and_policy (rtx len, bool force_vlmax = false)\n {\n+ bool vlmax_p = force_vlmax;\n gcc_assert (has_dest);\n- gcc_assert (len || vlmax_p);\n \n- if (len)\n-\tadd_input_operand (len, Pmode);\n- else\n+ if (!len)\n \t{\n-\t rtx vlmax = gen_reg_rtx (Pmode);\n-\t emit_vlmax_vsetvl (dest_mode, vlmax);\n-\t add_input_operand (vlmax, Pmode);\n+\t vlmax_p = true;\n+\t len = gen_reg_rtx (Pmode);\n+\t emit_vlmax_vsetvl (dest_mode, len);\n \t}\n \n+ add_input_operand (len, Pmode);\n+\n if (GET_MODE_CLASS (dest_mode) != MODE_VECTOR_BOOL)\n \tadd_policy_operand (get_prefer_tail_policy (), get_prefer_mask_policy ());\n \n- if (vlmax_p)\n-\tadd_avl_type_operand (avl_type::VLMAX);\n- else\n-\tadd_avl_type_operand (avl_type::NONVLMAX);\n+ add_avl_type_operand (vlmax_p ? avl_type::VLMAX : avl_type::NONVLMAX);\n }\n \n void expand (enum insn_code icode, bool temporary_volatile_p = false)\n@@ -232,14 +229,14 @@ autovec_use_vlmax_p (void)\n /* Emit an RVV unmask && vl mov from SRC to DEST. */\n static void\n emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,\n-\t machine_mode mask_mode, bool vlmax_p)\n+\t machine_mode mask_mode, bool force_vlmax = false)\n {\n insn_expander<8> e;\n e.set_dest_and_mask (mask, dest, mask_mode);\n \n e.add_input_operand (src, GET_MODE (src));\n \n- e.set_len_and_policy (len, vlmax_p);\n+ e.set_len_and_policy (len, force_vlmax);\n \n e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src));\n }\n@@ -248,8 +245,8 @@ emit_pred_op (unsigned icode, rtx mask, rtx dest, rtx src, rtx len,\n specified using SCALAR_MODE. */\n static void\n emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2,\n-\t\t rtx len, machine_mode mask_mode, machine_mode scalar_mode,\n-\t\t bool vlmax_p)\n+\t\t rtx len, machine_mode mask_mode,\n+\t\t machine_mode scalar_mode = VOIDmode)\n {\n insn_expander<9> e;\n e.set_dest_and_mask (mask, dest, mask_mode);\n@@ -267,37 +264,60 @@ emit_pred_binop (unsigned icode, rtx mask, rtx dest, rtx src1, rtx src2,\n else\n e.add_input_operand (src2, scalar_mode);\n \n- e.set_len_and_policy (len, vlmax_p);\n+ e.set_len_and_policy (len);\n \n e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src1) || MEM_P (src2));\n }\n \n+/* The RISC-V vsetvli pass uses \"known vlmax\" operations for optimization.\n+ Whether or not an instruction actually is a vlmax operation is not\n+ recognizable from the length operand alone but the avl_type operand\n+ is used instead. In general, there are two cases:\n+\n+ - Emit a vlmax operation by passing a NULL length. Here we emit\n+ a vsetvli with vlmax configuration and set the avl_type to VLMAX.\n+ - Emit an operation that uses the existing (last-set) length and\n+ set the avl_type to NONVLMAX.\n+\n+ Sometimes we also need to set the VLMAX avl_type to an operation that\n+ already uses a given length register. This can happen during or after\n+ register allocation when we are not allowed to create a new register.\n+ For that case we also allow to set the avl_type to VLMAX.\n+*/\n+\n+/* This function emits a VLMAX vsetvli followed by the actual operation. */\n void\n emit_vlmax_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode)\n {\n- emit_pred_op (icode, NULL_RTX, dest, src, NULL_RTX, mask_mode, true);\n+ emit_pred_op (icode, NULL_RTX, dest, src, NULL_RTX, mask_mode);\n }\n \n+/* This function emits an operation with a given LEN that is determined\n+ by a previously emitted VLMAX vsetvli. */\n void\n-emit_vlmax_op (unsigned icode, rtx dest, rtx src, rtx len,\n-\t machine_mode mask_mode)\n+emit_len_op (unsigned icode, rtx dest, rtx src, rtx len,\n+\t machine_mode mask_mode)\n {\n- emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, true);\n+ emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode);\n }\n \n+/* This function emits an operation with a given LEN that is known to be\n+ a preceding VLMAX. It also sets the VLMAX flag which allows further\n+ optimization in the vsetvli pass. */\n void\n-emit_nonvlmax_op (unsigned icode, rtx dest, rtx src, rtx len,\n-\t\t machine_mode mask_mode)\n+emit_vlmax_reg_op (unsigned icode, rtx dest, rtx src, rtx len,\n+\t\t machine_mode mask_mode)\n {\n- emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode, false);\n+ emit_pred_op (icode, NULL_RTX, dest, src, len, mask_mode,\n+\t\t/* Force VLMAX */ true);\n }\n \n void\n-emit_nonvlmax_binop (unsigned icode, rtx dest, rtx src1, rtx src2, rtx len,\n-\t\t machine_mode mask_mode, machine_mode scalar_mode)\n+emit_len_binop (unsigned icode, rtx dest, rtx src1, rtx src2, rtx len,\n+\t\tmachine_mode mask_mode, machine_mode scalar_mode)\n {\n- emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len, mask_mode,\n-\t\t scalar_mode, len ? false : true);\n+ emit_pred_binop (icode, NULL_RTX, dest, src1, src2, len,\n+\t\t mask_mode, scalar_mode);\n }\n \n /* Emit vid.v instruction. */\n@@ -345,14 +365,14 @@ expand_vec_series (rtx dest, rtx base, rtx step)\n \t int shift = exact_log2 (INTVAL (step));\n \t rtx shift_amount = gen_int_mode (shift, Pmode);\n \t insn_code icode = code_for_pred_scalar (ASHIFT, mode);\n-\t emit_nonvlmax_binop (icode, step_adj, vid, shift_amount,\n-\t\t\t NULL, mask_mode, Pmode);\n+\t emit_len_binop (icode, step_adj, vid, shift_amount,\n+\t\t\t NULL, mask_mode, Pmode);\n \t}\n else\n \t{\n \t insn_code icode = code_for_pred_scalar (MULT, mode);\n-\t emit_nonvlmax_binop (icode, step_adj, vid, step,\n-\t\t\t NULL, mask_mode, inner_mode);\n+\t emit_len_binop (icode, step_adj, vid, step,\n+\t\t\t NULL, mask_mode, inner_mode);\n \t}\n }\n \n@@ -367,7 +387,7 @@ expand_vec_series (rtx dest, rtx base, rtx step)\n {\n rtx result = gen_reg_rtx (mode);\n insn_code icode = code_for_pred_scalar (PLUS, mode);\n- emit_nonvlmax_binop (i 100 24127 100 23977 100 150 632k 4054 --:--:-- --:--:-- --:--:-- 636k code, result, step_adj, base,\n+ emit_len_binop (icode, result, step_adj, base,\n \t\t\t NULL, mask_mode, inner_mode);\n emit_move_insn (dest, result);\n }\n@@ -739,8 +759,8 @@ sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl,\n *scalar_op = force_reg (scalar_mode, *scalar_op);\n \n rtx tmp = gen_reg_rtx (vector_mode);\n- riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (vector_mode), tmp,\n-\t\t\t\t *scalar_op, vl, mask_mode);\n+ riscv_vector::emit_len_op (code_for_pred_broadcast (vector_mode), tmp,\n+\t\t\t *scalar_op, vl, mask_mode);\n emit_vector_func (operands, tmp);\n \n return true;\n@@ -1046,7 +1066,7 @@ expand_tuple_move (machine_mode mask_mode, rtx *ops)\n \t rtx mem = gen_rtx_MEM (subpart_mode, ops[3]);\n \n \t if (fractional_p)\n-\t\temit_vlmax_op (code_for_pred_mov (subpart_mode), subreg, mem,\n+\t\temit_vlmax_reg_op (code_for_pred_mov (subpart_mode), subreg, mem,\n \t\t\t ops[4], mask_mode);\n \t else\n \t\temit_move_insn (subreg, mem);\n@@ -1068,7 +1088,7 @@ expand_tuple_move (machine_mode mask_mode, rtx *ops)\n \t rtx mem = gen_rtx_MEM (subpart_mode, ops[3]);\n \n \t if (fractional_p)\n-\t\temit_vlmax_op (code_for_pred_mov (subpart_mode), mem, subreg,\n+\t\temit_vlmax_reg_op (code_for_pred_mov (subpart_mode), mem, subreg,\n \t\t\t ops[4], mask_mode);\n \t else\n \t\temit_move_insn (mem, subreg);\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 02d581589ac..cecb4d49092 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -7391,8 +7391,8 @@ vector_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)\n \t emitted_vlmax_vsetvl = true;\n \t }\n \n-\t riscv_vector::emit_vlmax_op (code_for_pred_mov (mode), target,\n-\t\t\t\t CONST0_RTX (mode), vl, mask_mode);\n+\t riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode), target,\n+\t\t\t\t\t CONST0_RTX (mode), vl, mask_mode);\n \n \t SET_HARD_REG_BIT (zeroed_hardregs, regno);\n \t}\ndiff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex 9ccc0d6a513..75479f27bcd 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -721,8 +721,9 @@ (define_insn_and_split \"*mov_lra\"\n else\n {\n riscv_vector::emit_vlmax_vsetvl (mode, operands[2]);\n- riscv_vector::emit_vlmax_op (code_for_pred_mov (mode),\n- \t\toperands[0], operands[1], operands[2], mode);\n+ riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode),\n+\t\t\t\t operands[0], operands[1], operands[2],\n+\t\t\t\t mode);\n }\n DONE;\n })\n@@ -741,8 +742,9 @@ (define_insn_and_split \"*mov_lra\"\n else\n {\n riscv_vector::emit_vlmax_vsetvl (mode, operands[2]);\n- riscv_vector::emit_vlmax_op (code_for_pred_mov (mode),\n- \t\toperands[0], operands[1], operands[2], mode);\n+ riscv_vector::emit_vlmax_reg_op (code_for_pred_mov (mode),\n+\t\t\t\t operands[0], operands[1], operands[2],\n+\t\t\t\t mode);\n }\n DONE;\n })\n@@ -806,7 +808,7 @@ (define_expand \"vec_duplicate\"\n \"TARGET_VECTOR\"\n {\n riscv_vector::emit_vlmax_op (code_for_pred_broadcast (mode),\n-\t\toperands[0], operands[1], mode);\n+\t\t\t\t operands[0], operands[1], mode);\n DONE;\n }\n )\n","prefixes":["v2"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE