Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision 733a1b777f16cd397b43a242d9c31761f66d3da8 (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f 733a1b777f16cd397b43a242d9c31761f66d3da8 # timeout=10 Commit message: "sched-deps: do not schedule pseudos across calls [PR108117]" > git rev-list --no-walk b4b1c6aa6d28d3afe989a6dc3210606a3d55a367 # timeout=10 First time build. Skipping changelog. [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. 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compute_convert_gain tweak. | | | 38068 modula-2, driver: Implement handling for -static-libgm2. | | | 38072 [x86] Improve ix86_expand_int_movcc to allow condition (mask) sharing. | | | 38095 modula-2: Module registration constructors need to be visible [PR108259]. | | | 38114 modula-2: Fix registration of modules via constructors [PR108183]. | | | 38235 RISC-V: Fix vsetivli instruction asm for IMM AVL | | | 38295 RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly | | | 38298 RISC-V: Fix wrong in_group flag in validate_change call function | | | 38300 RISC-V: Fix backward_propagate_worthwhile_p | | | 38308 RISC-V: Simplify codes of changing vsetvl instruction | | | 38311 RISC-V: Fix bugs of available condition. | | | 38321 [1/4] i386: Remove Meteorlake's family_model | | | 38322 [2/4] Initial Emeraldrapids Support | | | 38329 [COMMITTED] ada: Fix support of Default_Component_Value aspect on derived types | | | 38330 [COMMITTED] ada: Cannot reference ghost entity in class-wide precondition | | | 38333 [COMMITTED] ada: Simplify [Small_]Integer_Type_For | | | 38331 [COMMITTED] ada: Fix detection of function calls in object declarations | | | 38337 [COMMITTED] ada: GNAT UGN: Adjust wording in "Platform-specific Information" chapter | | | 38340 [COMMITTED] ada: Make Sem_Util.Is_Aliased_View predicate more robust | | | 38342 [COMMITTED] ada: Another small adjustment to special resolution of membership test | | | 38332 [COMMITTED] ada: Adapt frontend optimization for aggregate assignment | | | 38336 [COMMITTED] ada: Fix calling convention of foreign functions returning limited type | | | 38335 [COMMITTED] ada: Make Apply_Discriminant_Check.Denotes_Explicit_Dereference more robust | | | 38344 [COMMITTED] ada: Fix format string parsing in GNAT.Formatted_String | | | 38339 [COMMITTED] ada: Fix premature finalization of return temporary | | | 38334 [COMMITTED] ada: Fix parsing bug in GNAT.Formatted_String | | | 38341 [COMMITTED] ada: Fix GNAT.Formatted_String's handling of real values | | | 38343 [COMMITTED] ada: output.adb: fix newline being inserted when buffer is full | | | 38338 [COMMITTED] ada: Fix unescaped quotes when combining fdiagnostics-format=json and gnatdJ | | | 38358 cfgrtl: Don't try to redirect asm goto to EXIT [PR108263] | | | 38365 expr: Fix up store_expr into SUBREG_PROMOTED_* target [PR108264] | | | 38382 Various fixes for DWARF register size computation | | | 38427 PR tree-optimization/92342: Optimize b & -(a==c) in match.pd | | | 38695 gcc-11: FTBFS on hurd-i386 | | | 38731 libiberty: Handle Windows nul device in unlink-if-ordinary.c [PR108276] | | | 38739 Add link to gmplib.org | | | 38749 [PATCH-1,rs6000] Change mode and insn condition for scalar extract exp instruction | | | 38750 [PATCH-2,rs6000] Change mode and insn condition for scalar extract sig instruction | | | 38751 [PATCH-3,rs6000] Change mode and insn condition for scalar insert exp instruction | | | 38752 [PATCH-4,rs6000] Change ilp32 target check for some scalar-extract-sig and scalar-insert-exp test cases | | | 38773 [V3] rs6000: Load high and low part of 64bit constant independently | | | 38782 swap: Fix incorrect lane extraction by vec_extract() [PR106770] | | | 38812 ubsan: Avoid narrowing of multiply for -fsanitize=signed-integer-overflow [PR108256] | | | 38814 vrp: Handle pointers in maybe_set_nonzero_bits [PR108253] | | | 38815 rs6000: Don't use optimize_function_for_speed_p too early [PR108184] | | | 38817 rs6000: Make P10_FUSION honour tuning setting | | | 38818 generic-match-head: Don't assume GENERIC folding is done only early [PR108237] | | | 38825 c++: Error recovery in merge_default_template_args [PR108206] | | | 38879 [committed] libstdc++: Fix std::array::data() to be a constant expression [PR108258] | | | 38896 [V4] Use reg mode to move sub blocks for parameters and returns | | | 38935 RISC-V: Refine Phase 3 of VSETVL PASS | | | 38936 [V2] extract DF/SF/SI/HI/QI subreg from parameter word on stack | | | 38938 RISC-V: Add testcases for IMM (0 ~ 31) AVL | | | 38993 c++: mark_single_function and SFINAE [PR108282] | | | 39041 Avoid quadratic behaviour of symbol renaming | | | 39045 [ping] cp: warn uninitialized const/ref in base class [PR80681] | | | 39157 [modula2] Add missing declarations to gcc/m2/gm2-libs-min/M2RTS.def | | | 39235 [committed] libstdc++: Fix std::chrono::hh_mm_ss with unsigned rep [PR108265] | | | 39236 [committed] libstdc++: Only use std::atomic if lock free [PR108228] | | | 39237 [committed] libstdc++: Support single components in name of chrono::current_zone() [PR108211] | | | 39294 [1/1] Add link to gmplib.org | | | 39489 xtensa: Optimize stack frame adjustment more | | | 39481 [committed] openmp: Fix up finish_omp_target_clauses [PR108286] | | | 39524 PR target/89828 Inernal compiler error on -fno-omit-frame-pointer | | | 39528 modula-2: Remove uses of scalb*() and significand*() [PR107631] | | | 39603 [x86_64] Introduce insvti_highpart define_insn_and_split. | | | 39612 [COMMITTED] ada: Fix incorrect warning about unreferenced packed arrays | | | 39613 [COMMITTED] ada: Fix finalization issues in extended return statements | | | 39616 [COMMITTED] ada: Update doc for -gnatw_q | | | 39617 [COMMITTED] ada: Better error message for bad Discard_Names configuration pragma | | | 39619 [COMMITTED] ada: Revert to constrained allocation for string concatenation | | | 39614 [COMMITTED] ada: Spurious error on Lock_Free protected type with discriminants | | | 39618 [COMMITTED] ada: Fix generic instantiation of sibling package | | | 39615 [COMMITTED] ada: Adjust handling of "%g" in GNAT.Formatted_String | | | 39620 [COMMITTED] ada: Simplify new expansion of contracts | | | 39622 [COMMITTED] ada: Further adjust freezing for expansion of contracts | | | 39628 [COMMITTED] ada: Update gnatpp documentation with --layout switch | | | 39630 [COMMITTED] ada: INOX: prototype RFC on String Interpolation | | | 39624 [COMMITTED] ada: Fix spurious emissions of -gnatwj warning | | | 39621 [COMMITTED] ada: Fix pasto in comment | | | 39629 [COMMITTED] ada: Optimize class-wide objects initialized with function calls | | | 39623 [COMMITTED] ada: Do not use decimal approximation in -gnatRj output | | | 39631 [COMMITTED] ada: Fix nested generic instantiation | | | 39633 [COMMITTED] ada: Remove unhelpful special case for renamed bodies in GNATprove mode | | | 39627 [COMMITTED] ada: Flag renaming-as-spec as a body to inline | | | 39632 [COMMITTED] ada: Clean up interface handling in Expand_N_Object_Declaration | | | 39635 [COMMITTED] ada: Minor tweak to test added in previous change | | | 39661 [committed] libstdc++: Reduce size of std::bind_front(empty_type) result [PR108290] | | | 39662 [committed] libstdc++: Fix printers for Python 2 [PR108212] | | | 39663 ipa: Sort ipa_param_body_adjustments::m_replacements (PR 108110) | | | 39709 c++: class-head parsing and CPP_TEMPLATE_ID access [PR108275] | | | 39731 [committed] hppa: Fix atomic operations on PA-RISC 2.0 processors | | | 39782 wwwdocs: Note that old reload is deprecated | | | 39826 [v2,1/4] diagnostics: libcpp: Add LC_GEN linemaps to support in-memory buffers | | | 39824 [v2,2/4] diagnostics: Handle generated data locations in edit_context | | | 39827 [v2,3/4] diagnostics: libcpp: Assign real locations to the tokens inside _Pragma strings | | | 39825 [v2,4/4] diagnostics: Support generated data locations in SARIF output | | | 39968 [RISCV] Change the generation mode of `adjust_sp_rtx` from gen_insn to gen_SET. | | | 39978 [pushed] contrib: add 'contrib' to default dirs in update-copyright.py | | | 39991 Handle Windows nul device in unlink-if-ordinary.c | | | 39995 Handle Windows nul device in unlink-if-ordinary.c | | | 40003 configure: remove dependencies on gmp and mpfr when gdb is disabled | | | 40052 rs6000: Teach rs6000_opaque_type_invalid_use_p about inline asm [PR108272] | | | 40057 rs6000: Allow powerpc64 to be unset for implicit 64 bit [PR108240] | | | 40063 [committed] testsuite: Add testcases from PR108292 and PR108308 | | | 40073 Set CROSS_SYSTEM_HEADER_DIR according includedir | | | 40081 libsanitizer/mips: always build with largefile support | | | 40084 [wwwdocs] Document libstdc++ additions for GCC 12 and 13 | | | 40088 [wwwdocs] Fix typo in libstdc++ release notes | | | 40093 diagnostics: fix crash with -fdiagnostics-format=json-file | | | 40099 [committed] libstdc++: Fix deadlock in debug iterator increment [PR108288] | | | 40108 Remove legacy pre-C++ 11 definitions | | | 40109 rs6000: mark tieable between INT and FLOAT | | | 40123 [committed] libstdc++: Disable broken std::format for floating-point types [PR108221] | | | 40144 [committed] libstdc++: Fix misuse of alloca in std::bitset [PR108214] | | | 40155 libstdc++: Add feature-test macros for implemented C++23 views [PR108260] | | | 40213 libbacktrace patch committed: Only test --build-id if supported | | | 40217 Always define `WIN32_LEAN_AND_MEAN` before | | | 40232 [committed] c: C2x semantics for __builtin_tgmath | | | 40268 [committed] libstdc++: Refactor time_zone::_Impl::rules_counter [PR108235] | | | 40269 [committed] libstdc++: Suppress -Waddress warning in tzdb.cc [PR108228] | | | 40270 [modula2] PR-108182 gm2 driver mishandles target and multilib options | | | 40301 [v2] xtensa: Optimize stack frame adjustment more | | | 40302 xtensa: Optimize bitwise splicing operation | | | 40362 modula-2, driver: Do not add extra '-L' options that shadow $libdir. | | | 40381 gcc: fix gcc --help -v opertion with linker flags and input files [PR108328] | | | 40413 modula-2, libm2min: Declare abort and exit as expected. | | | 40414 [fortran] Fix common subexpression elimination with IEEE rounding (PR108329) | | | 40426 [modula2] v2 PR-108182 gm2 driver mishandles target and multilib options | | | 40444 [committed] Fix compilation of gcc.dg/atomic/c11-atomic-exec-[45].c on hpux | | | 40446 c++tools: Fix compilation of server.cc on hpux | | | 40481 [v2] xtensa: Optimize bitwise splicing operation | | | 40787 c++: Only do maybe_init_list_as_range optimization if !processing_template_decl [PR108047] | | | 40788 calls: Fix up TYPE_NO_NAMED_ARGS_STDARG_P handling [PR107453] | | | 40792 hash: do not insert deleted value to a hash_set | | | 40798 tree-optimization/101912 - testcase for fixed uninit case | | | 40799 tree-optimization/107767 - not profitable switch conversion | | | 40820 middle-end/69482 - not preserving volatile accesses | | | 40867 [nvptx] Correct pattern for popcountdi2 insn in nvptx.md. | | | 40888 middle-end/108209 - typo in genmatch.cc:commutative_op | | | 40894 [COMMITTED] ada: Simplify finalization of temporaries created for interface objects | | | 40895 [COMMITTED] ada: Remove a couple of unreachable statements | | | 40911 [x86] PR rtl-optimization/107991: peephole2 to tweak register allocation. | | | 41084 PR rtl-optimization/106421: ICE in bypass_block from non-local goto. | | | 41184 [committed] c: Check for modifiable static compound literals in inline definitions | | | 41190 Modula-2: fix documentation layout | | | 41191 RISC-V: Cleanup the codes of bitmap create and free [NFC] | | | 41195 RISC-V: Avoid redundant flow in forward fusion | | | 41203 bpf: correct bpf_print_operand for floats [PR108293] | | | 41207 RISC-V: Refine codes in backward fusion | | | 41208 RISC-V: Avoid redundant flow in backward fusion | | | 41210 RISC-V: Rename insn into rinsn for rtx_insn * | | | 41211 RISC-V: Remove dirty_pat since it is redundant | | | 41214 RISC-V: Add probability model of each block to prevent endless loop of Phase 3 | | | 41217 RISC-V: Call DCE to remove redundant instructions created by the PASS | | | 41218 RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS | | | 41219 RISC-V: Adjust testcases for AVL=REG support | | | 41225 RISC-V: Add testcases for AVL=REG support | | | 41228 RISC-V: Add the rest testcases of AVL=REG support | | | 41253 [Modula2] PR-108142 Many empty directories created in the build directory | | | 41280 xtensa: Make instruction cost estimation for size more accurate | | | 41292 More znver4 x86-tune flags | | | 41368 [Committed] IBM zSystems: Make -fcall-saved-... work. | | | 41382 tree-optimization/108314 - avoid BIT_NOT optimization for extract-last | | | 41384 [1/2] libstdc++: Enable string_view in freestanding | | | 41383 [2/2] libstdc++: Fix a few !HOSTED test regressions | | | 41412 [1/2] OpenMP: Add lang hooks + run-time filled map arrays for Fortran deep mapping of DT | | | 41418 [committed,1/3] libstdc++: Fix std::span constraint for sizeof(size_t) < sizeof(int) [PR108221] | | | 41417 [committed,2/3] libstdc++: Fix some algos for 16-bit size_t [PR108221] | | | 41416 [committed,3/3] libstdc++: Fix tzdb.cc to compile with -fno-exceptions | | | 41451 [v2] libstdc++: Fix Unicode codecvt and add tests [PR86419] | | | 41476 rs6000: Enhance lowpart/highpart DI->SF by mtvsrws/mtvsrd | | | 41489 [PING] arm: Split up MVE _Generic associations to prevent type clashes [PR107515] | | | 41512 gcc: emit DW_AT_name for DW_TAG_GNU_formal_parameter_pack [PR70536] | | | 41532 tree-optimization/106293 - missed DSE with virtual LC PHI | | | 41603 [v2] bpf: correct bpf_print_operand for floats [PR108293] | | | 41672 Fortran: frontend passes do_subscript leaks gmp memory [PR97345] | | | 41736 ifcvt.cc: Prevent excessive if-conversion for conditional moves | | | 41776 tree-optimization/106293 - fix testcase | | | 41854 fortran: Fix up function types for realloc and sincos{,f,l} builtins [PR108349] | | | 41870 c++: Avoid some false positive -Wfloat-conversion warnings with extended precision [PR108285] | | | 41871 Resolve bugzilla #108150 and #108192 for mingw | | | 41872 [10/15,V7] arm: Implement cortex-M return signing address codegen | | | 41873 Fix PR tree-optimization/108199 | | | 41882 [Committed] IBM zSystems: Use NAND instruction to implement bit not | | | 41883 switch expansion: limit JT growth param values | | | 41890 tree-optimization/108353 - copyprop iteration order | | | 41900 [gcc-12,backport] strlen: do not use cond_expr for boundaries | | | 41916 [PING] nvptx: Make 'nvptx_uniform_warp_check' fit for non-full-warp execution (was: [committed][nvptx] Add uniform_warp_check insn) | | | 41920 [PING] Add '-Wno-complain-wrong-lang', and use it in 'gcc/testsuite/lib/target-supports.exp:check_compile' and elsewhere | | | 41922 [RISCV] Add 'Zfa' extension according to riscv-isa-manual | | | 41930 [PING^3] nvptx: stack size limits are relevant for execution only (was: [PATCH, testsuite] Add effective target stack_size) | | | 41941 [PING^2] nvptx: Support global constructors/destructors via 'collect2' | | | 41944 [PING] nvptx: Support global constructors/destructors via 'collect2' for offloading (was: nvptx: Support global constructors/destructors via 'collect2') | | | 41948 tree-optimization/108352 - FSM threads creating irreducible loops | | | 41951 [PING] nvptx: '-mframe-malloc-threshold', '-Wframe-malloc-threshold' (was: Handling of large stack objects in GPU code generation -- maybe transform into heap allocation?) | | | 41973 [committed] rs6000/test: Make ppc-fortran.exp only available for PowerPC target | | | 41979 rs6000: Imply VSX early to adopt some checkings on conflict [PR108240] | | | 42016 [v3,1/2] aarch64: fix warning emission for ABI break since GCC 9.1 | | | 42017 [v3,2/2] aarch64: Fix bit-field alignment in param passing [PR105549] | | | 42027 [1/2,v2] arm: Add define_attr to to create a mapping between MVE predicated and unpredicated insns | | | 42035 [2/2,v2] arm: Add support for MVE Tail-Predicated Low Overhead Loops | | | 42124 c++: Avoid incorrect shortening of divisions [PR108365] | | | 42127 c: Don't emit DEBUG_BEGIN_STMTs for K&R function argument declarations [PR105972] | | | 42126 [OG12,committed] amdgcn, libgomp: custom USM allocator | | | 42204 [committed] analyzer: fix leak false positives on "*UNKNOWN = PTR; " [PR108252] | | | 42208 [committed] wwwdocs: gcc-8: Properly spell "command-line option" | | | 42209 [committed] config-list.mk: Remove obsolete FreeBSD targets | | | 42221 gimple-fold.h: Add missing gimple-iterator.h | | | 42222 [v2,RISCV] Add 'Zfa' extension according to riscv-isa-manual | | | 42251 [1/2] xtensa: Tune "*btrue" insn pattern | | | 42252 [2/2] xtensa: Optimize ctzsi2 and ffssi2 a bit | | | 42258 [v3,RISCV] Add 'Zfa' extension according to riscv-isa-manual | | | 42823 [18/18] hash table: enforce testing is_empty before is_deleted | | | 42273 [v4,RISCV] Add 'Zfa' extension according to riscv-isa-manual | | | 42354 Fortran/OpenMP: Reject non-scalar 'holds' expr in 'omp assume(s)' [PR107424] | | | 42421 tree-optimization/99412 - reassoc and reduction chains | | | 42442 nvptx: Avoid deadlock in 'cuStreamAddCallback' callback, error case (was: [PATCH 6/6, OpenACC, libgomp] Async re-work, nvptx changes) | | | 42780 c, c++, v2: Avoid incorrect shortening of divisions [PR108365] | | | 42806 [committed] libstdc++: Update shared library version history in manual | | | 42809 [committed] libstdc++: Extend max_align_t special case to 64-bit HP-UX [PR77691] | | | 42812 libstdc++: Make forward to C version if included by C | | | 42822 libstdc++: Fix unintended layout change to std::basic_filebuf [PR108331] | | | 42856 [1/1] Replace flag_strict_flex_arrays with DECL_NOT_FLEXARRAY in middle-end | | | 42876 [committed] libstdc++: Do not include in concurrency headers | | | 42878 [committed] libstdc++: Fix exports for IEEE128 versions of __try_use_facet [PR108327] | | | 42880 modula-2: Handle pass '-v' option to the compiler. | | | 42883 c, c++: Allow ignoring -Winit-self through pragmas [PR105593] | | | 42884 x86: Avoid -Wuninitialized warnings on _mm*_undefined_* in C++ [PR105593] | | | 42909 [v5] LoongArch: Fixed a compilation failure with '%c' in inline assembly [PR107731]. | | | 43052 [1/9] aarch64: Don't add crtfastmath.o for -shared | | | 43054 [2/9] alpha: Don't add crtfastmath.o for -shared | | | 43053 [3/9] arm: Don't add crtfastmath.o for -shared | | | 43055 [4/9] ia64: Don't add crtfastmath.o for -shared | | | 43056 [5/9] loongarch: Don't add crtfastmath.o for -shared | | | 43057 [6/9] mips: Don't add crtfastmath.o for -shared | | | 43058 [7/9] sparc: Don't add crtfastmath.o for -shared | | | 43059 [8/9] solaris2: Don't add crtfastmath.o for -shared | | | 43060 [9/9] Clarify -shared effect on crtfastmath.o | | | 43075 Sync LTO type_for_mode with c-family/ | | | 43100 [1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx | | | 43118 [1/1,fwprop] : Add the support of forwarding the vec_duplicate rtx | | | 43121 tree-optimization/108387 - ICE with VN handling of x << C as x * (1< FETCH_HEAD + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master Updating 733a1b777..cf467fb93 Fast-forward gcc/config/pa/pa-linux.h | 3 - gcc/config/pa/pa.cc | 4 +- gcc/config/pa/pa.h | 12 +- gcc/config/pa/pa.md | 124 +++++++++++++-- gcc/config/pa/pa.opt | 4 + gcc/doc/invoke.texi | 171 +++++++++++++-------- libgcc/config.host | 4 +- libgcc/config/pa/linux-atomic.c | 79 ++++++++-- libgcc/config/pa/sync-libfuncs.c | 324 +++++++++++++++++++++++++++++++++++++++ libgcc/config/pa/t-netbsd | 1 + libgcc/config/pa/t-openbsd | 1 + libgcc/config/pa/t-pa64-hpux | 4 + libgcc/config/pa/t-pa64-linux | 8 + 13 files changed, 628 insertions(+), 111 deletions(-) create mode 100644 libgcc/config/pa/sync-libfuncs.c create mode 100644 libgcc/config/pa/t-pa64-hpux create mode 100644 libgcc/config/pa/t-pa64-linux + git push -u origin upstream-master To github.com:plctlab/patchwork-gcc.git 733a1b777..cf467fb93 upstream-master -> upstream-master branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master Updating 733a1b777..cf467fb93 Fast-forward gcc/config/pa/pa-linux.h | 3 - gcc/config/pa/pa.cc | 4 +- gcc/config/pa/pa.h | 12 +- gcc/config/pa/pa.md | 124 +++++++++++++-- gcc/config/pa/pa.opt | 4 + gcc/doc/invoke.texi | 171 +++++++++++++-------- libgcc/config.host | 4 +- libgcc/config/pa/linux-atomic.c | 79 ++++++++-- libgcc/config/pa/sync-libfuncs.c | 324 +++++++++++++++++++++++++++++++++++++++ libgcc/config/pa/t-netbsd | 1 + libgcc/config/pa/t-openbsd | 1 + libgcc/config/pa/t-pa64-hpux | 4 + libgcc/config/pa/t-pa64-linux | 8 + 13 files changed, 628 insertions(+), 111 deletions(-) create mode 100644 libgcc/config/pa/sync-libfuncs.c create mode 100644 libgcc/config/pa/t-pa64-hpux create mode 100644 libgcc/config/pa/t-pa64-linux + git push -u origin master To github.com:plctlab/patchwork-gcc.git 733a1b777..cf467fb93 master -> master branch 'master' set up to track 'origin/master'. + branchname=series17758-patch43560 ++ git branch -a ++ grep 'series17758-patch43560$' + checkbranch= + checkbranchresult=null + '[' null = series17758-patch43560 ']' + git checkout -b series17758-patch43560 Switched to a new branch 'series17758-patch43560' ++ curl https://patchwork.plctlab.org/api/1.2/series/17758/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1390 100 1390 0 0 30217 0 --:--:-- --:--:-- --:--:-- 29574 100 1390 100 1390 0 0 30217 0 --:--:-- --:--:-- --:--:-- 29574 + series_response='{"id":17758,"url":"https://patchwork.plctlab.org/api/1.2/series/17758/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=17758","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[committed] hppa: Fix support for atomic loads and stores on hppa","date":"2023-01-13T19:39:51","submitter":{"id":3283,"url":"https://patchwork.plctlab.org/api/1.2/people/3283/","name":"John David Anglin","email":"dave@parisc-linux.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/17758/mbox/","cover_letter":null,"patches":[{"id":43560,"url":"https://patchwork.plctlab.org/api/1.2/patches/43560/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/","msgid":"","list_archive_url":null,"date":"2023-01-13T19:39:51","name":"[committed] hppa: Fix support for atomic loads and stores on hppa","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' ++ echo '{"id":17758,"url":"https://patchwork.plctlab.org/api/1.2/series/17758/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=17758","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[committed] hppa: Fix support for atomic loads and stores on hppa","date":"2023-01-13T19:39:51","submitter":{"id":3283,"url":"https://patchwork.plctlab.org/api/1.2/people/3283/","name":"John David Anglin","email":"dave@parisc-linux.org"},"version":1,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/17758/mbox/","cover_letter":null,"patches":[{"id":43560,"url":"https://patchwork.plctlab.org/api/1.2/patches/43560/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/","msgid":"","list_archive_url":null,"date":"2023-01-13T19:39:51","name":"[committed] hppa: Fix support for atomic loads and stores on hppa","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/"}]}' + patchid_patchurl='"43560,https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/"' + echo '"43560,https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/"' + IFS=, + read -r series_patch_id series_patch_url ++ echo '"43560' ++ sed 's/"//g' + series_patch_id=43560 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++ git rev-parse HEAD + commitid_before=cf467fb93b7b92330ddcb9c8fe7c93df45ce8e40 + eval '+++ declare -p bout bret declare -- bout="Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied." declare -- bret="0" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 45758 100 45758 0 0 744k 0 --:--:-- --:--:-- --:--:-- 744k +++ bout='\''\'\'''\''Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied.'\''\'\'''\'' +++ bret=0'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 45758 100 45758 0 0 744k 0 --:--:-- --:--:-- --:--:-- 744k +++ bout='\''Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied.'\'' +++ bret=0"' ++ +++ declare -p bout bret /tmp/jenkins12622386046591908156.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied.' ++ declare -- bret=0 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 45758 100 45758 0 0 744k 0 --:--:-- --:--:-- --:--:-- 744k +++ bout='\''Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied.'\'' +++ bret=0' /tmp/jenkins12622386046591908156.sh: line 168: ++: command not found ++ ++ declare -p berr /tmp/jenkins12622386046591908156.sh: line 169: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/ ++++ git am -3 --empty=drop % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 45758 100 45758 0 0 744k 0 --:--:-- --:--:-- --:--:-- 744k +++ bout='\''Applying: hppa: Fix support for atomic loads and stores on hppa Using index info to reconstruct a base tree... M gcc/config/pa/pa-linux.h M gcc/config/pa/pa.cc M gcc/config/pa/pa.h M gcc/config/pa/pa.md M gcc/config/pa/pa.opt M gcc/doc/invoke.texi M libgcc/config.host M libgcc/config/pa/linux-atomic.c M libgcc/config/pa/t-netbsd M libgcc/config/pa/t-openbsd Falling back to patching base and 3-way merge... Auto-merging gcc/doc/invoke.texi No changes -- Patch already applied.'\'' +++ bret=0' ++ git rev-parse HEAD + commitid_after=cf467fb93b7b92330ddcb9c8fe7c93df45ce8e40 + '[' 0 = 0 ']' + '[' cf467fb93b7b92330ddcb9c8fe7c93df45ce8e40 = cf467fb93b7b92330ddcb9c8fe7c93df45ce8e40 ']' + submit_check warning 'Repeat Merge' https://patchwork.plctlab.org/jenkins/job/gcc-patch/3634/consoleText 'Git am fail log' + check_state=warning + patch_state='Repeat Merge' + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/3634/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/3634/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/43560/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 965 100 425 100 540 13281 16875 --:--:-- --:--:-- --:--:-- 30156 {"id":4042,"url":"https://patchwork.plctlab.org/api/patches/43560/checks/4042/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-01-13T20:16:16.773579","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/3634/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F 'state=Repeat Merge' https://patchwork.plctlab.org/api/1.2/patches/43560/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":43560,"url":"https://patchwork.plctlab.org/api/1.2/patches/43560/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"","list_archive_url":null,"date":"2023-01-13T19:39:51","name":"[committed] hppa: Fix support for atomic loads and stores on hppa","commit_ref":null,"pull_url":null,"state":"repeat-merge","archived":false,"hash":"af27063112183d95b3e40461ff52ed6d7c426c58","submitter":{"id":3283,"url":"https://patchwork.plctlab.org/api/1.2/people/3283/","name":"John David Anglin","email":"dave@parisc-linux.org"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/Y8Gzh4bMh3n/RVyo@mx3210.localdomain/mbox/","series":[{"id":17758,"url":"https://patchwork.plctlab.org/api/1.2/series/17758/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=17758","date":"2023-01-13T19:39:51","name":"[committed] hppa: Fix support for atomic loads and stores on hppa","version":1,"mbox":"https://patchwork.plctlab.org/series/17758/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/43560/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/43560/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp449110wrt;\n Fri, 13 Jan 2023 11:40:51 -0800 (PST)","from sourceware.org (server2.sourceware.org. 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It's possible we need\nadditional atomic load support for this case but I think that's\nunnecessary since hppa requires strict alignment.\n\nWe could use an array of locks in sync-libfuncs.c to improve\nperformance but I kept things simple for now.\n\nCommitted to trunk.\n\nDave\n---\n\nFix support for atomic loads and stores on hppa.\n\nThis change updates the atomic libcall support to fix the following\nissues:\n\n1) A internal compiler error with -fno-sync-libcalls.\n2) When sync libcalls are disabled, we don't generate libcalls for\n libatomic.\n3) There is no sync libcall support for targets other than linux.\n As a result, non-atomic stores are silently emitted for types\n smaller or equal to the word size. There are now a few atomic\n libcalls in the libgcc code, so we need sync support on all\n targets.\n\n2023-01-13 John David Anglin \n\ngcc/ChangeLog:\n\n\t* config/pa/pa-linux.h (TARGET_SYNC_LIBCALL): Delete define.\n\t* config/pa/pa.cc (pa_init_libfuncs): Use MAX_SYNC_LIBFUNC_SIZE\n\tdefine.\n\t* config/pa/pa.h (TARGET_SYNC_LIBCALLS): Use flag_sync_libcalls.\n\t(MAX_SYNC_LIBFUNC_SIZE): Define.\n\t(TARGET_CPU_CPP_BUILTINS): Define __SOFTFP__ when soft float is\n\tenabled.\n\t* config/pa/pa.md (atomic_storeqi): Emit __atomic_exchange_1\n\tlibcall when sync libcalls are disabled.\n\t(atomic_storehi, atomic_storesi, atomic_storedi): Likewise.\n\t(atomic_loaddi): Emit __atomic_load_8 libcall when sync libcalls\n\tare disabled on 32-bit target.\n\t* config/pa/pa.opt (matomic-libcalls): New option.\n\t* doc/invoke.texi (HPPA Options): Update.\n\nlibgcc/ChangeLog:\n\n\t* config.host (hppa*64*-*-linux*): Adjust tmake_file to use\n\tpa/t-pa64-linux.\n\t(hppa*64*-*-hpux11*): Adjust tmake_file to use pa/t-pa64-hpux\n\tinstead of pa/t-hpux and pa/t-pa64.\n\t* config/pa/linux-atomic.c: Define u32 type.\n\t(ATOMIC_LOAD): Define new macro to implement atomic_load_1,\n\tatomic_load_2, atomic_load_4 and atomic_load_8. Update sync\n\tdefines to use atomic_load calls for type.\n\t(SYNC_LOCK_LOAD_2): New macro to implement __sync_lock_load_8.\n\t* config/pa/sync-libfuncs.c: New file.\n\t* config/pa/t-netbsd (LIB2ADD_ST): Define.\n\t* config/pa/t-openbsd (LIB2ADD_ST): Define.\n\t* config/pa/t-pa64-hpux: New file.\n\t* config/pa/t-pa64-linux: New file.","diff":"diff --git a/gcc/config/pa/pa-linux.h b/gcc/config/pa/pa-linux.h\nindex 5af11a1df80..1073f42bd6b 100644\n--- a/gcc/config/pa/pa-linux.h\n+++ b/gcc/config/pa/pa-linux.h\n@@ -133,9 +133,6 @@ along with GCC; see the file COPYING3. If not see\n #undef TARGET_GAS\n #define TARGET_GAS 1\n \n-#undef TARGET_SYNC_LIBCALL\n-#define TARGET_SYNC_LIBCALL 1\n-\n /* The SYNC operations are implemented as library functions, not\n INSN patterns. As a result, the HAVE defines for the patterns are\n not defined. We need to define them to generate the corresponding\ndiff --git a/gcc/config/pa/pa.cc b/gcc/config/pa/pa.cc\nindex 9f43802075f..b43a91f2edb 100644\n--- a/gcc/config/pa/pa.cc\n+++ b/gcc/config/pa/pa.cc\n@@ -5940,8 +5940,8 @@ pa_init_libfuncs (void)\n \t\t\t\"_U_Qfcnvxf_udbl_to_quad\");\n }\n \n- if (TARGET_SYNC_LIBCALL)\n- init_sync_libfuncs (8);\n+ if (TARGET_SYNC_LIBCALLS)\n+ init_sync_libfuncs (MAX_SYNC_LIBFUNC_SIZE);\n }\n \n /* HP's millicode routines mean something special to the assembler.\ndiff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h\nindex bafdf602138..93d6f53f97f 100644\n--- a/gcc/config/pa/pa.h\n+++ b/gcc/config/pa/pa.h\n@@ -72,10 +72,12 @@ extern unsigned long total_code_bytes;\n #define HPUX_LONG_DOUBLE_LIBRARY 0\n #endif\n \n-/* Linux kernel atomic operation support. */\n-#ifndef TARGET_SYNC_LIBCALL\n-#define TARGET_SYNC_LIBCALL 0\n-#endif\n+/* Sync libcall support. */\n+#define TARGET_SYNC_LIBCALLS (flag_sync_libcalls)\n+\n+/* The maximum size of the sync library functions supported. DImode\n+ is supported on 32-bit targets using floating point loads and stores. */\n+#define MAX_SYNC_LIBFUNC_SIZE 8\n \n /* The following three defines are potential target switches. The current\n defines are optimal given the current capabilities of GAS and GNU ld. */\n@@ -173,6 +175,8 @@ do {\t\t\t\t\t\t\t\t\\\n builtin_define(\"_PA_RISC1_0\");\t\t\t\t\\\n if (HPUX_LONG_DOUBLE_LIBRARY)\t\t\t\t\\\n builtin_define(\"__SIZEOF_FLOAT128__=16\");\t\t\\\n+ if (TARGET_SOFT_FLOAT)\t\t\t\t\t\\\n+ builtin_define(\"__SOFTFP__\");\t\t\t\t\\\n } while (0)\n \n /* An old set of OS defines for various BSD-like systems. */\ndiff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md\nindex 41382271e54..71f391f2bf7 100644\n--- a/gcc/config/pa/pa.md\n+++ b/gcc/config/pa/pa.md\n@@ -10360,7 +10360,23 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n ;; doubleword loads and stores are not guaranteed to be atomic\n ;; when referencing the I/O address space.\n \n-;; These patterns are at the bottom so the non atomic versions are preferred.\n+;; Atomic and sync libcalls use different lock sets. Great care is\n+;; needed if both are used in a single application.\n+\n+;; Atomic load and store libcalls are enabled by the -matomic-libcalls\n+;; option. This option is not enabled by default as the generated\n+;; libcalls depend on libatomic which is not built until the end of\n+;; the gcc build. For loads, we only need an atomic libcall for DImode.\n+;; Sync libcalls are not generated when atomic libcalls are enabled.\n+\n+;; Sync libcalls are enabled by default when supported. They can be\n+;; disabled by the -fno-sync-libcalls option. Sync libcalls always\n+;; use a single memory store in their implementation, even for DImode.\n+;; DImode stores are done using either std or fstd. Thus, we only\n+;; need a sync load libcall for DImode when we don't have an atomic\n+;; processor load available for the mode (TARGET_SOFT_FLOAT).\n+\n+;; Implement atomic QImode store using exchange.\n \n (define_expand \"atomic_storeqi\"\n [(match_operand:QI 0 \"memory_operand\") ;; memory\n@@ -10368,19 +10384,30 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n (match_operand:SI 2 \"const_int_operand\")] ;; model\n \"\"\n {\n- if (TARGET_SYNC_LIBCALL)\n+ rtx addr, libfunc;\n+\n+ if (TARGET_SYNC_LIBCALLS)\n {\n- rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, QImode);\n- rtx addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = optab_libfunc (sync_lock_test_and_set_optab, QImode);\n+ emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n+\t\t\t operands[1], QImode);\n+ DONE;\n+ }\n \n+ if (TARGET_ATOMIC_LIBCALLS)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = init_one_libfunc (\"__atomic_exchange_1\");\n emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n \t\t\t operands[1], QImode);\n DONE;\n }\n+\n FAIL;\n })\n \n-;; Implement atomic HImode stores using exchange.\n+;; Implement atomic HImode store using exchange.\n \n (define_expand \"atomic_storehi\"\n [(match_operand:HI 0 \"memory_operand\") ;; memory\n@@ -10388,15 +10415,26 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n (match_operand:SI 2 \"const_int_operand\")] ;; model\n \"\"\n {\n- if (TARGET_SYNC_LIBCALL)\n+ rtx addr, libfunc;\n+\n+ if (TARGET_SYNC_LIBCALLS)\n {\n- rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, HImode);\n- rtx addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = optab_libfunc (sync_lock_test_and_set_optab, HImode);\n+ emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n+\t\t\t operands[1], HImode);\n+ DONE;\n+ }\n \n+ if (TARGET_ATOMIC_LIBCALLS)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = init_one_libfunc (\"__atomic_exchange_2\");\n emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n \t\t\t operands[1], HImode);\n DONE;\n }\n+\n FAIL;\n })\n \n@@ -10408,20 +10446,39 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n (match_operand:SI 2 \"const_int_operand\")] ;; model\n \"\"\n {\n- if (TARGET_SYNC_LIBCALL)\n+ rtx addr, libfunc;\n+\n+ if (TARGET_SYNC_LIBCALLS)\n {\n- rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, SImode);\n- rtx addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = optab_libfunc (sync_lock_test_and_set_optab, SImode);\n+ emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n+\t\t\t operands[1], SImode);\n+ DONE;\n+ }\n \n+ if (TARGET_ATOMIC_LIBCALLS)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = init_one_libfunc (\"__atomic_exchange_4\");\n emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n \t\t\t operands[1], SImode);\n DONE;\n }\n+\n FAIL;\n })\n \n ;; Implement atomic DImode load.\n \n+;; We need an atomic or sync libcall whenever the processor load or\n+;; store used for DImode is not atomic. The 32-bit libatomic\n+;; implementation uses a pair of stw instructions. They are not\n+;; atomic, so we need to call __atomic_load_8. The linux libgcc\n+;; sync implementation uses a std or fstd instruction. They are\n+;; atomic, so we only need to call __sync_load_8 when the load\n+;; operation would not be atomic (e.g., 32-bit TARGET_SOFT_FLOAT).\n+\n (define_expand \"atomic_loaddi\"\n [(match_operand:DI 0 \"register_operand\") ;; val out\n (match_operand:DI 1 \"memory_operand\") ;; memory\n@@ -10429,12 +10486,35 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n \"\"\n {\n enum memmodel model;\n+ rtx addr, libfunc;\n \n- if (TARGET_64BIT || TARGET_SOFT_FLOAT)\n+ if (TARGET_64BIT)\n FAIL;\n \n+ if (TARGET_SYNC_LIBCALLS && MAX_SYNC_LIBFUNC_SIZE >= 8 && TARGET_SOFT_FLOAT)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[1], 0));\n+ libfunc = init_one_libfunc (\"__sync_load_8\");\n+ emit_library_call_value (libfunc, operands[0], LCT_NORMAL, DImode,\n+\t\t\t addr, Pmode);\n+ DONE;\n+ }\n+\n+ if (TARGET_ATOMIC_LIBCALLS && TARGET_SOFT_FLOAT)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[1], 0));\n+ libfunc = init_one_libfunc (\"__atomic_load_8\");\n+ emit_library_call_value (libfunc, operands[0], LCT_NORMAL, DImode,\n+\t\t\t addr, Pmode);\n+ DONE;\n+ }\n+\n+ if (TARGET_SOFT_FLOAT)\n+ FAIL;\n+\n+ /* Fallback to processor load with barriers. */\n model = memmodel_from_int (INTVAL (operands[2]));\n- operands[1] = force_reg (SImode, XEXP (operands[1], 0));\n+ operands[1] = force_reg (Pmode, XEXP (operands[1], 0));\n if (is_mm_seq_cst (model))\n expand_mem_thread_fence (model);\n emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1]));\n@@ -10460,12 +10540,21 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n \"\"\n {\n enum memmodel model;\n+ rtx addr, libfunc;\n \n- if (TARGET_SYNC_LIBCALL)\n+ if (TARGET_SYNC_LIBCALLS && MAX_SYNC_LIBFUNC_SIZE >= 8)\n {\n- rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, DImode);\n- rtx addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = optab_libfunc (sync_lock_test_and_set_optab, DImode);\n+ emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n+\t\t\t operands[1], DImode);\n+ DONE;\n+ }\n \n+ if (TARGET_ATOMIC_LIBCALLS)\n+ {\n+ addr = convert_memory_address (Pmode, XEXP (operands[0], 0));\n+ libfunc = init_one_libfunc (\"__atomic_exchange_8\");\n emit_library_call (libfunc, LCT_NORMAL, VOIDmode, addr, Pmode,\n \t\t\t operands[1], DImode);\n DONE;\n@@ -10474,8 +10563,9 @@ add,l %2,%3,%3\\;bv,n %%r0(%3)\"\n if (TARGET_64BIT || TARGET_SOFT_FLOAT)\n FAIL;\n \n+ /* Fallback to processor store with barriers. */\n model = memmodel_from_int (INTVAL (operands[2]));\n- operands[0] = force_reg (SImode, XEXP (operands[0], 0));\n+ operands[0] = force_reg (Pmode, XEXP (operands[0], 0));\n if (operands[1] != CONST0_RTX (DImode))\n operands[1] = force_reg (DImode, operands[1]);\n expand_mem_thread_fence (model);\ndiff --git a/gcc/config/pa/pa.opt b/gcc/config/pa/pa.opt\nindex 58b59f8f0e8..2d074f5fe88 100644\n--- a/gcc/config/pa/pa.opt\n+++ b/gcc/config/pa/pa.opt\n@@ -37,6 +37,10 @@ march=2.0\n Target RejectNegative\n Generate PA2.0 code (requires binutils 2.10 or later).\n \n+matomic-libcalls\n+Target Var(TARGET_ATOMIC_LIBCALLS) Init(1)\n+Generate libcalls for atomic loads and stores when sync libcalls are disabled.\n+\n mbig-switch\n Target Ignore\n Does nothing. Preserved for backward compatibility.\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 701c228bd0a..474dcaed5dc 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -975,17 +975,18 @@ Objective-C and Objective-C++ Dialects}.\n \n @emph{HPPA Options}\n @gccoptlist{-march=@var{architecture-type} @gol\n+-matomic-libcalls -mbig-switch @gol\n -mcaller-copies -mdisable-fpregs -mdisable-indexing @gol\n--mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol\n+-mordered -mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol\n -mfixed-range=@var{register-range} @gol\n--mjump-in-delay -mlinker-opt -mlong-calls @gol\n--mlong-load-store -mno-disable-fpregs @gol\n+-mcoherent-ldcw -mjump-in-delay -mlinker-opt -mlong-calls @gol\n+-mlong-load-store -mno-atomic-libcalls -mno-disable-fpregs @gol\n -mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol\n -mno-jump-in-delay -mno-long-load-store @gol\n -mno-portable-runtime -mno-soft-float @gol\n -mno-space-regs -msoft-float -mpa-risc-1-0 @gol\n -mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime @gol\n--mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol\n+-mschedule=@var{cpu-type} -mspace-regs -msoft-mult -msio -mwsio @gol\n -munix=@var{unix-std} -nolibdld -static -threads}\n \n @emph{IA-64 Options}\n@@ -24891,6 +24892,33 @@ other way around.\n @opindex mpa-risc-2-0\n Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.\n \n+@item -matomic-libcalls\n+@opindex matomic-libcalls\n+@opindex mno-atomic-libcalls\n+Generate libcalls for atomic loads and stores when sync libcalls are disabled.\n+This option is enabled by default. It only affects the generation of\n+atomic libcalls by the HPPA backend.\n+\n+Both the sync and @file{libatomic} libcall implementations use locking.\n+As a result, processor stores are not atomic with respect to other\n+atomic operations. Processor loads up to DImode are atomic with\n+respect to other atomic operations provided they are implemented as\n+a single access.\n+\n+The PA-RISC architecture does not support any atomic operations in\n+hardware except for the @code{ldcw} instruction. Thus, all atomic\n+support is implemented using sync and atomic libcalls. Sync libcall\n+support is in @file{libgcc.a}. Atomic libcall support is in\n+@file{libatomic}.\n+\n+This option generates @code{__atomic_exchange} calls for atomic stores.\n+It also provides special handling for atomic DImode accesses on 32-bit\n+targets.\n+\n+@item -mbig-switch\n+@opindex mbig-switch\n+Does nothing. Preserved for backward compatibility.\n+\n @item -mcaller-copies\n @opindex mcaller-copies\n The caller copies function arguments passed by hidden reference. This\n@@ -24899,30 +24927,19 @@ option should be used with care as it is not compatible with the default\n passed by hidden reference and the option provides better compatibility\n with OpenMP.\n \n-@item -mjump-in-delay\n-@opindex mjump-in-delay\n-This option is ignored and provided for compatibility purposes only.\n+@item -mcoherent-ldcw\n+@opindex mcoherent-ldcw\n+Use ldcw/ldcd coherent cache-control hint.\n \n @item -mdisable-fpregs\n @opindex mdisable-fpregs\n-Prevent floating-point registers from being used in any manner. This is\n-necessary for compiling kernels that perform lazy context switching of\n-floating-point registers. If you use this option and attempt to perform\n-floating-point operations, the compiler aborts.\n+Disable floating-point registers. Equivalent to @code{-msoft-float}.\n \n @item -mdisable-indexing\n @opindex mdisable-indexing\n Prevent the compiler from using indexing address modes. This avoids some\n rather obscure problems when compiling MIG generated code under MACH@.\n \n-@item -mno-space-regs\n-@opindex mno-space-regs\n-@opindex mspace-regs\n-Generate code that assumes the target has no space registers. This allows\n-GCC to generate faster indirect calls and use unscaled index address modes.\n-\n-Such code is suitable for level 0 PA systems and kernels.\n-\n @item -mfast-indirect-calls\n @opindex mfast-indirect-calls\n Generate code that assumes calls never cross space boundaries. This\n@@ -24939,57 +24956,10 @@ useful when compiling kernel code. A register range is specified as\n two registers separated by a dash. Multiple register ranges can be\n specified separated by a comma.\n \n-@item -mlong-load-store\n-@opindex mlong-load-store\n-Generate 3-instruction load and store sequences as sometimes required by\n-the HP-UX 10 linker. This is equivalent to the @samp{+k} option to\n-the HP compilers.\n-\n-@item -mportable-runtime\n-@opindex mportable-runtime\n-Use the portable calling conventions proposed by HP for ELF systems.\n-\n @item -mgas\n @opindex mgas\n Enable the use of assembler directives only GAS understands.\n \n-@item -mschedule=@var{cpu-type}\n-@opindex mschedule\n-Schedule code according to the constraints for the machine type\n-@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}\n-@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer\n-to @file{/usr/lib/sched.models} on an HP-UX system to determine the\n-proper scheduling option for your machine. The default scheduling is\n-@samp{8000}.\n-\n-@item -mlinker-opt\n-@opindex mlinker-opt\n-Enable the optimization pass in the HP-UX linker. Note this makes symbolic\n-debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9\n-linkers in which they give bogus error messages when linking some programs.\n-\n-@item -msoft-float\n-@opindex msoft-float\n-Generate output containing library calls for floating point.\n-@strong{Warning:} the requisite libraries are not available for all HPPA\n-targets. Normally the facilities of the machine's usual C compiler are\n-used, but this cannot be done directly in cross-compilation. You must make\n-your own arrangements to provide suitable library functions for\n-cross-compilation.\n-\n-@option{-msoft-float} changes the calling convention in the output file;\n-therefore, it is only useful if you compile @emph{all} of a program with\n-this option. In particular, you need to compile @file{libgcc.a}, the\n-library that comes with GCC, with @option{-msoft-float} in order for\n-this to work.\n-\n-@item -msio\n-@opindex msio\n-Generate the predefine, @code{_SIO}, for server IO@. The default is\n-@option{-mwsio}. This generates the predefines, @code{__hp9000s700},\n-@code{__hp9000s700__} and @code{_WSIO}, for workstation IO@. These\n-options are available under HP-UX and HI-UX@.\n-\n @item -mgnu-ld\n @opindex mgnu-ld\n Use options specific to GNU @command{ld}.\n@@ -25019,6 +24989,12 @@ configure option, GCC's program search path, and finally by the user's\n `gcc -print-prog-name=ld`}. This option is only available on the 64-bit\n HP-UX GCC, i.e.@: configured with @samp{hppa*64*-*-hpux*}.\n \n+@item -mlinker-opt\n+@opindex mlinker-opt\n+Enable the optimization pass in the HP-UX linker. Note this makes symbolic\n+debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9\n+linkers in which they give bogus error messages when linking some programs.\n+\n @item -mlong-calls\n @opindex mno-long-calls\n @opindex mlong-calls\n@@ -25047,6 +25023,69 @@ symbol-difference or pc-relative calls should be relatively small.\n However, an indirect call is used on 32-bit ELF systems in pic code\n and it is quite long.\n \n+@item -mlong-load-store\n+@opindex mlong-load-store\n+Generate 3-instruction load and store sequences as sometimes required by\n+the HP-UX 10 linker. This is equivalent to the @samp{+k} option to\n+the HP compilers.\n+\n+@item -mjump-in-delay\n+@opindex mjump-in-delay\n+This option is ignored and provided for compatibility purposes only.\n+\n+@item -mno-space-regs\n+@opindex mno-space-regs\n+@opindex mspace-regs\n+Generate code that assumes the target has no space registers. This allows\n+GCC to generate faster indirect calls and use unscaled index address modes.\n+\n+Such code is suitable for level 0 PA systems and kernels.\n+\n+@item -mordered\n+@opindex mordered\n+Assume memory references are ordered and barriers are not needed.\n+\n+@item -mportable-runtime\n+@opindex mportable-runtime\n+Use the portable calling conventions proposed by HP for ELF systems.\n+\n+@item -mschedule=@var{cpu-type}\n+@opindex mschedule\n+Schedule code according to the constraints for the machine type\n+@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}\n+@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer\n+to @file{/usr/lib/sched.models} on an HP-UX system to determine the\n+proper scheduling option for your machine. The default scheduling is\n+@samp{8000}.\n+\n+@item -msio\n+@opindex msio\n+Generate the predefine, @code{_SIO}, for server IO@. The default is\n+@option{-mwsio}. This generates the predefines, @code{__hp9000s700},\n+@code{__hp9000s700__} and @code{_WSIO}, for workstation IO@. These\n+options are available under HP-UX and HI-UX@.\n+\n+@item -msoft-float\n+@opindex msoft-float\n+Generate output containing library calls for floating point.\n+@strong{Warning:} the requisite libraries are not available for all HPPA\n+targets. Normally the facilities of the machine's usual C compiler are\n+used, but this cannot be done directly in cross-compilation. You must make\n+your own arrangements to provide suitable library functions for\n+cross-compilation.\n+\n+@option{-msoft-float} changes the calling convention in the output file;\n+therefore, it is only useful if you compile @emph{all} of a program with\n+this option. In particular, you need to compile @file{libgcc.a}, the\n+library that comes with GCC, with @option{-msoft-float} in order for\n+this to work.\n+\n+@item -msoft-mult\n+@opindex msoft-mult\n+Use software integer multiplication.\n+\n+This disables the use of the @code{xmpyu} instruction.\n+\n @item -munix=@var{unix-std}\n @opindex march\n Generate compiler predefines and select a startfile for the specified\ndiff --git a/libgcc/config.host b/libgcc/config.host\nindex d2087654c40..3e2c9109ab1 100644\n--- a/libgcc/config.host\n+++ b/libgcc/config.host\n@@ -633,7 +633,7 @@ h8300-*-linux*)\n \ttm_file=\"$tm_file h8300/h8300-lib.h\"\n \t;;\n hppa*64*-*-linux*)\n-\ttmake_file=\"$tmake_file pa/t-linux64 pa/t-dimode\"\n+\ttmake_file=\"$tmake_file pa/t-pa64-linux pa/t-dimode\"\n \ttmake_file=\"$tmake_file pa/t-softfp-sfdftf t-softfp\"\n \textra_parts=\"crtbegin.o crtbeginS.o crtbeginT.o crtend.o crtendS.o\"\n \t;;\n@@ -649,7 +649,7 @@ hppa*-*-linux*)\n \tmd_unwind_header=pa/linux-unwind.h\n \t;;\n hppa*64*-*-hpux11*)\n-\ttmake_file=\"$tmake_file pa/t-hpux pa/t-pa64 pa/t-dimode\"\n+\ttmake_file=\"$tmake_file pa/t-pa64-hpux pa/t-dimode\"\n \ttmake_file=\"$tmake_file pa/t-stublib t-libgcc-pic t-slibgcc\"\n \t# Set the libgcc version number\n \tif test x$ac_cv_sjlj_exceptions = xyes; then\ndiff --git a/libgcc/config/pa/linux-atomic.c b/libgcc/config/pa/linux-atomic.c\nindex 10d7f4217f5..1978e681f77 100644\n--- a/libgcc/config/pa/linux-atomic.c\n+++ b/libgcc/config/pa/linux-atomic.c\n@@ -32,6 +32,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n \n typedef unsigned char u8;\n typedef short unsigned int u16;\n+typedef unsigned int u32;\n #ifdef __LP64__\n typedef long unsigned int u64;\n #else\n@@ -115,6 +116,36 @@ __kernel_cmpxchg2 (volatile void *mem, const void *oldval, const void *newval,\n #define MASK_1 0xffu\n #define MASK_2 0xffffu\n \n+/* Load value with an atomic processor load if possible. */\n+#define ATOMIC_LOAD(TYPE, WIDTH)\t\t\t\t\t\\\n+ static inline TYPE\t\t\t\t\t\t\t\\\n+ atomic_load_##WIDTH (volatile void *ptr)\t\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ return *(volatile TYPE *)ptr;\t\t\t\t\t\\\n+ }\n+\n+#if defined(__LP64__) || defined(__SOFTFP__)\n+ATOMIC_LOAD (u64, 8)\n+#else\n+static inline u64\n+atomic_load_8 (volatile void *ptr)\n+{\n+ u64 result;\n+ double tmp;\n+\n+ asm volatile (\"{fldds|fldd} 0(%2),%1\\n\\t\"\n+\t\t\"{fstds|fstd} %1,-16(%%sp)\\n\\t\"\n+\t\t\"{ldws|ldw} -16(%%sp),%0\\n\\t\"\n+\t\t\"{ldws|ldw} -12(%%sp),%R0\"\n+\t\t: \"=r\" (result), \"=f\" (tmp) : \"r\" (ptr): \"memory\");\n+ return result;\n+}\n+#endif\n+\n+ATOMIC_LOAD (u32, 4)\n+ATOMIC_LOAD (u16, 2)\n+ATOMIC_LOAD (u8, 1)\n+\n #define FETCH_AND_OP_2(OP, PFX_OP, INF_OP, TYPE, WIDTH, INDEX)\t\t\\\n TYPE HIDDEN\t\t\t\t\t\t\t\t\\\n __sync_fetch_and_##OP##_##WIDTH (volatile void *ptr, TYPE val)\t\\\n@@ -123,7 +154,7 @@ __kernel_cmpxchg2 (volatile void *mem, const void *oldval, const void *newval,\n long failure;\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n- tmp = __atomic_load_n ((volatile TYPE *)ptr, __ATOMIC_RELAXED);\t\\\n+ tmp = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\t\t\\\n newval = PFX_OP (tmp INF_OP val);\t\t\t\t\t\\\n failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX);\t\t\\\n } while (failure != 0);\t\t\t\t\t\t\\\n@@ -160,7 +191,7 @@ FETCH_AND_OP_2 (nand, ~, &, u8, 1, 0)\n long failure;\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n- tmp = __atomic_load_n ((volatile TYPE *)ptr, __ATOMIC_RELAXED);\t\\\n+ tmp = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\t\t\\\n newval = PFX_OP (tmp INF_OP val);\t\t\t\t\t\\\n failure = __kernel_cmpxchg2 (ptr, &tmp, &newval, INDEX);\t\t\\\n } while (failure != 0);\t\t\t\t\t\t\\\n@@ -197,8 +228,7 @@ OP_AND_FETCH_2 (nand, ~, &, u8, 1, 0)\n long failure;\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n- tmp = __atomic_load_n ((volatile unsigned int *)ptr,\t\t\\\n-\t\t\t __ATOMIC_RELAXED);\t\t\t\t\\\n+ tmp = atomic_load_4 ((volatile unsigned int *)ptr);\t\t\\\n failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val));\t\\\n } while (failure != 0);\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n@@ -220,8 +250,7 @@ FETCH_AND_OP_WORD (nand, ~, &)\n long failure;\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n- tmp = __atomic_load_n ((volatile unsigned int *)ptr,\t\t\\\n-\t\t\t __ATOMIC_RELAXED);\t\t\t\t\\\n+ tmp = atomic_load_4 ((volatile unsigned int *)ptr);\t\t\\\n failure = __kernel_cmpxchg (ptr, tmp, PFX_OP (tmp INF_OP val));\t\\\n } while (failure != 0);\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n@@ -247,8 +276,7 @@ typedef unsigned char bool;\n \t\t\t\t\t\t\t\t\t\\\n while (1)\t\t\t\t\t\t\t\t\\\n {\t\t\t\t\t\t\t\t\t\\\n-\tactual_oldval = __atomic_load_n ((volatile TYPE *)ptr,\t\t\\\n-\t\t\t\t\t __ATOMIC_RELAXED);\t\t\\\n+\tactual_oldval = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\\\n \t\t\t\t\t\t\t\t\t\\\n \tif (__builtin_expect (oldval != actual_oldval, 0))\t\t\\\n \t return actual_oldval;\t\t\t\t\t\t\\\n@@ -281,8 +309,7 @@ __sync_val_compare_and_swap_4 (volatile void *ptr, unsigned int oldval,\n \n while (1)\n {\n- actual_oldval = __atomic_load_n ((volatile unsigned int *)ptr,\n-\t\t\t\t __ATOMIC_RELAXED);\n+ actual_oldval = atomic_load_4 ((volatile unsigned int *)ptr);\n \n if (__builtin_expect (oldval != actual_oldval, 0))\n \treturn actual_oldval;\n@@ -310,8 +337,7 @@ TYPE HIDDEN\t\t\t\t\t\t\t\t\\\n long failure;\t\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\t\\\n- oldval = __atomic_load_n ((volatile TYPE *)ptr,\t\t\t\\\n-\t\t\t\t__ATOMIC_RELAXED);\t\t\t\\\n+ oldval = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\t\\\n failure = __kernel_cmpxchg2 (ptr, &oldval, &val, INDEX);\t\t\\\n } while (failure != 0);\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\t\\\n@@ -322,14 +348,14 @@ SYNC_LOCK_TEST_AND_SET_2 (u64, 8, 3)\n SYNC_LOCK_TEST_AND_SET_2 (u16, 2, 1)\n SYNC_LOCK_TEST_AND_SET_2 (u8, 1, 0)\n \n-unsigned int HIDDEN\n+u32 HIDDEN\n __sync_lock_test_and_set_4 (volatile void *ptr, unsigned int val)\n {\n long failure;\n unsigned int oldval;\n \n do {\n- oldval = __atomic_load_n ((volatile unsigned int *)ptr, __ATOMIC_RELAXED);\n+ oldval = atomic_load_4 ((volatile unsigned int *)ptr);\n failure = __kernel_cmpxchg (ptr, oldval, val);\n } while (failure != 0);\n \n@@ -344,8 +370,7 @@ __sync_lock_test_and_set_4 (volatile void *ptr, unsigned int val)\n long failure;\t\t\t\t\t\t\\\n \t\t\t\t\t\t\t\t\\\n do {\t\t\t\t\t\t\t\\\n- oldval = __atomic_load_n ((volatile TYPE *)ptr,\t\t\\\n-\t\t\t\t__ATOMIC_RELAXED);\t\t\\\n+ oldval = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\\\n failure = __kernel_cmpxchg2 (ptr, &oldval, &val, INDEX);\t\\\n } while (failure != 0);\t\t\t\t\t\\\n }\n@@ -361,7 +386,27 @@ __sync_lock_release_4 (volatile void *ptr)\n unsigned int oldval;\n \n do {\n- oldval = __atomic_load_n ((volatile unsigned int *)ptr, __ATOMIC_RELAXED);\n+ oldval = atomic_load_4 ((volatile unsigned int *)ptr);\n failure = __kernel_cmpxchg (ptr, oldval, 0);\n } while (failure != 0);\n }\n+\n+#ifndef __LP64__\n+#define SYNC_LOCK_LOAD_2(TYPE, WIDTH, INDEX)\t\t\t\t\\\n+ TYPE __sync_lock_load_##WIDTH (volatile void *) HIDDEN;\t\t\\\n+ TYPE\t\t\t\t\t\t\t\t\t\\\n+ __sync_lock_load_##WIDTH (volatile void *ptr)\t\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE oldval;\t\t\t\t\t\t\t\\\n+ long failure;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ do {\t\t\t\t\t\t\t\t\\\n+ oldval = atomic_load_##WIDTH ((volatile TYPE *)ptr);\t\t\\\n+ failure = __kernel_cmpxchg2 (ptr, &oldval, &oldval, INDEX);\t\\\n+ } while (failure != 0);\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return oldval;\t\t\t\t\t\t\t\\\n+ }\n+\n+SYNC_LOCK_LOAD_2 (u64, 8, 3)\n+#endif\ndiff --git a/libgcc/config/pa/sync-libfuncs.c b/libgcc/config/pa/sync-libfuncs.c\nnew file mode 100644\nindex 00000000000..c70be0fde73\n--- /dev/null\n+++ b/libgcc/config/pa/sync-libfuncs.c\n@@ -0,0 +1,324 @@\n+/* PA-RISC sync libfunc support.\n+ Copyright (C) 2008-2023 Free Software Foundation, Inc.\n+ Based on code contributed by CodeSourcery for ARM EABI Linux.\n+ Modifications for PA Linux by Helge Deller \n+ Revised for general use by John David Anglin \n+\n+This file is part of GCC.\n+\n+GCC is free software; you can redistribute it and/or modify it under\n+the terms of the GNU General Public License as published by the Free\n+Software Foundation; either version 3, or (at your option) any later\n+version.\n+\n+GCC is distributed in the hope that it will be useful, but WITHOUT ANY\n+WARRANTY; without even the implied warranty of MERCHANTABILITY or\n+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License\n+for more details.\n+\n+Under Section 7 of GPL version 3, you are granted additional\n+permissions described in the GCC Runtime Library Exception, version\n+3.1, as published by the Free Software Foundation.\n+\n+You should have received a copy of the GNU General Public License and\n+a copy of the GCC Runtime Library Exception along with this program;\n+see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n+. */\n+\n+typedef unsigned char u8;\n+typedef short unsigned int u16;\n+typedef unsigned int u32;\n+#ifdef __LP64__\n+typedef long unsigned int u64;\n+#else\n+typedef long long unsigned int u64;\n+#endif\n+\n+/* PA-RISC 2.0 supports out-of-order execution for loads and stores.\n+ Thus, we need to synchonize memory accesses. For more info, see:\n+ \"Advanced Performance Features of the 64-bit PA-8000\" by Doug Hunt. */\n+\n+typedef volatile int __attribute__((aligned (16))) ldcw_t;\n+static ldcw_t __atomicity_lock = 1;\n+\n+/* We want default visibility for the sync routines. */\n+#undef VISIBILITY\n+#if defined(__hpux__) && !defined(__LP64__)\n+#define VISIBILITY\n+#else\n+#define VISIBILITY __attribute__ ((visibility (\"default\")))\n+#endif\n+\n+/* Perform ldcw operation in cache when possible. The ldcw instruction\n+ is a full barrier. */\n+#ifndef _PA_LDCW_INSN\n+# ifdef _PA_RISC2_0\n+# define _PA_LDCW_INSN \"ldcw,co\"\n+# else\n+# define _PA_LDCW_INSN \"ldcw\"\n+# endif\n+#endif\n+\n+static inline void\n+__sync_spin_lock (void)\n+{\n+ ldcw_t *lock = &__atomicity_lock;\n+ int tmp;\n+\n+ __asm__ __volatile__ (_PA_LDCW_INSN \" 0(%1),%0\\n\\t\"\n+\t\t\t\"cmpib,<>,n 0,%0,.+20\\n\\t\"\n+\t\t\t\"ldw,ma 0(%1),%0\\n\\t\"\n+\t\t\t\"cmpib,<> 0,%0,.-12\\n\\t\"\n+\t\t\t\"nop\\n\\t\"\n+\t\t\t\"b,n .-12\"\n+\t\t\t: \"=&r\" (tmp)\n+\t\t\t: \"r\" (lock)\n+\t\t\t: \"memory\");\n+}\n+\n+static inline void\n+__sync_spin_unlock (void)\n+{\n+ ldcw_t *lock = &__atomicity_lock;\n+ int tmp = 1;\n+\n+ /* Use ordered store for release. */\n+ __asm__ __volatile__ (\"stw,ma %1,0(%0)\"\n+\t\t\t: : \"r\" (lock), \"r\" (tmp) : \"memory\");\n+}\n+\n+/* Load value with an atomic processor load if possible. */\n+#define ATOMIC_LOAD(TYPE, WIDTH)\t\t\t\t\t\\\n+ static inline TYPE\t\t\t\t\t\t\t\\\n+ atomic_load_##WIDTH (volatile void *ptr)\t\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ return *(volatile TYPE *)ptr;\t\t\t\t\t\\\n+ }\n+\n+#if defined(__LP64__) || defined(__SOFTFP__)\n+ATOMIC_LOAD (u64, 8)\n+#else\n+static inline u64\n+atomic_load_8 (volatile void *ptr)\n+{\n+ u64 result;\n+ double tmp;\n+\n+ asm volatile (\"{fldds|fldd} 0(%2),%1\\n\\t\"\n+\t\t\"{fstds|fstd} %1,-16(%%sp)\\n\\t\"\n+\t\t\"{ldws|ldw} -16(%%sp),%0\\n\\t\"\n+\t\t\"{ldws|ldw} -12(%%sp),%R0\"\n+\t\t: \"=r\" (result), \"=f\" (tmp) : \"r\" (ptr): \"memory\");\n+ return result;\n+}\n+#endif\n+\n+ATOMIC_LOAD (u32, 4)\n+ATOMIC_LOAD (u16, 2)\n+ATOMIC_LOAD (u8, 1)\n+\n+/* Store value with an atomic processor store if possible. */\n+#define ATOMIC_STORE(TYPE, WIDTH)\t\t\t\t\t\\\n+ static inline void\t\t\t\t\t\t\t\\\n+ atomic_store_##WIDTH (volatile void *ptr, TYPE value)\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ *(volatile TYPE *)ptr = value;\t\t\t\t\t\\\n+ }\n+\n+#if defined(__LP64__) || defined(__SOFTFP__)\n+ATOMIC_STORE (u64, 8)\n+#else\n+static inline void\n+atomic_store_8 (volatile void *ptr, u64 value)\n+{\n+ double tmp;\n+\n+ asm volatile (\"stws|stw} %2,-16(%%sp)\\n\\t\"\n+\t\t\"{stws|stw} %R2,-12(%%sp)\\n\\t\"\n+\t\t\"{fldds|fldd} -16(%%sp),%1\\n\\t\"\n+\t\t\"{fstds|fstd} %1,0(%0)\"\n+\t\t: \"=m\" (ptr), \"=&f\" (tmp) : \"r\" (value): \"memory\");\n+}\n+#endif\n+\n+ATOMIC_STORE (u32, 4)\n+ATOMIC_STORE (u16, 2)\n+ATOMIC_STORE (u8, 1)\n+\n+#define FETCH_AND_OP(OP, PFX_OP, INF_OP, TYPE, WIDTH)\t\t\t\\\n+ TYPE VISIBILITY\t\t\t\t\t\t\t\\\n+ __sync_fetch_and_##OP##_##WIDTH (volatile void *ptr, TYPE val)\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE tmp, newval;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ tmp = atomic_load_##WIDTH (ptr);\t\t\t\t\t\\\n+ newval = PFX_OP (tmp INF_OP val);\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, newval);\t\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return tmp;\t\t\t\t\t\t\t\t\\\n+ }\n+\n+FETCH_AND_OP (add, , +, u64, 8)\n+FETCH_AND_OP (sub, , -, u64, 8)\n+FETCH_AND_OP (or, , |, u64, 8)\n+FETCH_AND_OP (and, , &, u64, 8)\n+FETCH_AND_OP (xor, , ^, u64, 8)\n+FETCH_AND_OP (nand, ~, &, u64, 8)\n+\n+FETCH_AND_OP (add, , +, u32, 4)\n+FETCH_AND_OP (sub, , -, u32, 4)\n+FETCH_AND_OP (or, , |, u32, 4)\n+FETCH_AND_OP (and, , &, u32, 4)\n+FETCH_AND_OP (xor, , ^, u32, 4)\n+FETCH_AND_OP (nand, ~, &, u32, 4)\n+\n+FETCH_AND_OP (add, , +, u16, 2)\n+FETCH_AND_OP (sub, , -, u16, 2)\n+FETCH_AND_OP (or, , |, u16, 2)\n+FETCH_AND_OP (and, , &, u16, 2)\n+FETCH_AND_OP (xor, , ^, u16, 2)\n+FETCH_AND_OP (nand, ~, &, u16, 2)\n+\n+FETCH_AND_OP (add, , +, u8, 1)\n+FETCH_AND_OP (sub, , -, u8, 1)\n+FETCH_AND_OP (or, , |, u8, 1)\n+FETCH_AND_OP (and, , &, u8, 1)\n+FETCH_AND_OP (xor, , ^, u8, 1)\n+FETCH_AND_OP (nand, ~, &, u8, 1)\n+\n+#define OP_AND_FETCH(OP, PFX_OP, INF_OP, TYPE, WIDTH)\t\t\t\\\n+ TYPE VISIBILITY \t\t\t\t\t\t\t\\\n+ __sync_##OP##_and_fetch_##WIDTH (volatile void *ptr, TYPE val)\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE tmp, newval;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ tmp = atomic_load_##WIDTH (ptr);\t\t\t\t\t\\\n+ newval = PFX_OP (tmp INF_OP val);\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, newval);\t\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return newval;\t\t\t\t\t\t\t\\\n+ }\n+\n+OP_AND_FETCH (add, , +, u64, 8)\n+OP_AND_FETCH (sub, , -, u64, 8)\n+OP_AND_FETCH (or, , |, u64, 8)\n+OP_AND_FETCH (and, , &, u64, 8)\n+OP_AND_FETCH (xor, , ^, u64, 8)\n+OP_AND_FETCH (nand, ~, &, u64, 8)\n+\n+OP_AND_FETCH (add, , +, u32, 4)\n+OP_AND_FETCH (sub, , -, u32, 4)\n+OP_AND_FETCH (or, , |, u32, 4)\n+OP_AND_FETCH (and, , &, u32, 4)\n+OP_AND_FETCH (xor, , ^, u32, 4)\n+OP_AND_FETCH (nand, ~, &, u32, 4)\n+\n+OP_AND_FETCH (add, , +, u16, 2)\n+OP_AND_FETCH (sub, , -, u16, 2)\n+OP_AND_FETCH (or, , |, u16, 2)\n+OP_AND_FETCH (and, , &, u16, 2)\n+OP_AND_FETCH (xor, , ^, u16, 2)\n+OP_AND_FETCH (nand, ~, &, u16, 2)\n+\n+OP_AND_FETCH (add, , +, u8, 1)\n+OP_AND_FETCH (sub, , -, u8, 1)\n+OP_AND_FETCH (or, , |, u8, 1)\n+OP_AND_FETCH (and, , &, u8, 1)\n+OP_AND_FETCH (xor, , ^, u8, 1)\n+OP_AND_FETCH (nand, ~, &, u8, 1)\n+\n+#define COMPARE_AND_SWAP(TYPE, WIDTH)\t\t\t\t\t\\\n+ TYPE VISIBILITY \t\t\t\t\t\t\t\\\n+ __sync_val_compare_and_swap_##WIDTH (volatile void *ptr, TYPE oldval,\t\\\n+\t\t\t\t TYPE newval)\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE actual_oldval;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ actual_oldval = atomic_load_##WIDTH (ptr);\t\t\t\t\\\n+ if (actual_oldval == oldval)\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, newval);\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return actual_oldval;\t\t\t\t\t\t\\\n+ }\t\t\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ _Bool VISIBILITY\t\t\t\t\t\t\t\\\n+ __sync_bool_compare_and_swap_##WIDTH (volatile void *ptr,\t\t\\\n+\t\t\t\t\tTYPE oldval, TYPE newval)\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE actual_oldval;\t\t\t\t\t\t\t\\\n+ _Bool result;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ actual_oldval = atomic_load_##WIDTH (ptr);\t\t\t\t\\\n+ result = (actual_oldval == oldval);\t\t\t\t\t\\\n+ if (result)\t\t\t\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, newval);\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return result;\t\t\t\t\t\t\t\\\n+ }\n+\n+COMPARE_AND_SWAP (u64, 8)\n+COMPARE_AND_SWAP (u32, 4)\n+COMPARE_AND_SWAP (u16, 2)\n+COMPARE_AND_SWAP (u8, 1)\n+\n+#define SYNC_LOCK_TEST_AND_SET(TYPE, WIDTH)\t\t\t\t\\\n+TYPE VISIBILITY \t\t\t\t\t\t\t\\\n+ __sync_lock_test_and_set_##WIDTH (volatile void *ptr, TYPE val)\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE oldval;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ oldval = atomic_load_##WIDTH (ptr);\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, val);\t\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return oldval;\t\t\t\t\t\t\t\\\n+ }\n+\n+SYNC_LOCK_TEST_AND_SET (u64, 8)\n+SYNC_LOCK_TEST_AND_SET (u32, 4)\n+SYNC_LOCK_TEST_AND_SET (u16, 2)\n+SYNC_LOCK_TEST_AND_SET (u8, 1)\n+\n+#define SYNC_LOCK_RELEASE(TYPE, WIDTH)\t\t\t\t\\\n+ void VISIBILITY\t\t\t\t\t\t\\\n+ __sync_lock_release_##WIDTH (volatile void *ptr)\t\t\\\n+ {\t\t\t\t\t\t\t\t\\\n+ TYPE val = 0;\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\\\n+ atomic_store_##WIDTH (ptr, val);\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\\\n+ }\n+\n+SYNC_LOCK_RELEASE (u64, 8)\n+SYNC_LOCK_RELEASE (u32, 4)\n+SYNC_LOCK_RELEASE (u16, 2)\n+SYNC_LOCK_RELEASE (u8, 1)\n+\n+#define SYNC_LOCK_LOAD(TYPE, WIDTH)\t\t\t\t\t\\\n+TYPE VISIBILITY __sync_lock_load_##WIDTH (volatile void *); \t\t\\\n+TYPE VISIBILITY \t\t\t\t\t\t\t\\\n+ __sync_lock_load_##WIDTH (volatile void *ptr)\t\t\t\t\\\n+ {\t\t\t\t\t\t\t\t\t\\\n+ TYPE oldval;\t\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ __sync_spin_lock();\t\t\t\t\t\t\t\\\n+ oldval = atomic_load_##WIDTH (ptr);\t\t\t\t\t\\\n+ __sync_spin_unlock();\t\t\t\t\t\t\\\n+\t\t\t\t\t\t\t\t\t\\\n+ return oldval;\t\t\t\t\t\t\t\\\n+ }\n+\n+SYNC_LOCK_LOAD (u64, 8)\n+SYNC_LOCK_LOAD (u32, 4)\n+SYNC_LOCK_LOAD (u16, 2)\n+SYNC_LOCK_LOAD (u8, 1)\ndiff --git a/libgcc/config/pa/t-netbsd b/libgcc/config/pa/t-netbsd\nindex 8b99068ce42..13943940a37 100644\n--- a/libgcc/config/pa/t-netbsd\n+++ b/libgcc/config/pa/t-netbsd\n@@ -7,3 +7,4 @@ LIB1ASMFUNCS = _divI _divU _remI _remU _div_const _mulI _dyncall\n HOST_LIBGCC2_CFLAGS += -DELF=1 -DLINUX=1\n \n LIB2ADD = $(srcdir)/config/pa/fptr.c\n+LIB2ADD_ST = $(srcdir)/config/pa/sync-libfuncs.c\ndiff --git a/libgcc/config/pa/t-openbsd b/libgcc/config/pa/t-openbsd\nindex 8b99068ce42..13943940a37 100644\n--- a/libgcc/config/pa/t-openbsd\n+++ b/libgcc/config/pa/t-openbsd\n@@ -7,3 +7,4 @@ LIB1ASMFUNCS = _divI _divU _remI _remU 100 50356 100 50204 100 152 1000k 3102 --:--:-- --:--:-- --:--:-- 1003k _div_const _mulI _dyncall\n HOST_LIBGCC2_CFLAGS += -DELF=1 -DLINUX=1\n \n LIB2ADD = $(srcdir)/config/pa/fptr.c\n+LIB2ADD_ST = $(srcdir)/config/pa/sync-libfuncs.c\ndiff --git a/libgcc/config/pa/t-pa64-hpux b/libgcc/config/pa/t-pa64-hpux\nnew file mode 100644\nindex 00000000000..55194e8f379\n--- /dev/null\n+++ b/libgcc/config/pa/t-pa64-hpux\n@@ -0,0 +1,4 @@\n+LIB2ADD = $(srcdir)/config/pa/quadlib.c\n+LIB2ADD_ST = $(srcdir)/config/pa/sync-libfuncs.c\n+\n+HOST_LIBGCC2_CFLAGS += -frandom-seed=fixed-seed -Dpa64=1 -DELF=1 -mlong-calls\ndiff --git a/libgcc/config/pa/t-pa64-linux b/libgcc/config/pa/t-pa64-linux\nnew file mode 100644\nindex 00000000000..026b48b02e5\n--- /dev/null\n+++ b/libgcc/config/pa/t-pa64-linux\n@@ -0,0 +1,8 @@\n+# Plug millicode routines into libgcc.a We want these on both native and\n+# cross compiles.\n+LIB1ASMSRC = pa/milli64.S\n+LIB1ASMFUNCS = _divI _divU _remI _remU _div_const _mulI\n+\n+HOST_LIBGCC2_CFLAGS += -Dpa64=1 -DELF=1 -DLINUX=1\n+\n+LIB2ADD_ST = $(srcdir)/config/pa/linux-atomic.c\n","prefixes":["committed"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE