Started by user snail Running as SYSTEM [EnvInject] - Loading node environment variables. Building remotely on docker-jenkins-agent in workspace /home/jenkins/agent/workspace/gcc-patch [WS-CLEANUP] Deleting project workspace... [WS-CLEANUP] Deferred wipeout is used... [WS-CLEANUP] Done The recommended git tool is: NONE using credential 0adb5fc7-caa2-429d-97d2-c7fa2fa1d884 Cloning the remote Git repository Using shallow clone with depth 1 Avoid fetching tags Cloning repository git@github.com:plctlab/patchwork-gcc.git > git init /home/jenkins/agent/workspace/gcc-patch # timeout=10 Fetching upstream changes from git@github.com:plctlab/patchwork-gcc.git > git --version # timeout=10 > git --version # 'git version 2.37.2' using GIT_SSH to set credentials patchwork github wangliu-iscas git ssh key Verifying host key using known hosts file, will automatically accept unseen keys > git fetch --no-tags --force --progress --depth=1 -- git@github.com:plctlab/patchwork-gcc.git +refs/heads/*:refs/remotes/origin/* # timeout=10 > git config remote.origin.url git@github.com:plctlab/patchwork-gcc.git # timeout=10 > git config --add remote.origin.fetch +refs/heads/*:refs/remotes/origin/* # timeout=10 Avoid second fetch > git rev-parse refs/remotes/origin/master^{commit} # timeout=10 Checking out Revision c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a (refs/remotes/origin/master) > git config core.sparsecheckout # timeout=10 > git checkout -f c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 Commit message: "RISC-V: Reorganize binary autovec testcases" > git rev-list --no-walk c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a # timeout=10 [EnvInject] - Mask passwords that will be passed as build parameters. [EnvInject] - Executing scripts and injecting environment variables after the SCM step. [EnvInject] - Injecting as environment variables the properties content GITHUB_REPO=https://github.com/plctlab/patchwork-gcc PATCHWORK_URL=https://patchwork.plctlab.org [EnvInject] - Variables injected successfully. [gcc-patch] $ /usr/bin/env bash /tmp/jenkins6766831915579429783.sh + git config pw.server https://patchwork.plctlab.org/api/1.2/ + git config pw.project gcc-patch + git config pw.token [*******] ++ date +%Y-%m + now_date=2023-12 ++ date +%Y + now_date_year=2023 + bundle_name=gcc-patch_2023-12 ++ curl -s -H 'Authorization: Token [*******]' 'https://patchwork.plctlab.org/api/1.2/bundles/?project=gcc-patch&per_page=999' + bundle_response=' Site Maintenance

We’ll be back soon!

Sorry for the inconvenience. We’re performing some maintenance at the moment.

' ++ echo ' Site Maintenance

We’ll be back soon!

Sorry for the inconvenience. We’re performing some maintenance at the moment.

++ jq -rc '.[].name'
' parse error: Invalid numeric literal at line 1, column 10 + bundle_name_list= + [[ '' =~ 2023-12 ]] + git-pw bundle create --public gcc-patch_2023-12 171822 Server error. Please report this issue to https://github.com/getpatchwork/patchwork Traceback (most recent call last): File "/usr/local/bin/git-pw", line 8, in sys.exit(cli()) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1130, in __call__ return self.main(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1055, in main rv = self.invoke(ctx) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1657, in invoke return _process_result(sub_ctx.command.invoke(sub_ctx)) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1657, in invoke return _process_result(sub_ctx.command.invoke(sub_ctx)) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 1404, in invoke return ctx.invoke(self.callback, **ctx.params) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 760, in invoke return __callback(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/decorators.py", line 26, in new_func return f(get_current_context(), *args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 418, in new_func return ctx.invoke(f, *args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/click/core.py", line 760, in invoke return __callback(*args, **kwargs) File "/usr/local/lib/python3.9/dist-packages/git_pw/bundle.py", line 232, in create_cmd bundle = api.create('bundles', data) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 363, in create return _post(url, data).json() File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 180, in _post _handle_error('create', exc) File "/usr/local/lib/python3.9/dist-packages/git_pw/api.py", line 178, in _post rsp.raise_for_status() File "/usr/local/lib/python3.9/dist-packages/requests/models.py", line 1021, in raise_for_status raise HTTPError(http_error_msg, response=self) requests.exceptions.HTTPError: 500 Server Error: Internal Server Error for url: https://patchwork.plctlab.org/api/1.2/bundles/ + git clone git@github.com:wangliu-iscas/Patchwork-Bundles.git Cloning into 'Patchwork-Bundles'... + cd Patchwork-Bundles + sed -i '/## 2023/a[2023-12](https://patchwork.plctlab.org/bundle/patchwork-bot/gcc-patch_2023-12) ' gcc-patch.md + git add gcc-patch.md + git commit -m 'gcc-patch add 2023-12 bundle' [main f18158b] gcc-patch add 2023-12 bundle 1 file changed, 1 insertion(+) + git push To github.com:wangliu-iscas/Patchwork-Bundles.git bb8c62b..f18158b main -> main + cd - /home/jenkins/agent/workspace/gcc-patch + git config pull.rebase false + git fetch origin master ssh: Could not resolve hostname github.com: Temporary failure in name resolution fatal: Could not read from remote repository. Please make sure you have the correct access rights and the repository exists. + git checkout master Switched to a new branch 'master' branch 'master' set up to track 'origin/master'. + git pull origin master From github.com:plctlab/patchwork-gcc * branch master -> FETCH_HEAD Already up to date. + git fetch origin upstream-master From github.com:plctlab/patchwork-gcc * branch upstream-master -> FETCH_HEAD + git checkout upstream-master Switched to a new branch 'upstream-master' branch 'upstream-master' set up to track 'origin/upstream-master'. + git remote add upstream https://github.com/gcc-mirror/gcc.git + git pull upstream master From https://github.com/gcc-mirror/gcc * branch master -> FETCH_HEAD * [new branch] master -> upstream/master fatal: refusing to merge unrelated histories + git push -u origin upstream-master Everything up-to-date branch 'upstream-master' set up to track 'origin/upstream-master'. + git checkout master Switched to branch 'master' Your branch is up to date with 'origin/master'. + git merge upstream-master fatal: refusing to merge unrelated histories + git push -u origin master Everything up-to-date branch 'master' set up to track 'origin/master'. + branchname=series70967-patch171822 ++ git branch -a ++ grep 'series70967-patch171822$' + checkbranch= + checkbranchresult=null + '[' null = series70967-patch171822 ']' + git checkout -b series70967-patch171822 Switched to a new branch 'series70967-patch171822' ++ curl https://patchwork.plctlab.org/api/1.2/series/70967/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 1393 100 1393 0 0 38694 0 --:--:-- --:--:-- --:--:-- 38694 + series_response='{"id":70967,"url":"https://patchwork.plctlab.org/api/1.2/series/70967/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=70967","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","date":"2023-11-30T10:38:36","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"Juzhe-Zhong","email":"juzhe.zhong@rivai.ai"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/70967/mbox/","cover_letter":null,"patches":[{"id":171822,"url":"https://patchwork.plctlab.org/api/1.2/patches/171822/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/","msgid":"<20231130103836.3913724-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-11-30T10:38:36","name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ echo '{"id":70967,"url":"https://patchwork.plctlab.org/api/1.2/series/70967/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=70967","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","date":"2023-11-30T10:38:36","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"Juzhe-Zhong","email":"juzhe.zhong@rivai.ai"},"version":2,"total":1,"received_total":1,"received_all":true,"mbox":"https://patchwork.plctlab.org/series/70967/mbox/","cover_letter":null,"patches":[{"id":171822,"url":"https://patchwork.plctlab.org/api/1.2/patches/171822/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/","msgid":"<20231130103836.3913724-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-11-30T10:38:36","name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/"}]}' ++ jq '.patches[] | (.id|tostring) + "," + .mbox' + patchid_patchurl='"171822,https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/"' + IFS=, + read -r series_patch_id series_patch_url + echo '"171822,https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/"' ++ sed 's/"//g' ++ echo '"171822' + series_patch_id=171822 ++ echo 'https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/"' ++ sed 's/"//g' + series_patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++ git rev-parse HEAD + commitid_before=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + eval '+++ declare -p bout bret declare -- bout="Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\"." declare -- bret="128" ++ berr='\''++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24159 100 24159 0 0 107k 0 --:--:-- --:--:-- --:--:-- 107k +++ bout='\''\'\'''\''Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''\'\'''\''\'\''\'\'''\'''\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\''\'\''\'\'''\'''\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\''\'\'''\'' +++ bret=128'\'' ++ declare -p berr declare -- berr="++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24159 100 24159 0 0 107k 0 --:--:-- --:--:-- --:--:-- 107k +++ bout='\''Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''\\'\'''\''git am --show-current-patch=diff'\''\\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run \"git am --continue\". If you prefer to skip this patch, run \"git am --skip\" instead. To restore the original branch and stop patching, run \"git am --abort\".'\'' +++ bret=128"' ++ +++ declare -p bout bret /tmp/jenkins6766831915579429783.sh: line 129: +++: command not found ++ declare -- 'bout=Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' ++ declare -- bret=128 ++ ++ 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24159 100 24159 0 0 107k 0 --:--:-- --:--:-- --:--:-- 107k +++ bout='\''Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' /tmp/jenkins6766831915579429783.sh: line 154: ++: command not found ++ ++ declare -p berr /tmp/jenkins6766831915579429783.sh: line 155: ++: command not found ++ declare -- 'berr=++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24159 100 24159 0 0 107k 0 --:--:-- --:--:-- --:--:-- 107k +++ bout='\''Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''\'\'''\''git am --show-current-patch=diff'\''\'\'''\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".'\'' +++ bret=128' ++ git rev-parse HEAD + commitid_after=c2d62cdd63f34c2f5187687d4c7b9f00f7d8fa3a + '[' 128 = 0 ']' + [[ ++++ git_am https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ patch_url=https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ ++++ git am -3 --empty=drop ++++ curl https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 24159 100 24159 0 0 107k 0 --:--:-- --:--:-- --:--:-- 107k +++ bout='Applying: RISC-V: Remove earlyclobber for wx/wf instructions. error: sha1 information is lacking or useless (gcc/config/riscv/vector.md). error: could not build fake ancestor hint: Use '\''git am --show-current-patch=diff'\'' to see the failed patch Patch failed at 0001 RISC-V: Remove earlyclobber for wx/wf instructions. When you have resolved this problem, run "git am --continue". If you prefer to skip this patch, run "git am --skip" instead. To restore the original branch and stop patching, run "git am --abort".' +++ bret=128 =~ sha1 information is lacking or useless ]] + submit_check warning Unresolved https://patchwork.plctlab.org/jenkins/job/gcc-patch/14356/consoleText 'Git am fail log' + check_state=warning + patch_state=Unresolved + repo_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/14356/consoleText + DESCRIPTION='Git am fail log' + curl -X POST -H 'Authorization: Token [*******]' -F state=warning -F target_url=https://patchwork.plctlab.org/jenkins/job/gcc-patch/14356/consoleText -F context=gcc-patch-check -F 'description=Git am fail log' https://patchwork.plctlab.org/api/patches/171822/checks/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0 100 970 100 429 100 541 3666 4623 --:--:-- --:--:-- --:--:-- 8290 {"id":16614,"url":"https://patchwork.plctlab.org/api/patches/171822/checks/16614/","user":{"id":1,"url":"https://patchwork.plctlab.org/api/users/1/","username":"snail","first_name":"","last_name":"","email":"wangliu@iscas.ac.cn"},"date":"2023-12-12T05:35:24.383383","state":"warning","target_url":"https://patchwork.plctlab.org/jenkins/job/gcc-patch/14356/consoleText","context":"gcc-patch-check","description":"Git am fail log"}+ curl -X PATCH -H 'Authorization: Token [*******]' -F state=Unresolved https://patchwork.plctlab.org/api/1.2/patches/171822/ % Total % Received % Xferd Average Speed Time Time Time Current Dload Upload Total Spent Left Speed 0 0 0 0 0 0 0 0 --:--:-- --:--:-- --:--:-- 0{"id":171822,"url":"https://patchwork.plctlab.org/api/1.2/patches/171822/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/","project":{"id":1,"url":"https://patchwork.plctlab.org/api/1.2/projects/1/","name":"gcc-patch","link_name":"gcc-patch","list_id":"gcc-patches.gcc.gnu.org","list_email":"gcc-patches@gcc.gnu.org","web_url":"https://github.com/wangliu-iscas/Patchwork-Bundles/blob/main/gcc-patch.md","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20231130103836.3913724-1-juzhe.zhong@rivai.ai>","list_archive_url":null,"date":"2023-11-30T10:38:36","name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","commit_ref":null,"pull_url":null,"state":"unresolved","archived":false,"hash":"ecefc495a502a3c1be4ac9dae955f95fc618f1a7","submitter":{"id":36,"url":"https://patchwork.plctlab.org/api/1.2/people/36/","name":"Juzhe-Zhong","email":"juzhe.zhong@rivai.ai"},"delegate":null,"mbox":"https://patchwork.plctlab.org/project/gcc-patch/patch/20231130103836.3913724-1-juzhe.zhong@rivai.ai/mbox/","series":[{"id":70967,"url":"https://patchwork.plctlab.org/api/1.2/series/70967/","web_url":"https://patchwork.plctlab.org/project/gcc-patch/list/?series=70967","date":"2023-11-30T10:38:36","name":"[V2] RISC-V: Remove earlyclobber for wx/wf instructions.","version":2,"mbox":"https://patchwork.plctlab.org/series/70967/mbox/"}],"comments":"https://patchwork.plctlab.org/api/patches/171822/comments/","check":"warning","checks":"https://patchwork.plctlab.org/api/patches/171822/checks/","tags":{},"headers":{"Return-Path":"","Delivered-To":["ouuuleilei@gmail.com","gcc-patches@gcc.gnu.org"],"Received":["by 2002:a59:bcd1:0:b0:403:3b70:6f57 with SMTP id r17csp289684vqy;\n Thu, 30 Nov 2023 02:39:11 -0800 (PST)","from server2.sourceware.org (server2.sourceware.org.\n [2620:52:3:1:0:246e:9693:128c])\n by mx.google.com with ESMTPS id\n qr20-20020a05620a391400b0077d94e32f22si800292qkn.280.2023.11.30.02.39.11\n for \n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 30 Nov 2023 02:39:11 -0800 (PST)","from server2.sourceware.org (localhost [IPv6:::1])\n\tby sourceware.org (Postfix) with ESMTP id 44B213857BB1\n\tfor ; Thu, 30 Nov 2023 10:39:11 +0000 (GMT)","from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239])\n by 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client-ip=2620:52:3:1:0:246e:9693:128c;","Authentication-Results":["mx.google.com;\n arc=pass (i=1);\n spf=pass (google.com: domain of\n gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates\n 2620:52:3:1:0:246e:9693:128c as permitted sender)\n smtp.mailfrom=\"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org\"","sourceware.org;\n dmarc=none (p=none dis=none) header.from=rivai.ai","sourceware.org; spf=pass smtp.mailfrom=rivai.ai","server2.sourceware.org;\n arc=none smtp.remote-ip=18.169.211.239"],"X-Original-To":"gcc-patches@gcc.gnu.org","DMARC-Filter":"OpenDMARC Filter v1.4.2 sourceware.org ECAFE3858D37","ARC-Filter":"OpenARC Filter v1.0.0 sourceware.org ECAFE3858D37","X-QQ-mid":"bizesmtp82t1701340718t6fbya7l","X-QQ-SSF":"01400000000000G0V000000A0000000","X-QQ-FEAT":"kN2ypXZVqgzZNoAlZeScQ0/JnUH8HilEhxel3TENiK6qPK8WuJnDFrkEzid3f\n iynjemBmKEIa6zEPFchC/zWjgD4ySwaTtJ1zOXkTCWHhKDjK1OJRZ1YSnix37DeLR5Qjvd8\n YRXFi9aMFIKBO7YZ3kVUHdsq1x1TePUt3k2VcTEfPnAMH/bXdKM8AXbIILQjFVoLXyzB/lP\n VUi5faFDR4zni+aIk8tCAFcZ+s6THYbzP3zwqryCidqEDIiBZ4SNhSAZOPD8CKmmWB3Iu1P\n SaivMIzInZow+3PAm3Gmh+uU/rnIhsB7LbFYS5M+W+c2pQEL+t31tc2vQGYgY3kSqXaa67K\n L+Ltoj97Rn7tNg5hcvJRQPKK9h6b0n7Yw7DbNWMsXgsBwtbDwkbGM5PCuQnGoQdMPXzyYxF\n QZT1krB9F3I=","X-QQ-GoodBg":"2","X-BIZMAIL-ID":"1695146524101988222","From":"Juzhe-Zhong ","To":"gcc-patches@gcc.gnu.org","Cc":"kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com,\n rdapp.gcc@gmail.com, Juzhe-Zhong ","Subject":"[PATCH V2] RISC-V: Remove earlyclobber for wx/wf instructions.","Date":"Thu, 30 Nov 2023 18:38:36 +0800","Message-Id":"<20231130103836.3913724-1-juzhe.zhong@rivai.ai>","X-Mailer":"git-send-email 2.36.3","MIME-Version":"1.0","Content-Transfer-Encoding":"8bit","X-QQ-SENDSIZE":"520","Feedback-ID":"bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0","X-Spam-Status":"No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0,\n KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE,\n RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6","X-Spam-Checker-Version":"SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org","X-BeenThere":"gcc-patches@gcc.gnu.org","X-Mailman-Version":"2.1.30","Precedence":"list","List-Id":"Gcc-patches mailing list ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org","X-getmail-retrieved-from-mailbox":"INBOX","X-GMAIL-THRID":"1783985079948086571","X-GMAIL-MSGID":"1783985079948086571"},"content":"While working on overlap for widening instructions, I realize that we set\nvwadd.wx/vfwadd.wf as earlyclobber which is incorrect.\n\nSince according to RVV ISA:\n\"The destination EEW equals the source EEW.\"\n\nvwadd.vx widens the first source operand (i.e. 2 * source EEW = dest EEW) while\nvwadd.wx only widens the second/scalar source operand.\n\nTherefore overlap is legal for wx but not for vx.\n\nBefore this patch (heave spillings):\n\n csrr a5,vlenb\n slli a5,a5,1\n addi a5,a5,64\n vfwadd.wf v2,v14,fs0\n add a5,a5,sp\n vs2r.v v2,0(a5)\n vl2re32.v v2,0(a1)\n vfwadd.wf v14,v12,fs0\n vfwadd.wf v12,v10,fs0\n vfwadd.wf v10,v8,fs0\n vfwadd.wf v8,v6,fs0\n vfwadd.wf v6,v4,fs0\n vfwadd.wf v4,v2,fs0\n vfwadd.wf v2,v16,fs0\n vfwadd.wf v16,v18,fs0\n vfwadd.wf v18,v20,fs0\n vfwadd.wf v20,v22,fs0\n vfwadd.wf v22,v24,fs0\n vfwadd.wf v24,v26,fs0\n vfwadd.wf v26,v28,fs0\n vfwadd.wf v28,v30,fs0\n vfwadd.wf v30,v0,fs0\n nop\n vsetvli zero,zero,e32,m2,ta,ma\n csrr a5,vlenb\n\nAfter this patch (no spillings):\n\n \tvfwadd.wf\tv16,v16,fs0\n\tvfwadd.wf\tv14,v14,fs0\n\tvfwadd.wf\tv12,v12,fs0\n\tvfwadd.wf\tv10,v10,fs0\n\tvfwadd.wf\tv8,v8,fs0\n\tvfwadd.wf\tv6,v6,fs0\n\tvfwadd.wf\tv4,v4,fs0\n\tvfwadd.wf\tv2,v2,fs0\n\tvfwadd.wf\tv18,v18,fs0\n\tvfwadd.wf\tv20,v20,fs0\n\tvfwadd.wf\tv22,v22,fs0\n\tvfwadd.wf\tv24,v24,fs0\n\tvfwadd.wf\tv26,v26,fs0\n\tvfwadd.wf\tv28,v28,fs0\n\tvfwadd.wf\tv30,v30,fs0\n\tvfwadd.wf\tv0,v0,fs0\n\nConfirm the codegen above run successfully on both SPIKE/QEMU.\n\n\tPR target/112431\n\ngcc/ChangeLog:\n\n\t* config/riscv/vector.md: Remove earlyclobber for wx/wf instructions.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/riscv/rvv/base/pr112431-19.c: New test.\n\t* gcc.target/riscv/rvv/base/pr112431-20.c: New test.\n\t* gcc.target/riscv/rvv/base/pr112431-21.c: New test.\n\n---\n gcc/config/riscv/vector.md | 4 +-\n .../gcc.target/riscv/rvv/base/pr112431-19.c | 103 +++++++++++++++++\n .../gcc.target/riscv/rvv/base/pr112431-20.c | 103 +++++++++++++++++\n .../gcc.target/riscv/rvv/base/pr112431-21.c | 106 ++++++++++++++++++\n 4 files changed, 314 insertions(+), 2 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-19.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-20.c\n create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c","diff":"diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md\nindex e5d62c6e58b..b47b9742b62 100644\n--- a/gcc/config/riscv/vector.md\n+++ b/gcc/config/riscv/vector.md\n@@ -3833,7 +3833,7 @@\n (set_attr \"mode\" \"\")])\n \n (define_insn \"@pred_single_widen__scalar\"\n- [(set (match_operand:VWEXTI 0 \"register_operand\" \"=&vr,&vr\")\n+ [(set (match_operand:VWEXTI 0 \"register_operand\" \"=vr, vr\")\n \t(if_then_else:VWEXTI\n \t (unspec:\n \t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\n@@ -7114,7 +7114,7 @@\n \t(symbol_ref \"riscv_vector::get_frm_mode (operands[9])\"))])\n \n (define_insn \"@pred_single_widen__scalar\"\n- [(set (match_operand:VWEXTF 0 \"register_operand\" \"=&vr, &vr\")\n+ [(set (match_operand:VWEXTF 0 \"register_operand\" \"=vr, vr\")\n \t(if_then_else:VWEXTF\n \t (unspec:\n \t [(match_operand: 1 \"vector_mask_operand\" \"vmWc1,vmWc1\")\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-19.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-19.c\nnew file mode 100644\nindex 00000000000..affe1aaf4f2\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-19.c\n@@ -0,0 +1,103 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcv -mabi=lp64d -O3\" } */\n+\n+#include \"riscv_vector.h\"\n+\n+size_t __attribute__ ((noinline))\n+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,\n+\t size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,\n+\t size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,\n+\t size_t sum15)\n+{\n+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9\n+\t + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;\n+}\n+\n+size_t __attribute__ ((noinline))\n+foo (short const *buf, size_t len)\n+{\n+ size_t sum = 0;\n+ size_t vl = 4;\n+ const short *it = buf;\n+ for (int i = 0; i < len; i++)\n+ {\n+ vint16m2_t v0 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v1 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v2 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v3 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v4 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v5 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v6 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v7 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v8 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v9 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v10 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v11 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v12 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v13 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v14 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v15 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+\n+ asm volatile(\"nop\" ::: \"memory\");\n+ vint16m2_t vw0 = __riscv_vwadd_wx_i16m2 (v0, 55, vl);\n+ vint16m2_t vw1 = __riscv_vwadd_wx_i16m2 (v1, 55, vl);\n+ vint16m2_t vw2 = __riscv_vwadd_wx_i16m2 (v2, 55, vl);\n+ vint16m2_t vw3 = __riscv_vwadd_wx_i16m2 (v3, 55, vl);\n+ vint16m2_t vw4 = __riscv_vwadd_wx_i16m2 (v4, 55, vl);\n+ vint16m2_t vw5 = __riscv_vwadd_wx_i16m2 (v5, 55, vl);\n+ vint16m2_t vw6 = __riscv_vwadd_wx_i16m2 (v6, 55, vl);\n+ vint16m2_t vw7 = __riscv_vwadd_wx_i16m2 (v7, 55, vl);\n+ vint16m2_t vw8 = __riscv_vwadd_wx_i16m2 (v8, 55, vl);\n+ vint16m2_t vw9 = __riscv_vwadd_wx_i16m2 (v9, 55, vl);\n+ vint16m2_t vw10 = __riscv_vwadd_wx_i16m2 (v10, 55, vl);\n+ vint16m2_t vw11 = __riscv_vwadd_wx_i16m2 (v11, 55, vl);\n+ vint16m2_t vw12 = __riscv_vwadd_wx_i16m2 (v12, 55, vl);\n+ vint16m2_t vw13 = __riscv_vwadd_wx_i16m2 (v13, 55, vl);\n+ vint16m2_t vw14 = __riscv_vwadd_wx_i16m2 (v14, 55, vl);\n+ vint16m2_t vw15 = __riscv_vwadd_wx_i16m2 (v15, 55, vl);\n+\n+ asm volatile(\"nop\" ::: \"memory\");\n+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);\n+ size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);\n+ size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);\n+ size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);\n+ size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);\n+ size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);\n+ size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);\n+ size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);\n+ size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);\n+ size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);\n+ size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);\n+ size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);\n+ size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);\n+ size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);\n+ size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);\n+ size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);\n+\n+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,\n+\t\t sum9, sum10, sum11, sum12, sum13, sum14, sum15);\n+ }\n+ return sum;\n+}\n+\n+/* { dg-final { scan-assembler-not {vmv1r} } } */\n+/* { dg-final { scan-assembler-not {vmv2r} } } */\n+/* { dg-final { scan-assembler-not {vmv4r} } } */\n+/* { dg-final { scan-assembler-not {vmv8r} } } */\n+/* { dg-final { scan-assembler-not {csrr} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-20.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-20.c\nnew file mode 100644\nindex 00000000000..72f3644e592\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-20.c\n@@ -0,0 +1,103 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-march=rv64gcv_zvfh_zfh -mabi=lp64d -O3\" } */\n+\n+#include \"riscv_vector.h\"\n+\n+size_t __attribute__ ((noinline))\n+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,\n+\t size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,\n+\t size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,\n+\t size_t sum15)\n+{\n+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9\n+\t + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;\n+}\n+\n+size_t __attribute__ ((noinline))\n+foo (float const *buf, size_t len)\n+{\n+ size_t sum = 0;\n+ size_t vl = 4;\n+ const float *it = buf;\n+ for (int i = 0; i < len; i++)\n+ {\n+ vfloat32m2_t v0 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v1 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v2 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v3 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v4 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v5 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v6 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v7 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v8 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v9 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v10 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v11 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v12 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v13 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v14 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+ vfloat32m2_t v15 = __riscv_vle32_v_f32m2 (it, vl);\n+ it += vl;\n+\n+ asm volatile(\"nop\" ::: \"memory\");\n+ vfloat32m2_t vw0 = __riscv_vfwadd_wf_f32m2 (v0, 55, vl);\n+ vfloat32m2_t vw1 = __riscv_vfwadd_wf_f32m2 (v1, 55, vl);\n+ vfloat32m2_t vw2 = __riscv_vfwadd_wf_f32m2 (v2, 55, vl);\n+ vfloat32m2_t vw3 = __riscv_vfwadd_wf_f32m2 (v3, 55, vl);\n+ vfloat32m2_t vw4 = __riscv_vfwadd_wf_f32m2 (v4, 55, vl);\n+ vfloat32m2_t vw5 = __riscv_vfwadd_wf_f32m2 (v5, 55, vl);\n+ vfloat32m2_t vw6 = __riscv_vfwadd_wf_f32m2 (v6, 55, vl);\n+ vfloat32m2_t vw7 = __riscv_vfwadd_wf_f32m2 (v7, 55, vl);\n+ vfloat32m2_t vw8 = __riscv_vfwadd_wf_f32m2 (v8, 55, vl);\n+ vfloat32m2_t vw9 = __riscv_vfwadd_wf_f32m2 (v9, 55, vl);\n+ vfloat32m2_t vw10 = __riscv_vfwadd_wf_f32m2 (v10, 55, vl);\n+ vfloat32m2_t vw11 = __riscv_vfwadd_wf_f32m2 (v11, 55, vl);\n+ vfloat32m2_t vw12 = __riscv_vfwadd_wf_f32m2 (v12, 55, vl);\n+ vfloat32m2_t vw13 = __riscv_vfwadd_wf_f32m2 (v13, 55, vl);\n+ vfloat32m2_t vw14 = __riscv_vfwadd_wf_f32m2 (v14, 55, vl);\n+ vfloat32m2_t vw15 = __riscv_vfwadd_wf_f32m2 (v15, 55, vl);\n+\n+ asm volatile(\"nop\" ::: \"memory\");\n+ size_t sum0 = __riscv_vfmv_f_s_f32m2_f32 (vw0);\n+ size_t sum1 = __riscv_vfmv_f_s_f32m2_f32 (vw1);\n+ size_t sum2 = __riscv_vfmv_f_s_f32m2_f32 (vw2);\n+ size_t sum3 = __riscv_vfmv_f_s_f32m2_f32 (vw3);\n+ size_t sum4 = __riscv_vfmv_f_s_f32m2_f32 (vw4);\n+ size_t sum5 = __riscv_vfmv_f_s_f32m2_f32 (vw5);\n+ size_t sum6 = __riscv_vfmv_f_s_f32m2_f32 (vw6);\n+ size_t sum7 = __riscv_vfmv_f_s_f32m2_f32 (vw7);\n+ size_t sum8 = __riscv_vfmv_f_s_f32m2_f32 (vw8);\n+ size_t sum9 = __riscv_vfmv_f_s_f32m2_f32 (vw9);\n+ size_t sum10 = __riscv_vfmv_f_s_f32m2_f32 (vw10);\n+ size_t sum11 = __riscv_vfmv_f_s_f32m2_f32 (vw11);\n+ size_t sum12 = __riscv_vfmv_f_s_f32m2_f32 (vw12);\n+ size_t sum13 = __riscv_vfmv_f_s_f32m2_f32 (vw13);\n+ size_t sum14 = __riscv_vfmv_f_s_f32m2_f32 (vw14);\n+ size_t sum15 = __riscv_vfmv_f_s_f32m2_f32 (vw15);\n+\n+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,\n+\t\t sum9, sum10, sum11, sum12, sum13, sum14, sum15);\n+ }\n+ return sum;\n+}\n+\n+/* { dg-final { scan-assembler-not {vmv1r} } } */\n+/* { dg-final { scan-assembler-not {vmv2r} } } */\n+/* { dg-final { scan-assembler-not {vmv4r} } } */\n+/* { dg-final { scan-assembler-not {vmv8r} } } */\n+/* { dg-final { scan-assembler-not {csrr} } } */\ndiff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c\nnew file mode 100644\nindex 00000000000..3e43c949509\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-21.c\n@@ -0,0 +1,106 @@\n+/* { dg-do run { target { riscv_v } } } */\n+/* { dg-additional-options \"-O3 -ansi -pedantic-errors -std=gnu99\" } */\n+\n+#include \n+\n+size_t __attribute__ ((noinline))\n+sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,\n+ size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,\n+ size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,\n+ size_t sum15)\n+{\n+ return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 + sum9\n+ + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;\n+}\n+\n+size_t __attribute__ ((noinline))\n+foo (short const *buf, size_t len)\n+{\n+ size_t sum = 0;\n+ size_t vl = 4;\n+ const short *it = buf;\n+ for (int i = 0; i < len; i++)\n+ {\n+ vint16m2_t v0 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v1 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v2 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v3 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v4 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v5 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v6 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v7 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v8 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v9 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v10 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v11 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v12 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v13 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v14 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+ vint16m2_t v15 = __riscv_vle16_v_i16m2 (it, vl);\n+ it += vl;\n+\n+ asm volatile (\"\" ::: \"memory\");\n+ vint16m2_t vw0 = __riscv_vwadd_wx_i16m2 (v0, 55, vl);\n+ vint16m2_t vw1 = __riscv_vwadd_wx_i16m2 (v1, 55, vl);\n+ vint16m2_t vw2 = __riscv_vwadd_wx_i16m2 (v2, 55, vl);\n+ vint16m2_t vw3 = __riscv_vwadd_wx_i16m2 (v3, 55, vl);\n+ vint16m2_t vw4 = __riscv_vwadd_wx_i16m2 (v4, 55, vl);\n+ vint16m2_t vw5 = __riscv_vwadd_wx_i16m2 (v5, 55, vl);\n+ vint16m2_t vw6 = __riscv_vwadd_wx_i16m2 (v6, 55, vl);\n+ vint16m2_t vw7 = __riscv_vwadd_wx_i16m2 (v7, 55, vl);\n+ vint16m2_t vw8 = __riscv_vwadd_wx_i16m2 (v8, 55, vl);\n+ vint16m2_t vw9 100 26420 100 26270 100 150 382k 2238 --:--:-- --:--:-- --:--:-- 385k = __riscv_vwadd_wx_i16m2 (v9, 55, vl);\n+ vint16m2_t vw10 = __riscv_vwadd_wx_i16m2 (v10, 55, vl);\n+ vint16m2_t vw11 = __riscv_vwadd_wx_i16m2 (v11, 55, vl);\n+ vint16m2_t vw12 = __riscv_vwadd_wx_i16m2 (v12, 55, vl);\n+ vint16m2_t vw13 = __riscv_vwadd_wx_i16m2 (v13, 55, vl);\n+ vint16m2_t vw14 = __riscv_vwadd_wx_i16m2 (v14, 55, vl);\n+ vint16m2_t vw15 = __riscv_vwadd_wx_i16m2 (v15, 55, vl);\n+\n+ asm volatile (\"\" ::: \"memory\");\n+ size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);\n+ size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);\n+ size_t sum2 = __riscv_vmv_x_s_i16m2_i16 (vw2);\n+ size_t sum3 = __riscv_vmv_x_s_i16m2_i16 (vw3);\n+ size_t sum4 = __riscv_vmv_x_s_i16m2_i16 (vw4);\n+ size_t sum5 = __riscv_vmv_x_s_i16m2_i16 (vw5);\n+ size_t sum6 = __riscv_vmv_x_s_i16m2_i16 (vw6);\n+ size_t sum7 = __riscv_vmv_x_s_i16m2_i16 (vw7);\n+ size_t sum8 = __riscv_vmv_x_s_i16m2_i16 (vw8);\n+ size_t sum9 = __riscv_vmv_x_s_i16m2_i16 (vw9);\n+ size_t sum10 = __riscv_vmv_x_s_i16m2_i16 (vw10);\n+ size_t sum11 = __riscv_vmv_x_s_i16m2_i16 (vw11);\n+ size_t sum12 = __riscv_vmv_x_s_i16m2_i16 (vw12);\n+ size_t sum13 = __riscv_vmv_x_s_i16m2_i16 (vw13);\n+ size_t sum14 = __riscv_vmv_x_s_i16m2_i16 (vw14);\n+ size_t sum15 = __riscv_vmv_x_s_i16m2_i16 (vw15);\n+\n+ sum += sumation (sum0, sum1, sum2, sum3, sum4, sum5, sum6, sum7, sum8,\n+ sum9, sum10, sum11, sum12, sum13, sum14, sum15);\n+ }\n+ return sum;\n+}\n+\n+int\n+main (int in, char **out)\n+{\n+ short const buf[1000];\n+ int i = foo (buf, 4);\n+ **out = i;\n+ return 0;\n+}\n","prefixes":["V2"]}+ exit 1 Build step 'Execute shell' marked build as failure Finished: FAILURE